MIPS%Assembly% E155%
|
|
- Anthony Tyler
- 1 years ago
- Views:
Transcription
1 MIPS%Assembly% E155%
2 Outline MIPS Architecture ISA Instruction types Machine codes Procedure call Stack 2
3 The MIPS Register Set Name Register Number Usage $0 0 the constant value 0 $at 1 assembler temporary $v0-$v1 2-3 procedure return values $a0-$a3 4-7 procedure arguments $t0-$t temporaries $s0-$s saved variables $t8-$t more temporaries $k0-$k OS temporaries $gp 28 global pointer $sp 29 stack pointer $fp 30 frame pointer $ra 31 procedure return address 3
4 R-Type Register-type 3 register operands: rs, rt: source registers rd: destination register Other fields: op: the operation code or opcode (0 for R-type instructions) funct: the function together, the opcode and function tell the computer what operation to perform shamt: the shift amount for shift instructions, otherwise it s 0 R-Type op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 4
5 I-Type Immediate-type 3 operands: rs, rt: register operands imm: 16-bit two s complement immediate Other fields: op: the opcode Simplicity favors regularity: all instructions have opcode Operation is completely determined by the opcode I-Type op rs rt imm 6 bits 5 bits 5 bits 16 bits 5
6 Machine Language: J-Type Jump-type 26-bit address operand (addr) Used for jump instructions (j) J-Type op addr 6 bits 26 bits 6
7 Review: Instruction Formats R-Type op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits I-Type op rs rt imm 6 bits 5 bits 5 bits 16 bits J-Type op addr 6 bits 26 bits 7
8 Logical Instructions and, or, xor, nor and: useful for masking bits Masking all but the least significant byte of a value: 0xF234012F AND 0x000000FF = 0x F or: useful for combining bit fields Combine 0xF with 0x000012BC: 0xF OR 0x000012BC = 0xF23412BC nor: useful for inverting bits: A NOR $0 = NOT A andi, ori, xori 16-bit immediate is zero-extended (not sign-extended) nori not needed 8
9 Logical Instruction Examples Source Registers Assembly Code and $s3, $s1, $s2 or $s4, $s1, $s2 xor $s5, $s1, $s2 nor $s6, $s1, $s2 $s1 $s2 $s3 $s4 $s5 $s Result
10 Shift Instructions sll: shift left logical Example: sll $t0, $t1, 5 # $t0 <= $t1 << 5 srl: shift right logical Example: srl $t0, $t1, 5 # $t0 <= $t1 >> 5 sra: shift right arithmetic Example: sra $t0, $t1, 5 # $t0 <= $t1 >>> 5 Variable shift instructions: sllv: shift left logical variable Example: sllv $t0, $t1, $t2 # $t0 <= $t1 << $t2 srlv: shift right logical variable Example: srlv $t0, $t1, $t2 # $t0 <= $t1 >> $t2 srav: shift right arithmetic variable Example: srav $t0, $t1, $t2 # $t0 <= $t1 >>> $t2 10
11 Shift Instructions Assembly Code sll $t0, $s1, 2 Field Values op rs rt rd shamt funct srl $s2, $s1, 2 sra $s3, $s1, bits 5 bits 5 bits 5 bits 5 bits 6 bits Machine Code op rs rt rd shamt funct bits 5 bits 5 bits 5 bits 5 bits 6 bits (0x ) (0x ) (0x ) 11
12 Generating Constants 16-bit constants using addi: High-level code // int is a 32-bit signed word int a = 0x4f3c; MIPS assembly code # $s0 = a addi $s0, $0, 0x4f3c 32-bit constants using load upper immediate (lui) and ori: (lui loads the 16-bit immediate into the upper half of the register and sets the lower half to 0.) High-level code int a = 0xFEDC8765; MIPS assembly code # $s0 = a lui $s0, 0xFEDC ori $s0, $s0, 0x
13 The Stored Program Assembly Code lw $t2, 32($0) add $s0, $s1, $s2 addi $t0, $s3, -12 sub $t0, $t3, $t5 Machine Code 0x8C0A0020 0x x2268FFF4 0x016D4022 Stored Program Address Instructions C D F F F C 0 A PC Main Memory 13
14 Branching Allows a program to execute instructions out of sequence. Types of branches: Conditional branches branch if equal (beq) branch if not equal (bne) Unconditional branches jump (j) jump register (jr) jump and link (jal) 14
15 Conditional Branching (beq) # MIPS assembly addi $s0, $0, 4 # $s0 = = 4 addi $s1, $0, 1 # $s1 = = 1 sll $s1, $s1, 2 # $s1 = 1 << 2 = 4 beq $s0, $s1, target # branch is taken addi $s1, $s1, 1 sub $s1, $s1, $s0 # not executed # not executed target: # label add $s1, $s1, $s0 # $s1 = = 8 Labels indicate instruction locations in a program. They cannot use reserved words and must be followed by a colon (:). 16
16 Branch Not Taken # MIPS assembly addi $s0, $0, 4 # $s0 = = 4 addi $s1, $0, 1 # $s1 = = 1 sll $s1, $s1, 2 # $s1 = 1 << 2 = 4 bne $s0, $s1, target # branch not taken addi $s1, $s1, 1 # $s1 = = 5 sub $s1, $s1, $s0 # $s1 = 5 4 = 1 target: add $s1, $s1, $s0 # $s1 = = 5 16
17 Unconditional Branching / Jumping (j) # MIPS assembly addi $s0, $0, 4 # $s0 = 4 addi $s1, $0, 1 # $s1 = 1 j target # jump to target sra $s1, $s1, 2 # not executed addi $s1, $s1, 1 # not executed sub $s1, $s1, $s0 # not executed target: add $s1, $s1, $s0 # $s1 = = 5 16
18 MIPS assembly code # $s0 = y Procedure Call main:... addi $a0, $0, 2 # argument 0 = 2 addi $a1, $0, 3 # argument 1 = 3 addi $a2, $0, 4 # argument 2 = 4 addi $a3, $0, 5 # argument 3 = 5 jal diffofsums # call procedure add $s0, $v0, $0 # y = returned value... # jal: jumps to diffofsums and saves PC+4 in the # return address register ($ra). # $s0 = result diffofsums: # jr $ra: jumps to address in $ra. add $t0, $a0, $a1 # $t0 = f + g add $t1, $a2, $a3 # $t1 = h + i sub $s0, $t0, $t1 # result = (f + g) - (h + i) add $v0, $s0, $0 # put return value in $v0 jr $ra # return to caller 18
19 Stack # $s0 = result diffofsums: addi $sp, $sp, -12 # make space on stack # to store 3 registers sw $s0, 8($sp) # save $s0 on stack sw $t0, 4($sp) # save $t0 on stack sw $t1, 0($sp) # save $t1 on stack add $t0, $a0, $a1 # $t0 = f + g add $t1, $a2, $a3 # $t1 = h + i sub $s0, $t0, $t1 # result = (f + g) - (h + i) add $v0, $s0, $0 # put return value in $v0 lw $t1, 0($sp) # restore $t1 from stack lw $t0, 4($sp) # restore $t0 from stack lw $s0, 8($sp) # restore $s0 from stack addi $sp, $sp, 12 # deallocate stack space jr $ra # return to caller 19
20 Procedure Call Caller Put arguments in $a0-$a3 Save any registers that are needed ($ra, maybe $t0-t9) jal callee Restore registers Look for result in $v0 Callee Save registers that might be disturbed ($s0-$s7) Perform procedure Put result in $v0 Restore registers jr $ra 20
ENGN1640: Design of Computing Systems Topic 03: Instruction Set Architecture Design
ENGN1640: Design of Computing Systems Topic 03: Instruction Set Architecture Design Professor Sherief Reda http://scale.engin.brown.edu School of Engineering Brown University Spring 2014 Sources: Computer
Today s topics. MIPS operations and operands. MIPS arithmetic. CS/COE1541: Introduction to Computer Architecture. A Review of MIPS ISA.
Today s topics CS/COE1541: Introduction to Computer Architecture MIPS operations and operands MIPS registers Memory view Instruction encoding A Review of MIPS ISA Sangyeun Cho Arithmetic operations Logic
ECE232: Hardware Organization and Design. Computer Organization - Previously covered
ECE232: Hardware Organization and Design Part 6: MIPS Instructions II http://www.ecs.umass.edu/ece/ece232/ Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Computer Organization
Concocting an Instruction Set
Concocting an Instruction Set Nerd Chef at work. move flour,bowl add milk,bowl add egg,bowl move bowl,mixer rotate mixer... Read: Chapter 2.1-2.7 L03 Instruction Set 1 A General-Purpose Computer The von
ECE 2035 Programming HW/SW Systems Fall problems, 7 pages Exam Two 23 October 2013
Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate
MIPS Reference Guide
MIPS Reference Guide Free at PushingButtons.net 2 Table of Contents I. Data Registers 3 II. Instruction Register Formats 4 III. MIPS Instruction Set 5 IV. MIPS Instruction Set (Extended) 6 V. SPIM Programming
Mips Code Examples Peter Rounce
Mips Code Examples Peter Rounce P.Rounce@cs.ucl.ac.uk Some C Examples Assignment : int j = 10 ; // space must be allocated to variable j Possibility 1: j is stored in a register, i.e. register $2 then
A General-Purpose Computer The von Neumann Model. Concocting an Instruction Set. Meaning of an Instruction. Anatomy of an Instruction
page 1 Concocting an Instruction Set Nerd Chef at work. move flour,bowl add milk,bowl add egg,bowl move bowl,mixer rotate mixer... A General-Purpose Computer The von Neumann Model Many architectural approaches
SPIM Instruction Set
SPIM Instruction Set This document gives an overview of the more common instructions used in the SPIM simulator. Overview The SPIM simulator implements the full MIPS instruction set, as well as a large
Machine Language Instructions Introduction. Instructions Words of a language understood by machine. Instruction set Vocabulary of the machine
Machine Language Instructions Introduction Instructions Words of a language understood by machine Instruction set Vocabulary of the machine Current goal: to relate a high level language to instruction
Rui Wang, Assistant professor Dept. of Information and Communication Tongji University.
Instructions: ti Language of the Computer Rui Wang, Assistant professor Dept. of Information and Communication Tongji University it Email: ruiwang@tongji.edu.cn Computer Hierarchy Levels Language understood
Computer Organization MIPS Architecture. Department of Computer Science Missouri University of Science & Technology
Computer Organization MIPS Architecture Department of Computer Science Missouri University of Science & Technology hurson@mst.edu Computer Organization Note, this unit will be covered in three lectures.
Midterm. CS64 Spring Midterm Exam
Midterm LAST NAME FIRST NAME PERM Number Instructions Please turn off all pagers, cell phones and beepers. Remove all hats & headphones. Place your backpacks, laptops and jackets at the front. Sit in every
Computer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: MIPS Instruction Set Architecture
Computer Science 324 Computer Architecture Mount Holyoke College Fall 2009 Topic Notes: MIPS Instruction Set Architecture vonneumann Architecture Modern computers use the vonneumann architecture. Idea:
CS3350B Computer Architecture
CS3350B Computer Architecture Winter 2015 Lecture 4.1: MIPS ISA: Introduction Marc Moreno Maza www.csd.uwo.ca/courses/cs3350b [Adapted d from lectures on Computer Organization and Design, Patterson & Hennessy,
Chapter 2. Instruction Set Architecture (ISA)
Chapter 2 Instruction Set Architecture (ISA) MIPS arithmetic Design Principle: simplicity favors regularity. Why? Of course this complicates some things... C code: A = B + C + D; E = F - A; MIPS code:
Announcements. EE108B Lecture MIPS Assembly Language III. MIPS Machine Instruction Review: Instruction Format Summary
Announcements EE108B Lecture MIPS Assembly Language III Christos Kozyrakis Stanford University http://eeclass.stanford.edu/ee108b PA1 available, due on Thursday 2/8 Work on you own (no groups) Homework
EN164: Design of Computing Systems Lecture 11: Processor / ISA 4
EN164: Design of Computing Systems Lecture 11: Processor / ISA 4 Professor Sherief Reda http://scale.engin.brown.edu Electrical Sciences and Computer Engineering School of Engineering Brown University
Architecture I. Computer Systems Laboratory Sungkyunkwan University
MIPS Instruction ti Set Architecture I Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Architecture (1) the attributes of a system as seen by the
Concocting an Instruction Set
Concocting an Instruction Set Nerd Chef at work. move flour,bowl add milk,bowl add egg,bowl move bowl,mixer rotate mixer... Lab is posted. Do your prelab! Stay tuned for the first problem set. L04 Instruction
MIPS Instruction Reference
Page 1 of 9 MIPS Instruction Reference This is a description of the MIPS instruction set, their meanings, syntax, semantics, and bit encodings. The syntax given for each instruction refers to the assembly
MIPS ISA and MIPS Assembly. CS301 Prof. Szajda
MIPS ISA and MIPS Assembly CS301 Prof. Szajda Administrative HW #2 due Wednesday (9/11) at 5pm Lab #2 due Friday (9/13) 1:30pm Read Appendix B5, B6, B.9 and Chapter 2.5-2.9 (if you have not already done
Today s Lecture. MIPS Assembly Language. Review: What Must be Specified? Review: A Program. Review: MIPS Instruction Formats
Today s Lecture Homework #2 Midterm I Feb 22 (in class closed book) MIPS Assembly Language Computer Science 14 Lecture 6 Outline Assembly Programming Reading Chapter 2, Appendix B 2 Review: A Program Review:
CPS311 - COMPUTER ORGANIZATION. A bit of history
CPS311 - COMPUTER ORGANIZATION A Brief Introduction to the MIPS Architecture A bit of history The MIPS architecture grows out of an early 1980's research project at Stanford University. In 1984, MIPS computer
Do-While Example. In C++ In assembly language. do { z--; while (a == b); z = b; loop: addi $s2, $s2, -1 beq $s0, $s1, loop or $s2, $s1, $zero
Do-While Example In C++ do { z--; while (a == b); z = b; In assembly language loop: addi $s2, $s2, -1 beq $s0, $s1, loop or $s2, $s1, $zero 25 Comparisons Set on less than (slt) compares its source registers
Computer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: MIPS Instruction Set Architecture
Computer Science 324 Computer Architecture Mount Holyoke College Fall 2007 Topic Notes: MIPS Instruction Set Architecture vonneumann Architecture Modern computers use the vonneumann architecture. Idea:
Assembly Language Programming. CPSC 252 Computer Organization Ellen Walker, Hiram College
Assembly Language Programming CPSC 252 Computer Organization Ellen Walker, Hiram College Instruction Set Design Complex and powerful enough to enable any computation Simplicity of equipment MIPS Microprocessor
EE108B Lecture 3. MIPS Assembly Language II
EE108B Lecture 3 MIPS Assembly Language II Christos Kozyrakis Stanford University http://eeclass.stanford.edu/ee108b 1 Announcements Urgent: sign up at EEclass and say if you are taking 3 or 4 units Homework
MIPS (SPIM) Assembler Syntax
MIPS (SPIM) Assembler Syntax Comments begin with # Everything from # to the end of the line is ignored Identifiers are a sequence of alphanumeric characters, underbars (_), and dots () that do not begin
A Processor. Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University. See: P&H Chapter , 4.1-3
A Processor Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University See: P&H Chapter 2.16-20, 4.1-3 Let s build a MIPS CPU but using Harvard architecture Basic Computer System Registers ALU
All instructions have 3 operands Operand order is fixed (destination first)
Instruction Set Architecture for MIPS Processors Overview Dr. Arjan Durresi Louisiana State University Baton Rouge, LA 70803 durresi@csc.lsu.edu These slides are available at: http://www.csc.lsu.edu/~durresi/_07/
Math 230 Assembly Programming (AKA Computer Organization) Spring 2008
Math 230 Assembly Programming (AKA Computer Organization) Spring 2008 MIPS Intro II Lect 10 Feb 15, 2008 Adapted from slides developed for: Mary J. Irwin PSU CSE331 Dave Patterson s UCB CS152 M230 L10.1
ECE 2035 A Programming Hw/Sw Systems Spring problems, 8 pages Final Exam 29 April 2015
Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate
EE 109 Unit 8 MIPS Instruction Set
1 EE 109 Unit 8 MIPS Instruction Set 2 Architecting a vocabulary for the HW INSTRUCTION SET OVERVIEW 3 Instruction Set Architecture (ISA) Defines the software interface of the processor and memory system
MIPS Instruction Format
MIPS Instruction Format MIPS uses a 32-bit fixed-length instruction format. only three different instruction word formats: There are Register format Op-code Rs Rt Rd Function code 000000 sssss ttttt ddddd
CS 4200/5200 Computer Architecture I
CS 4200/5200 Computer Architecture I MIPS Instruction Set Architecture Dr. Xiaobo Zhou Department of Computer Science CS420/520 Lec3.1 UC. Colorado Springs Adapted from UCB97 & UCB03 Review: Organizational
COMP 303 Computer Architecture Lecture 3. Comp 303 Computer Architecture
COMP 303 Computer Architecture Lecture 3 Comp 303 Computer Architecture 1 Supporting procedures in computer hardware The execution of a procedure Place parameters in a place where the procedure can access
Mark Redekopp, All rights reserved. EE 352 Unit 3 MIPS ISA
EE 352 Unit 3 MIPS ISA Instruction Set Architecture (ISA) Defines the software interface of the processor and memory system Instruction set is the vocabulary the HW can understand and the SW is composed
We will study the MIPS assembly language as an exemplar of the concept.
MIPS Assembly Language 1 We will study the MIPS assembly language as an exemplar of the concept. MIPS assembly instructions each consist of a single token specifying the command to be carried out, and
Week 10: Assembly Programming
Week 10: Assembly Programming Arithmetic instructions Instruction Opcode/Function Syntax Operation add 100000 $d, $s, $t $d = $s + $t addu 100001 $d, $s, $t $d = $s + $t addi 001000 $t, $s, i $t = $s +
CPU Design for Computer Integrated Experiment
CPU Design for Computer Integrated Experiment Shan Lu, Guangyao Li, Yijianan Wang CEIE, Tongji University, Shanghai, China Abstract - Considering the necessity and difficulty of designing a CPU for students,
Grading: 3 pts each part. If answer is correct but uses more instructions, 1 pt off. Wrong answer 3pts off.
Department of Electrical and Computer Engineering University of Wisconsin Madison ECE 552 Introductions to Computer Architecture Homework #2 (Suggested Solution) 1. (10 points) MIPS and C program translations
ECE 2035 A Programming Hw/Sw Systems Fall problems, 10 pages Final Exam 14 December 2016
Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate
CS61C : Machine Structures
inst.eecs.berkeley.edu/~cs61c/su06 CS61C : Machine Structures Lecture #9: MIPS Procedures 2006-07-11 CS 61C L09 MIPS Procedures (1) Andy Carle C functions main() { int i,j,k,m;... i = mult(j,k);... m =
MIPS Hello World. MIPS Assembly 1. # PROGRAM: Hello, World! # Data declaration section. out_string:.asciiz "\nhello, World!\n"
MIPS Hello World MIPS Assembly 1 # PROGRAM: Hello, World!.data # Data declaration section out_string:.asciiz "\nhello, World!\n".text # Assembly language instructions main: # Start of code section li $v0,
Shift and Rotate Instructions
Shift and Rotate Instructions Shift and rotate instructions facilitate manipulations of data (that is, modifying part of a 32-bit data word). Such operations might include: Re-arrangement of bytes in a
CSE Lecture In Class Example Handout
CSE 30321 Lecture 07-08 In Class Example Handout Part A: J-Type Example: If you look in your book at the syntax for j (an unconditional jump instruction), you see something like: e.g. j addr would seemingly
ECE Exam I February 19 th, :00 pm 4:25pm
ECE 3056 Exam I February 19 th, 2015 3:00 pm 4:25pm 1. The exam is closed, notes, closed text, and no calculators. 2. The Georgia Tech Honor Code governs this examination. 3. There are 4 questions and
Chapter 2. Instructions: Language of the Computer
Chapter 2 Instructions: Language g of the Computer Outlines Introduction to MIPS machine Operations of the Computer HW Operands of the Computer HW Representing instructions in the Computer Logical Operations
CS3350B Computer Architecture MIPS Procedures and Compilation
CS3350B Computer Architecture MIPS Procedures and Compilation Marc Moreno Maza http://www.csd.uwo.ca/~moreno/cs3350_moreno/index.html Department of Computer Science University of Western Ontario, Canada
Architecture II. Computer Systems Laboratory Sungkyunkwan University
MIPS Instruction ti Set Architecture II Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Making Decisions (1) Conditional operations Branch to a
Outline. EEL-4713 Computer Architecture Multipliers and shifters. Deriving requirements of ALU. MIPS arithmetic instructions
Outline EEL-4713 Computer Architecture Multipliers and shifters Multiplication and shift registers Chapter 3, section 3.4 Next lecture Division, floating-point 3.5 3.6 EEL-4713 Ann Gordon-Ross.1 EEL-4713
Instruction Set Architecture of. MIPS Processor. MIPS Processor. MIPS Registers (continued) MIPS Registers
CSE 675.02: Introduction to Computer Architecture MIPS Processor Memory Instruction Set Architecture of MIPS Processor CPU Arithmetic Logic unit Registers $0 $31 Multiply divide Coprocessor 1 (FPU) Registers
Patterson PII. Solutions
Patterson-1610874 978-0-12-407726-3 PII 2 Solutions Chapter 2 Solutions S-3 2.1 addi f, h, -5 (note, no subi) add f, f, g 2.2 f = g + h + i 2.3 sub $t0, $s3, $s4 add $t0, $s6, $t0 lw $t1, 16($t0) sw $t1,
Computer Architecture. Lecture 2 : Instructions
Computer Architecture Lecture 2 : Instructions 1 Components of a Computer Hierarchical Layers of Program Code 3 Instruction Set The repertoire of instructions of a computer 2.1 Intr roduction Different
Lecture 6 Decision + Shift + I/O
Lecture 6 Decision + Shift + I/O Instructions so far MIPS C Program add, sub, addi, multi, div lw $t0,12($s0) sw $t0, 12($s0) beq $s0, $s1, L1 bne $s0, $s1, L1 j L1 (unconditional branch) slt reg1,reg2,reg3
Review (1/2) IEEE 754 Floating Point Standard: Kahan pack as much in as could get away with. CS61C - Machine Structures
Review (1/2) CS61C - Machine Structures Lecture 11 - Starting a Program October 4, 2000 David Patterson http://www-inst.eecs.berkeley.edu/~cs61c/ IEEE 754 Floating Point Standard: Kahan pack as much in
Forecast. Instructions (354 Review) Basics. Basics. Instruction set architecture (ISA) is its vocabulary. Instructions are the words of a computer
Instructions (354 Review) Forecast Instructions are the words of a computer Instruction set architecture (ISA) is its vocabulary With a few other things, this defines the interface of computers But implementations
Problem maximum score 1 35pts 2 22pts 3 23pts 4 15pts Total 95pts
University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences CS61c Summer 2001 Woojin Yu Midterm Exam This is a closed-book exam. No calculators
MIPS PROJECT INSTRUCTION SET and FORMAT
ECE 312: Semester Project MIPS PROJECT INSTRUCTION SET FORMAT This is a description of the required MIPS instruction set, their meanings, syntax, semantics, bit encodings. The syntax given for each instruction
Digital System Design II
Digital System Design II 数字系统设计 II Peng Liu ( 刘鹏 ) Dept. of Info. Sci. & Elec. Engg. Zhejiang University liupeng@zju.edu.cn Lecture 2 MIPS Instruction Set Architecture 2 Textbook reading MIPS ISA 2.1-2.4
UCB CS61C : Machine Structures
inst.eecs.berkeley.edu/~cs61c UCB CS61C : Machine Structures Lecture 10 Introduction to MIPS Procedures I Sr Lecturer SOE Dan Garcia 2014-02-14 If cars broadcast their speeds to other vehicles (and the
CS 61c: Great Ideas in Computer Architecture
Introduction to Assembly Language June 30, 2014 Review C Memory Layout Local variables disappear because the stack changes Global variables don t disappear because they are in static data Dynamic memory
Code Generation. The Main Idea of Today s Lecture. We can emit stack-machine-style code for expressions via recursion. Lecture Outline.
The Main Idea of Today s Lecture Code Generation We can emit stack-machine-style code for expressions via recursion (We will use MIPS assembly as our target language) 2 Lecture Outline What are stack machines?
Lab 4 Report. Single Cycle Design BAOTUNG C. TRAN EEL4713C
Lab 4 Report Single Cycle Design BAOTUNG C. TRAN EEL4713C Added Hardware : Andi and Ori : For this instruction, I had to add a zero extender into my design. Which therefore required me to add a mux that
Field 6-Bit Op Code rs Field rt Field 16-bit Immediate field
Introduction to MIPS Instruction Set Architecture The MIPS used by SPIM is a 32-bit reduced instruction set architecture with 32 integer and 32 floating point registers. Other characteristics are as follows:
Orange Coast College. Business Division. Computer Science Department CS 116- Computer Architecture. The Instructions
Orange Coast College Business Division Computer Science Department CS 116- Computer Architecture The Instructions 1 1 Topics: Assembly language, assemblers MIPS R2000 Assembly language Instruction set
Compiling Techniques
Lecture 10: An Introduction to MIPS assembly 18 October 2016 Table of contents 1 Overview 2 3 Assembly program template.data Data segment: constant and variable definitions go here (including statically
8*4 + 4 = 36 each int is 4 bytes
CS 61CL (Clancy) Solutions and grading standards for exam 1 Spring 2009 169 students took the exam. The average score was 43.6; the median was 46. Scores ranged from 1 to 59. There were 89 scores between
Chapter loop: lw $v1, 0($a0) addi $v0, $v0, 1 sw $v1, 0($a1) addi $a0, $a0, 1 addi $a1, $a1, 1 bne $v1, $zero, loop
Chapter 3 3.7 loop: lw $v1, 0($a0) addi $v0, $v0, 1 sw $v1, 0($a1) addi $a0, $a0, 1 addi $a1, $a1, 1 bne $v1, $zero, loop Instructions Format OP rs rt Imm lw $v1, 0($a0) I 35 4 3 0 addi $v0, $v0, 1 I 8
Lecture Topics. Branch Condition Options. Branch Conditions ECE 486/586. Computer Architecture. Lecture # 8. Instruction Set Principles.
ECE 486/586 Computer Architecture Lecture # 8 Spring 2015 Portland State University Instruction Set Principles MIPS Control flow instructions Dealing with constants IA-32 Fallacies and Pitfalls Reference:
CS61C : Machine Structures
inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures $2M 3D camera Lecture 8 MIPS Instruction Representation I Instructor: Miki Lustig 2014-09-17 August 25: The final ISA showdown: Is ARM, x86, or
Operands and Addressing Modes
Operands and Addressing Modes Where is the data? Addresses as data Names and Values Indirection L5 Addressing Modes 1 Assembly Exercise Let s write some assembly language programs Program #1: Write a function
ISA: The Hardware Software Interface
ISA: The Hardware Software Interface Instruction Set Architecture (ISA) is where software meets hardware In embedded systems, this boundary is often flexible Understanding of ISA design is therefore important
CSc 256 Final Spring 2011
CSc 256 Final Spring 2011 NAME: Problem1: Convertthedecimalfloatingpointnumber 4.3toa32 bitfloat(inbinary)inieee 754standardrepresentation.Showworkforpartialcredit.10points Hint:IEEE754formatfor32 bitfloatsconsistsofs
CS 61C: Great Ideas in Computer Architecture MIPS Instruction Formats
CS 61C: Great Ideas in Computer Architecture MIPS Instruction Formats Instructors: Vladimir Stojanovic and Nicholas Weaver http://inst.eecs.berkeley.edu/~cs61c/sp16 1 Machine Interpretation Levels of Representation/Interpretation
Design of Digital Circuits 2017 Srdjan Capkun Onur Mutlu (Guest starring: Frank K. Gürkaynak and Aanjhan Ranganathan)
Microarchitecture Design of Digital Circuits 27 Srdjan Capkun Onur Mutlu (Guest starring: Frank K. Gürkaynak and Aanjhan Ranganathan) http://www.syssec.ethz.ch/education/digitaltechnik_7 Adapted from Digital
Chapter 2. Instruction Set. RISC vs. CISC Instruction set. The University of Adelaide, School of Computer Science 18 September 2017
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface RISC-V Edition Chapter 2 Instructions: Language of the Computer These slides are based on the slides by the authors. The slides doesn t
CS61C L10 MIPS Instruction Representation II, Floating Point I (6)
CS61C L1 MIPS Instruction Representation II, Floating Point I (1) inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #1 Instruction Representation II, Floating Point I 25-1-3 There is one
CSE Lecture In Class Example Handout
CSE 30321 Lecture 07-09 In Class Example Handout Part A: A Simple, MIPS-based Procedure: Swap Procedure Example: Let s write the MIPS code for the following statement (and function call): if (A[i] > A
Numbers: positional notation. CS61C Machine Structures. Faux Midterm Review Jaein Jeong Cheng Tien Ee. www-inst.eecs.berkeley.
CS 61C Faux Midterm Review (1) CS61C Machine Structures Faux Midterm Review 2002-09-29 Jaein Jeong Cheng Tien Ee www-inst.eecs.berkeley.edu/~cs61c/ Numbers: positional notation Number Base B B symbols
MIPS Processor Overview
MIPS Processor Cptr280 Dr Curtis Nelson MIPS Processor Overview Hardware Design philosophy Architecture Software Assembly language program structure QTSpim simulator Example programs 1 MIPS Processor Power
Lecture 3: The Instruction Set Architecture (cont.)
Lecture 3: The Instruction Set Architecture (cont.) COS / ELE 375 Computer Architecture and Organization Princeton University Fall 2015 Prof. David August 1 Review: Instructions Computers process information
Lecture 6: Assembly Programs
Lecture 6: Assembly Programs Today s topics: Procedures Examples Large constants The compilation process A full example 1 Procedures Local variables, AR, $fp, $sp Scratchpad and saves/restores, $fp Arguments
CS61C : Machine Structures
inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 14 Introduction to MIPS Instruction Representation II Lecturer PSOE Dan Garcia www.cs.berkeley.edu/~ddgarcia Are you P2P sharing fans? Two
COMP 303 MIPS Processor Design Project 3: Simple Execution Loop
COMP 303 MIPS Processor Design Project 3: Simple Execution Loop Due date: November 20, 23:59 Overview: In the first three projects for COMP 303, you will design and implement a subset of the MIPS32 architecture
MIPS Assembly Programming
COMP 212 Computer Organization & Architecture COMP 212 Fall 2008 Lecture 8 Cache & Disk System Review MIPS Assembly Programming Comp 212 Computer Org & Arch 1 Z. Li, 2008 Comp 212 Computer Org & Arch 2
The MIPS Processor Datapath
The MIPS Processor Datapath Module Outline MIPS datapath implementation Register File, Instruction memory, Data memory Instruction interpretation and execution. Combinational control Assignment: Datapath
CS61C : Machine Structures
inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 13 Introduction to MIPS Instruction Representation I Lecturer PSOE Dan Garcia www.cs.berkeley.edu/~ddgarcia Anyone seen Terminator? Military
Functions and Procedures
Functions and Procedures Function or Procedure A separate piece of code Possibly separately compiled Located at some address in the memory used for code, away from main and other functions (main is itself
CS 61C: Great Ideas in Computer Architecture. Lecture 11: Datapath. Bernhard Boser & Randy Katz
CS 61C: Great Ideas in Computer Architecture Lecture 11: Datapath Bernhard Boser & Randy Katz http://inst.eecs.berkeley.edu/~cs61c Agenda MIPS Datapath add instruction register transfer level circuit timing
CS61C : Machine Structures
inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #10 Instruction Representation II, Floating Point I 2005-10-03 Lecturer PSOE, new dad Dan Garcia www.cs.berkeley.edu/~ddgarcia #9 bears
2. dead code elimination (declaration and initialization of z) 3. common subexpression elimination (temp1 = j + g + h)
Problem 1 (20 points) Compilation Perform at least five standard compiler optimizations on the following C code fragment by writing the optimized version (in C) to the right. Assume f is a pure function
CO Computer Architecture and Programming Languages CAPL. Lecture 13 & 14
CO20-320241 Computer Architecture and Programming Languages CAPL Lecture 13 & 14 Dr. Kinga Lipskoch Fall 2017 Frame Pointer (1) The stack is also used to store variables that are local to function, but
COMPUTER ORGANIZATION AND DESIGN. The Hardware/Software Interface. Chapter 4. The Processor: A Based on P&H
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface Chapter 4 The Processor: A Based on P&H Introduction We will examine two MIPS implementations A simplified version A more realistic pipelined
Lecture 7: MIPS Functions Part 2. Nested Function Calls. Lecture 7: Character and String Operations. SPIM Syscalls. Recursive Functions
Part Part Part What if we need to call a function inside of a function? Will this work? int twofun(int a, int b) { int res; res = addfun(a, b) a / ; return res; } twofun: addi $sp, $sp, -4 sw $s0, 0($sp)
Lecture 4: Review of MIPS. Instruction formats, impl. of control and datapath, pipelined impl.
Lecture 4: Review of MIPS Instruction formats, impl. of control and datapath, pipelined impl. 1 MIPS Instruction Types Data transfer: Load and store Integer arithmetic/logic Floating point arithmetic Control
Procedure Calls Main Procedure. MIPS Calling Convention. MIPS-specific info. Procedure Calls. MIPS-specific info who cares? Chapter 2.7 Appendix A.
MIPS Calling Convention Chapter 2.7 Appendix A.6 Procedure Calls Main Procedure Call Procedure Call Procedure Procedure Calls Procedure must from any call Procedure uses that main was using We need a convention
CS61C : Machine Structures
inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 14 Introduction to MIPS Instruction Representation II 2004-02-23 Lecturer PSOE Dan Garcia www.cs.berkeley.edu/~ddgarcia In the US, who is
Lecture 2: RISC V Instruction Set Architecture. Housekeeping
S 17 L2 1 18 447 Lecture 2: RISC V Instruction Set Architecture James C. Hoe Department of ECE Carnegie Mellon University Housekeeping S 17 L2 2 Your goal today get bootstrapped on RISC V RV32I to start