Chapter 2. Instruction Set Architecture (ISA)

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1 Chapter 2 Instruction Set Architecture (ISA)

2 MIPS arithmetic Design Principle: simplicity favors regularity. Why? Of course this complicates some things... C code: A = B + C + D; E = F - A; MIPS code: (s0 A, s1 B, s2 C, s3 D, s4 E, s5 F) add \$t0, \$s1, \$s2 # t0 s1 + s2 add \$s0, \$t0, \$s3 # s0 t0 + s3 sub \$s4, \$s5, \$s0 # s4 s5 s0 Operands must be registers, only 32 registers provided Design Principle: smaller is faster. Why? Spring 2008 EE 334 2

3 Memory Organization Bytes are nice, but most data items use larger "words" For MIPS, a word is 32 bits or 4 bytes bits of data 32 bits of data 32 bits of data 32 bits of data Registers hold 32 bits of data 2 32 bytes with byte addresses from 0 to words with byte addresses 0, 4, 8, Words are aligned i.e., what are the least 2 significant bits of a word address? Spring 2008 EE 334 3

4 Instructions Load and store instructions (Memory Read and Write) Example: C code: A[8] = h + A[8]; MIPS code: lw \$t0, 32(\$s3) add \$t0, \$s2, \$t0 sw \$t0, 32(\$s3) # t0 M[s3+32] # t0 s2 + t0 # M[s3+32] t0 Store word has destination last Remember arithmetic operands are registers, not memory! Spring 2008 EE 334 4

5 So far we ve learned: MIPS loading words but addressing bytes arithmetic on registers only Instruction Meaning add \$s1, \$s2, \$s3 \$s1 = \$s2 + \$s3 sub \$s1, \$s2, \$s3 \$s1 = \$s2 \$s3 lw \$s1, 100(\$s2) \$s1 = Memory[\$s2+100] sw \$s1, 100(\$s2) Memory[\$s2+100] = \$s1 Spring 2008 EE 334 5

6 Machine Language Instructions, like registers and words of data, are also 32 bits long Example: add \$t0, \$s1, \$s2 registers have numbers, \$t0=8, \$s1=17, \$s2=18 Instruction Format: Code num.bits Fields op rs rt rd shamt funct Can you guess what the field names stand for? Spring 2008 EE 334 6

7 Machine Language Consider the load-word and store-word instructions, What would the regularity principle have us do? New principle: Good design demands a compromise Introduce a new type of instruction format I-type for data transfer instructions other format was R-type for register Example: lw \$t0, 32(\$s2) op rs rt 16 bit number Where's the compromise? Spring 2008 EE 334 7

8 Control Decision making instructions alter the control flow, i.e., change the "next" instruction to be executed MIPS conditional branch instructions: bne \$t0, \$t1, Label beq \$t0, \$t1, Label Example: if (i==j) h = i + j; bne \$s0, \$s1, Label add \$s3, \$s0, \$s1 Label:... Spring 2008 EE 334 8

9 Control MIPS unconditional branch instructions: j label Example: if (i!=j) beq \$s4, \$s5, Lab1 h=i+j; add \$s3, \$s4, \$s5 else j Lab2 h=i-j; Lab1:sub \$s3, \$s4, \$s5 Lab2:... Can you build a simple for loop? Spring 2008 EE 334 9

10 So far: Instruction Meaning add \$s1,\$s2,\$s3 \$s1 = \$s2 + \$s3 sub \$s1,\$s2,\$s3 \$s1 = \$s2 \$s3 lw \$s1,100(\$s2) \$s1 = Memory[\$s2+100] sw \$s1,100(\$s2) Memory[\$s2+100] = \$s1 bne \$s4,\$s5,l Next instr. is at Label if \$s4 \$s5 beq \$s4,\$s5,l Next instr. is at Label if \$s4 = \$s5 j Label Next instr. is at Label Formats: R I J op rs rt rd shamt funct op rs rt 16 bit address op 26 bit address Spring 2008 EE

11 Control Flow We have: beq, bne, what about Branch-if-less-than? New instruction: slt \$t0, \$s1, \$s2 if \$s1 < \$s2 then \$t0 = 1 else \$t0 = 0 Can use this instruction to build "blt \$s1, \$s2, Label" can now build general control structures Note that the assembler needs a register to do this, there are policy of use conventions for registers Spring 2008 EE

12 Conventions Name Register Usage Preserved on call? \$zero 0 the constant value 0 n.a. \$v0-\$v1 2-3 values for results and expression no \$a0-\$a3 4-7 arguments yes \$t0-\$t temporaries no \$s0-\$s saved yes \$t8-\$t more temporaries no \$gp 28 global pointer yes \$sp 29 stack pointer yes \$fp 30 frame pointer yes \$ra 31 return address yes Spring 2008 EE

13 Constants Small constants are used quite frequently (50% of operands) e.g., A = A + 5; B = B + 1; C = C - 18; Solutions? Why not? put 'typical constants' in memory and load them. create hard-wired registers (like \$zero) for constants like one. MIPS Instructions: addi \$29, \$29, 4 slti \$8, \$18, 10 andi \$29, \$29, 6 ori \$29, \$29, 4 How do we make this work? Spring 2008 EE

14 How about larger constants? We'd like to be able to load a 32 bit constant into a register Must use two instructions, new "load upper immediate" instruction lui \$t0, filled with zeros Then must get the lower order bits right, i.e., ori \$t0, \$t0, ori Spring 2008 EE

15 Assembly Language vs. Machine Language Assembly provides convenient symbolic representation much easier than writing down numbers e.g., destination first Machine language is the underlying reality e.g., destination is no longer first Assembly can provide 'pseudoinstructions' e.g., move \$t0, \$t1 exists only in Assembly would be implemented using add \$t0,\$t1,\$zero When considering performance you should count real instructions Spring 2008 EE

16 Other Issues Things we are not going to cover support for procedures linkers, loaders, memory layout stacks, frames, recursion manipulating strings and pointers interrupts and exceptions system calls and conventions Some of these we'll talk about later We've focused on architectural issues basics of MIPS assembly language and machine code we ll build a processor to execute these instructions. Spring 2008 EE

17 Overview of MIPS simple instructions all 32 bits wide very structured, no unnecessary baggage only three instruction formats R I J op rs rt rd shamt funct op rs rt 16 bit address op 26 bit address rely on compiler to achieve performance what are the compiler's goals? help compiler where we can Spring 2008 EE

18 Addresses in Branches and Jumps Instructions: bne \$t4,\$t5,label Next instruction is at Label if \$t4 \$t5 beq \$t4,\$t5,label Next instruction is at Label if \$t4 = \$t5 j Label Next instruction is at Label Formats: I J op rs rt 16 bit address op 26 bit address Addresses are not 32 bits How do we handle this with load and store instructions? Spring 2008 EE

19 Addresses in Branches Instructions: bne \$t4,\$t5,label Next instruction is at Label if \$t4/=\$t5 beq \$t4,\$t5,label Next instruction is at Label if \$t4=\$t5 Formats: I op rs rt 16 bit address Could specify a register (like lw and sw) and add it to address use Instruction Address Register (PC = program counter) most branches are local (principle of locality) Jump instructions just use high order bits of PC address boundaries of 256 MB Spring 2008 EE

20 MIPS Operands MIPS operands Name Example Comments \$s0-\$s7, \$t0-\$t9, \$zero, Fast locations for data. In MIPS, data must be in registers to perform 32 \$a0-\$a3, \$v0-\$v1, \$gp, arithmetic. MIPS register \$zero always equals 0. Register \$at is registers \$fp, \$sp, \$ra, \$at reserved for the assembler to handle large constants Memory[0], Accessed only by data transfer instructions. MIPS uses byte addresses, so memory Memory[4],..., sequential words differ by 4. Memory holds data structures, such as arrays, words Memory[ ] and spilled registers, such as those saved on procedure calls. Spring 2008 EE

21 Data 1. Immediate addressing op rs rt Immediate 2. Register addressing op rs rt rd... funct Registers Register 3. Base addressing op rs rt Address Memory Register + Byte Halfword Word 4. PC-relative addressing op rs rt Address Memory PC + Word 5. Pseudodirect addressing op Address Memory PC Word Spring 2008 EE

22 Alternative Architectures Design alternative: provide more powerful operations goal is to reduce number of instructions executed danger is a slower cycle time and/or a higher CPI Sometimes referred to as RISC vs. CISC virtually all new instruction sets since 1982 have been RISC VAX: minimize code size, make assembly language easy instructions from 1 to 54 bytes long! We ll look at PowerPC and 80x86 Spring 2008 EE

23 PowerPC Indexed addressing example: lw \$t1,\$a0+\$s3 #\$t1=memory[\$a0+\$s3] What do we have to do in MIPS? Update addressing update a register as part of load (for marching through arrays) example: lwu \$t0,4(\$s3) #\$t0=memory[\$s3+4];\$s3=\$s3+4 What do we have to do in MIPS? Others: load multiple/store multiple a special counter register bc Loop decrement counter, if not 0 goto loop Spring 2008 EE

24 Summary Instruction complexity is only one variable lower instruction count vs. higher CPI / lower clock rate Design Principles: simplicity favors regularity smaller is faster good design demands compromise make the common case fast Instruction set architecture a very important abstraction indeed! Spring 2008 EE

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