Chapter 6 Basic Function Instruction

Transcription

1 Chapter 6 Basic Function Instruction T 6-2 C 6-5 SET 6-8 RST 6- : MC 6-2 : MCE 6-4 2: SKP 6-5 3: SKPE 6-7 4: DIFU 6-8 5: DIFD 6-9 6: BSHF 6-2 7: UDCTR 6-2 8: MOV : MOV/ 6-24 : TOGG 6-25 : (+) : (-) : (*) : (/) 6-3 5: (+) : (-) : CMP : AND : OR : BCD : BIN

2 T TIMER T Symbol TB: Time Base (.S,.S, S) Tn: Timer Number PV: Preset value of the timer. Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K WX WX24 WY WY24 WM WM896 WS WS984 T T255 C C255 R R384 R3839 R393 R394 R3967 R3968 R467 R5 R87 D D495 Tn PV The total number of timers is 256 (T~T255) with three different time bases,.s,.s and S.The default number and allocation of timers is shown as below (Can be adjusted according to user s actual requirements by the Configuration function): T~T49:.S timer(default as.~327.67s) T5~T99:.S timer(default as.~3276.7s) T2~T255:S timer(default as ~32767S) FBs-PLC programming tool will lookup the timer s time base automatically according to the Memory Configuration after the timer number is keyed in. Timer s time = Time base x Preset value. In the example below, the time base T =.S and the PV value =, therefore the T timer s time =.S x =.S. If PV is a register, then Timer s time = Time base x register content. Therefore, you only need to change the register content to change the timer s time. Please refer to Example 2. The maximum error of a timer is a time base plus a scan time. In order to reduce the timing error in the application, please use the timer with a smaller time base. When the time control is, the timer will start timing (the current value will accumulate from ) until Time Up (i.e. CV PV), then the Tn contact and TUP (FO) will change to. As long as the timer control input is kept as, even the CV of Tn has reached or exceeded the PV, the CV of the timer will continue accumulating (with M957 = ) until it reaches the maximum limit (32767). The Tn contact status and flag will remain as when CV PV, unless the input is. When input is, the CV of Tn will be reset to immediately and the Tn contact and Time Up flag TUP will also change to (please refer to the diagram below). If the FBS-PLC OS version is higher than V3. (inclusive), the M957 can be set to so the CV will not accumulate further after Time Up and stops at the PV value. The default value of the M957 is, therefore the status of M957 can be set before executing any timer instruction in the program to individually set the timer CV to continue accumulating or stop at the PV after Time Up (please refer to the diagram below). 6-2

3 T TIMER T Example Constant preset value Ladder diagram Key operations Mnemonic code X.S T TUP Y X T PV: X P SET M957.S T TUP FO Y SHORT SET M 957 An example of taking Time-Up signal directly from FO. X T PV: M957= (Defaulted) Y or X T (CV) T.S S M957= T (CV) T CV Time Start Time-Up Example 2 Variable PV The preset value (PV) shown in example is a constant which is equal to. This value is fixed and can not be changed once programmed. In many circumstances, the preset time of the timers needs to be varied while PLC running. In order to change the preset time of a timer, can first use a register as the PV operand (R or WX, WY...) and then the preset time can be varied by changing the register content. As shown in this example, if set R to, then T becomes a S Timer, and hence if set R to 2, then T becomes a 2S Timer. 6-3

4 T TIMER T Ladder diagram Key operations Mnemonic code X T5.S T5 R TUP Y X T 5 PV: R T 5 An example of applying the time-up status by using the T5 contact. Y X 2 T5 (current value) When R= Y.S When R=2 Y 2.S Time Start Time-Up Time-Up Remark: If the preset value of the timer is equal to, then the timer's contact status and FO (TUP) become ("" input must be at ) immediately after the PLC finishes its first scan because "Time-Up" has occurred. (TUP) stays at until "" input changes to. 6-4

5 C Symbol COUNTER (6-Bit: C~C99,32-Bit: C2~C255) Basic Function Instruction C Cn: The Counter number PV: Preset value Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K WX WX24 WY WY24 WM WM896 WS WS984 T T255 C C255 R R3839 R384 R393 R394 R3967 R3968 R467 R5 R87 D D Cn PV There are total 2 6-Bit counters (C~C99). The range of preset value is between ~ C~C39 are Retentive Counters and the CV value will be retained when the PLC turns on or RUN again after a power failure or a PLC STOP. For Non Retentive Counters, if a power failure or PLC STOP occurs, the CV value will be reset to when the PLC turns on or RUN again. There are total Bit counters (C2~C255). The range of the preset value is between ~ C2~C239 are Retentive Counters and C24~C255 are Non Retentive Counters. The default number and assignment of the counters are shown below, if necessary can use the "CONFIGURATION" function to change the settings. To insure the proper counting, the sustain time of input status of CLK should greater than scan time. The max. counting frequency with this instruction can only up to 2Hz, for higher frequency please use the high-speed soft/hardware counter. When "CLR" is at, all of the contact Cn, FO (CUP), and CV value of the counter CV are cleared to and the counter stops counting. When "CLR" is at, the counter is allowed to count up. The Counter counts up every time the clock "CK " changes from to (adds to the CV) until the cumulative current value is equal to or greater than the preset value (CV>=PV), the counter "Count-Up" and the contact status of the counter Cn and FO (CUP) changes to. If the input status of clock continues to change, even the cumulative current value is equal and greater than the preset value, the CV value will still accumulate until it reaches the up limit at or The contact Cn and FO (CUP) stay at as long as CV>=PV unless the "CLR" input is set to.(please refer the diagram below) If the FBS-PLC OS version is higher than V3. (inclusive), the M973 can set to so the CV will not accumulate further after Count Up and stops at the PV. M973 default value is, therefore the status of M973 can be set before executing any counter instruction in the program to individually set the counter CV to continue accumulating or stops at the PV after Count Up (please refer to the diagram below). 6-5

6 C COUNTER (6-Bit: C~C99, 32-bit: C2~C255) C Example 6-Bit Fixed Counter Ladder diagram Key operations Mnemonic code SHORT X X PSU CLR RST C PV : M973 5 CUP Y LD RST M 973 X LD X C PV: 5 SET M973 X X PSU CLR C 2 PV : 5 CUP FO Y SHORT SET M 973 An example of applying the Count-Up status by using FO directly. LD X LD X C 2 PV: 5 X X M973= (Defaulted) M973= C Y C2 (CV) C times times 5 Count Start Count-Up Example 2 32-Bit counter with variable preset value Like a timer, if the PV of a counter is changed to a register (such as R, D, and so on), the counter will use the register contents as the counting PV. Therefore, only need to change the register contents to change the PV of the counter while PLC is running. Below is an example of a 32-bit counter that uses the data register R as the PV (in fact it is the 32-bit PV formed by R and R). 6-6

7 C COUNTER (6-Bit: C~C99, 32-Bit: C2~C255) C Ladder diagram Key operations Mnemonic code X C2 CUP X X CLR PV : R LD LD X C2 Y C2 PV: R C 2 An example of applying the time-up status by using the C2 contact. Y X X C (R=) When R=4 Y 4 times When R=9 Y 9 times Count Start Count-Up Count-Up Remark: If the preset value of the counter is and "CLR" input also at, then the Cn contact status and FO (CUP) becomes immediately after the PLC finishes its first scan because the "Count-Up" has occurred. It will stay at regardless how the CV value varies until "CLR" input changes to. 6-7

8 SET D P Symbol SET (Set coil or all the bits of register to ) SET D P D: destination to be set (the number of a coil or a register) Range Y M SM S WY WM WS TMR CTR HR OR SR ROR DR Y Y255 M M9 M92 M2 S S999 WY WY24 WM WM896 WS WS984 T T255 C C255 R R3839 R394 R3967 R3968 R467 R5 R87 D * * * D D495 When the set control "" = or from ( P instruction ), sets the bit of a coil or all bits of a register to. Example Single Coil Set Ladder Diagram Key Operations Mnemonic Codes X X P SET Y P RST Y SET RST P P X Y X Y X SET X RST Y 6-8

9 SET D P SET (Set coil or all the bits of register to ) Basic Function Instruction SET D P Example 2 Set 6-Bit Register Ladder Diagram Key Operations Mnemonic Codes X P SET R SET P X R B5 B D R X= B5 B D R Example 3 32-Bit Register Set Ladder Diagram Key Operations Mnemonic Codes X D SET R SET D X R B3 R R B D R X= D R 6-9

10 RST D P Symbol RESET (Reset the coil or the register to ) RST D P D: Destination to be reset (the number of a coil or a register) Range Y M SM S WY WM WS TMR CTR HR OR SR ROR DR Y Y255 M M9 M92 M2 S S999 WY WY24 WM WM896 WS WS984 T T255 C C255 R R3839 R394 R3967 R3968 R467 R5 R87 D * * * D D495 When the reset control "" = or from ( P instruction ), resets the coil or register to. Example Single Coil Reset Please refer to example for the SET instruction shown in page 6-8. Example 2 6-Bit Register Reset Ladder Diagram Key Operations Mnemonic Codes X RST P R 6-

11 RST D P RESET (Reset the coil or register to ) Basic Function Instruction RST D P B5 B D R X= B5 B D R Example 3 32-Bit Register Reset Ladder Diagram Key Operations Mnemonic Codes X D RST WM368 X RST D WM368 M399 WM384 WM368 M368 D WM368 X= D WM368 6-

12 FUN MC MASTER CONTROL LOOP START FUN MC Symbol Ladder symbol. N: Master Control Loop number (N=~27) Master control MC N the number N cannot be used repeatedly. There are a total of 28 MC loops (N=~27). Every Master Control Start instruction, MC N, must correspond to a Master Control End instruction, MCE N, which has the same loop number as MC N. They must always be used in pairs and you should also make sure that the MCE N instruction is after the MC N instruction. When the Master Control input "/" is, then this MC N instruction will not be executed, as it does not exist. When the Master Control input "/" is, the master control loop is active, the area between the MC N and MCE N is called the Master Control active loop area. All the status of coils or Timers within Master Control active loop area will be cleared to. Other instructions will not be executed. Example Ladder Diagram Key Operations Mnemonic Codes X X. MC Y FUN N: X X2 S T2 X Y T2 Y X 2 T2 PV: X. MCE Y2 T 2 Y FUN N: X Y 2 6-2

13 FUN MC MASTER CONTROL LOOP START FUN MC X X X2 T2 Y Y S Y2 Remark:MC/MCE instructions can be used in nesting or interleaving as shown to the right: Remark2: When M98= and the master input changes from, and if pulse type function instructions exist in the master control loop, then these instructions will have a chance to be executed only once (when the first time the master control input changes from ). Afterwards, no matter how many times the master control input changes from, the pulse type function instructions will not be executed again. When M98= and the master control input changes from, and if pulse type function instructions exist in the master control loop, then each time the master control input changes from the pulse type function instructions in the master control loop will be executed as long as the action conditions are satisfied. When a counting instruction exists in the master control loop, set M98 to can avoid counting error. When the pulse type function instructions in the master control loop must act upon the input change by the master control, the flag M98 should be set to. X X X2 MC MC MC MC MC MC. MC. MC 2. MC 3. MC 2. MC. MC 3 6-3

14 FUN MCE MASTER CONTROL LOOP D FUN MCE Symbol Ladder symbol. MCE N N: Master Control End number (N=~27) N can not be used repeatedly. Every MCE N must correspond to a Master Control Start instruction. They must always be used as a pair and you should also make sure that the MCE N instruction is after the MC N instruction. After the MC N instruction has been executed, all output coil status and timers will be cleared to and no other instructions will be executed. The program execution will resume until a MCE instruction which has the same N number as MC N instruction appears. MCE instruction does not require an input control because the instruction itself forms a network which other instructions can not connect to it. If the MC instruction has been executed then the master control operation will be completed when the execution of the program reaches the MCE instruction. If MC N instruction has never been executed then the MCE instruction will do nothing. Please refer to the example and explanations for MC instruction. 6-4

15 FUN 2 SKP Symbol SKIP START FUN 2 SKP Ladder symbol Skip control 2. SKP N N: Skip loop number (N=~27), N can not be used repeatedly. There are total 28 SKP loops (N=~27). Every skip start instruction, SKP N, must correspond to a skip end instruction, SKPE N, which has the same loop number as SKP N. They must always be used as a pair and you should also make sure that the SKPE N instruction is after the SKP N instruction. When the skip control "" is, then the Skip Start instruction will not be executed. When the skip control "" is, the range between the SKP N and SKPE N which is so called the Skip active loop area will be skipped, that is all the instructions in this area will not be executed. Therefore the statuses of the discrete or registers in this Skip active loop area will be retained. Example Ladder Diagram Key Operations Mnemonic Codes X X 2. SKP Y FUN N: X 2 X2 T2 S T2 Y X Y X 2 3. SKPE T2 PV: X Y2 T 2 Y FUN 3 N: X Y 2 6-5

16 FUN 2 SKP SKIP START FUN 2 SKP X X X2 T2 Y Y S Y2 6-6

17 FUN 3 SKPE SKIP D FUN 3 SKPE Symbol Ladder symbol 3. SKPE N N: SKIP D Loop number (N=~27) N can not be used repeatedly. Every SKPE N must correspond to a SKP N instruction. They must always be used as a pair and you should also make sure that the SKPE N instruction is behind the SKP N instruction. SKPE instruction does not require an input control because the instruction itself forms a network which other instructions can not connect to it. If the SKP N instruction has been executed then the skip operation will be completed when the execution of the program reaches the SKPE N instruction. If SKP N instruction has never been executed then the SKPE instruction will do nothing. Example Please refer to the example and explanations for SKP N instruction. Remark : SKP/SKPE instructions can be used by nesting or interleaving. The coding rules are the same as for the MC/MCE instructions. Please refer to the section of MC/MCE instructions. 6-7

18 FUN 4 DIFU Symbol DIFFERTIAL UP FUN 4 DIFU D: a specific coil number where the result of the Differential Up operation is stored. Range Y M SM S Y Y255 M M9 M92 M2 S S999 D * The DIFU instruction is used to output the up differentiation of a node status (status input to "TGU") and the pulse signal resulting from the status change at the rising edge of the "TGU" for one scan time is stored to a coil specified by D. The functionality of this instruction can also be achieved by using a TU contact. Example The results of the following two samples are exactly the same Ladder Diagram Key Operations Mnemonic Codes Example X TGU 4P. DIFU Y FUN FUN X 4 D: Y Example 2 X Y TU X Y X t t : scan time Y 6-8

19 FUN 5 P DIFD Symbol DIFFERTIAL DOWN FUN 5 P DIFD N: a specific coil number where the result of the Differential Down operation is stored. Range Y M SM S Y Y255 M M9 M92 M2 S S999 D * The DIFD instruction is used to output the down differentiation of a node status (status input to "TGD") and the pulse signal resulting from the status change at the falling edge of the "TGD" for one scan time is stored to a coil specified by D. The functionality of this instruction can also be achieved by using a TD contact. Example The results of the following two samples are exactly the same Ladder Diagram Key Operations Mnemonic Codes Example X TGD 5P. DIFD Y FUN X FUN 5 D: Y Example 2 X Y TD X Y X t t : scan time Y 6-9

20 FUN 6 D P BSHF Symbol BIT SHIFT (Shifts the data of the 6-bit or 32-bit register to left or to right by one bit) FUN 6 D P BSHF D: The register number for shifting Range WY WM WS TMR CTR HR OR SR ROR DR WY WY24 WM WM896 WS WS984 T T255 C C255 R R3839 R394 R3967 R3968 R467 R5 R87 D D495 D * * When the status of clear control "CLR" is at, then the data of register D and FO will all be cleared to. Other input signals are all in effect. When the status of clear control is "CLR" at, then the shift operation is permissible. When the shift control "" = or from ( P instruction), the data of the register will be shifted to right (L/R=) or to left (L/R=) by one bit. The shifted-out bit (MSB when shift to left and LSB when shift to right) for both cases will be sent to FO. The vacated bit space (LSB when shift to left and MSB when shift to right) due to shift operation will be filled in by the input status of fill-in bit "INB". Example Shifts the 6-bit register data Ladder diagram Key Operations Mnemonic Codes X X X2 INB 6P.BSHF D : R 3 OTB Y LD LD LD LD X 2 LD X 3 LD X 4 X3 X4 L/R CLR FUN FUN 6P D: R 3 FO Y X3= (Left shift) X3= (Right shift) B5 B Y Shifts the 6-bit data to left by one bit X2 B5 B X2 Shifts the 6-bit data to right by one bit Y 6-2

21 FUN 7 D P UDCTR Symbol UP/DOWN COUNTER (6-bit or 32-bit up and down 2-phase Counter) Basic Function Instruction FUN 7 D P UDCTR CV: The number of the Up/Down Counter PV: Preset value of the counter or it's register number Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K WX WY WM WS T C R R384 R394 R3968 R5 D Ope- rand WX24 WY24 WM896 WS984 T255 C255 R3839 R393 R3967 R467 R87 D495 CV * * 6/32-bit +/ number PV When the clear control CLR is, the counter s CV will be reset to and the counter will not be able to count. When the clear control CLR is, counting will then be allowed. The nature of the instruction is a P instruction. Therefore, when the count-pulse PLS is from (rising edge), the CV will increased by (if U/D=) or decreased by (if U/D=). When CV=PV, FO( Count-Up) will change to. If there are more clocks input, the counter will continue counting which cause CV PV. Then, FO will immediately change to. This means the Count-Up signal will only be equal to if CV=PV, or else it will be equal to (Care should be taken to this difference from the Count-Up signal of the general counter). The upper limit of up count value is (6-bit) or (32-bit). After the upper limit is reached, if another up count clock is received, the counting value will become or (the lower limit of down count). The lower limit of down count value is (6-bit) or (32-bit). After the lower limit is reached, if another down count clock is received, the counting value will become or (the upper limit of up count). If U/D is fixed as, the instruction will become a single-phase up count counter. If U/D is fixed as, the instruction will become a single-phase down count counter. 6-2

22 FUN 7 D P UDCTR UP/DOWN COUNTER (6-bit or 32-bit up/down 2-phase Counter) FUN 7 D P UDCTR Ladder Diagram Key Operations Mnemonic Codes X8 X7 PSU U/D 7P.UDCTR CV : PV : R - 3 CUP Y LD LD X 8 LD X 7 LD X 6 FUN 7 X6 CLR CV: R PV: 3 FO Y Up(add) Down(subtract) X6 X7 X8 R Y Remark : Since the counting operation of UDCTR is implemented by software scanning, therefore if the clock speed is faster than the scan speed, lose count may then happen (generally the clock should not exceed 2Hz depending on the size of the program). Please use the software or hardware high-speed counter in the PLC. Refer to the High Speed Counter Application in the Advanced Manual. Remark 2: In order to ensure the proper counting, the sustain time of the status of clock input should greater than scan time. 6-22

23 FUN 8 D P MOV MOVE (Moves data from S to D) Basic Function Instruction FUN 8 D P MOV Move control Ladder symbol 8DP.MOV S : D : S: Source register number D: Destination register number The S, N, D may combine with V, Z, P~P9 to serve indirect addressing Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K XR WX WX24 WY WY24 WM WM896 WS WS984 T T255 C C255 R R3839 R384 R393 R394 R3967 R3968 R467 R5 R87 D D495 6/32-bit +/ number P~P9 S D * * V Z Move (write) the data of S to a specified register D when the move control input "" = or from to ( P instruction). Example Writes a constant data into a 6-bit register. Ladder Diagram Key Operations Mnemonic Codes X 8P.MOV S : D : R X FUN 8P S: D: R S K X= D R 6-23

24 FUN 9 D P MOV/ Symbol MOVE INVERSE (Inverts the data of S and moves the result to a specified device D) FUN 9 D P MOV/ Move control Ladder symbol 9DP.MOV/ S : D : S: Source register number D: Destination register number S, N, D may combine with V, Z, P~P9 to serve indirect addressing Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K XR WX WX24 WY WY24 WM WM896 WS WS984 T T255 C C255 R R3839 R384 R3847 R394 R3967 R3968 R467 R5 R87 D D495 6/32-bit +/ number P~P9 S D * * V Z Inverts the data of S (changes the status from to and from to ) and moves the results to a specified register D when the move control input "" = or from to ( P instruction). Example Moves the inverted data of a 6-bit register to another 6-bit register. Ladder Diagram Key Operations Mnemonic Codes X 9.MOV/ S : R D : WY 8 X FUN 9 S: R D: WY 8 B5 S R 5555H B Y23 X= D WY8 AAAAH Y8 6-24

25 FUN TOGG Symbol TOGGLE SWITCH (Changes the output status when the rising edge of control input occur) FUN TOGG D: the coil number of the toggle switch Range Y M SM S Y Y255 M M92 M9 M2 S S999 D * The coil D changes its status (from to and from to ) each time the input "TGU" is triggered from to (rising edge). Example Ladder Diagram Key Operations Mnemonic Codes X TGU P. TOGG Y X FUN D: Y X Y 6-25

26 FUN D P (+) Symbol ADDITION (Performs addition of the data specified at Sa and Sb and stores the result in D) FUN D P (+) Sa: Augend Sb: Addend D : Destination register to store the results of the addition Sa, Sb, D may combine with V, Z, P~P9 to serve indirect addressing Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K XR WX WX24 WY WY24 WM WM896 WS WS984 T T255 C C255 R R3839 R384 R393 R394 R3967 R3968 R467 R5 R87 D D495 6/32-bit +/ number Sa Sb D * * V Z P~P9 Performs the addition of the data specified at Sa and Sb and writes the results to a specified register D when the add control input "" = or from to ( P instruction). If the result of addition is equal to then set FO to. If carry occurs (the result exceeds or ) then set FO to. If borrow occurs (adding negative numbers resulting in a sum less than or ), then set the FO2 to. All the FO statuses are retained until this instruction is executed again and overwritten by a new result. Example 6-bit addition Ladder Diagram Key Operations Mnemonic Codes X U/S P.(+) Sa : R Sb : R D : R 2 D= CY Y X FUN P Sa: R Sb: R BR D: R 2 FO Y Sa R 2345 Sb R 2425 R+R=3277 X= D R =3277 Y= (carry represents ) 6-26

27 FUN 2 D P ( ) Symbol SUBTRACTION (Performs subtraction of the data specified at Sa and Sb and stores the result in D) FUN 2 D P ( ) Ladder symbol 2DP.(-) Sa : Subtraction control D= Unsign/Sign U/S Sb : D : CY BR Difference=(FO) Carry(FO) Borrow(FO2) Sa: Minuend Sb: Subtrahend D : Destination register to store the results of the subtraction Sa, Sb, D may combine with V, Z, P~P9 to serve indirect addressing Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K XR WX WX24 WY WY24 WM WM896 WS WS984 T T255 C C255 R R3839 R384 R393 R394 R3967 R3968 R467 R5 R87 D D495 6/32-bit +/ number Sa Sb D * * V Z P~P9 Performs the subtraction of the data specified at Sa and Sb and writes the results to a specified register D when the subtract control input "" = or from to ( P instruction). If the result of subtraction is equal to then set FO to. If carry occurs (subtracting a negative number from a positive number and the result exceeds or ), then set FO to. If borrow occurs (subtracting a positive number from a negative number and the resulted difference is less than or ), then set FO2 to. All the FO statuses are retained until this instruction is executed again and overwritten by a new result. Example 6-bit subtraction Ladder Diagram Key Operations Mnemonic Codes X X 2P.(-) U/S Sa : Sb : D : R R R 2 D= CY BR Y2 FUN 2 Sa: R Sb: R D: R 2 FO 2 Y 2 Sa R -5 Sb R R-R= X= D R = Y2=(borrow represents-32768)please refer to section

28 FUN 3 D P (*) Symbol MULTIPLICATION (Performs multiplication of the data specified at Sa and Sb and stores the result in D) FUN 3 D P (*) Ladder symbol 3DP.(*) Sa : Mutiplication control D= Unsign/Sign U/S Sb : D : Product=(FO) D< Product is negative (FO) Sa: Multiplicand Sb: Multiplier D : Destination register to store the results of the multiplication. Sa, Sb, D may combine with V, Z, P~P9 to serve indirect addressing Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K XR WX WX24 WY WY24 WM WM896 WS WS984 T T255 C C255 R R3839 R384 R393 R394 R3967 R3968 R467 R5 R87 D D495 6/32-bit +/ number Sa Sb D * * V Z P~P9 Performs the multiplication of the data specified at Sa and Sb and writes the results to a specified register D when the multiplication control input "" = or from to ( P instruction). If the product of multiplication is equal to then set FO to. If the product is a negative number, then set FO to. Example 6-bit multiplication Ladder Diagram Key Operations Mnemonic Codes X X U/S 3P.(*) Sa : R Sb : R D : R 2 D= D< FUN 3P Sa: R Sb: R D: R 2 Sa Sb R 2345 R 4567 Multiplicand Multiplier D R R2 Product 6-28

29 FUN 3 D P (*) MULTIPLICATION (Performs multiplication of the data specified at Sa and Sb and stores the result in D) FUN 3 D P (*) Example 2 32-bit multiplication Ladder Diagram Key Operations Mnemonic Codes X X U/S 3D.(*) Sa : R Sb : R D : R 2 4 D= D< FUN 3D Sa: R Sb: R 2 D: R 4 Sa R R Multiplicand Sb R3 R2 Multiplier D R7 R6 R5 R Product 6-29

30 FUN 4 D P (/) Symbol DIVISION (Performs division of the data specified at Sa and Sb and stores the result in D) FUN 4 D P (/) Ladder symbol 4DP.(/) Division control Sa : D= Sb : Unsign/Sign U/S D : ERR Quotient= (FO) Divisor is (FO) Sa: Dividend Sb: Divisor D : Destination register to store the results of the division. Sa, Sb, D may combine with V, Z, P~P9 to serve indirect addressing Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K XR WX WX24 WY WY24 WM WM896 WS WS984 T T255 C C255 R R3839 R384 R393 R394 R3967 R3968 R467 R5 R87 D D495 6/32-bit +/ number Sa Sb D * * V Z P~P9 Performs the division of the data specified at Sa and Sb and writes the quotient and remainder to registers specified by register D when the division control input "" = or from to ( P instruction). If the quotient of division is equal to then set FO to. If the divisor Sb= then set the error flag FO to without executing the instruction. Example 6-bit division Ladder Diagram Key Operations Mnemonic Codes X U/S 4P.(/) Sa: R Sb: R D : R 2 D= ERR X FUN 4 Sa: R Sb: R D: R 2 Sa Sb R 256 R 2 Dividend Divisor D R3 R2 4 2 Remainder Quotient 6-3

31 FUN 4 D P (/) DIVISION (Performs division of the data specified at Sa and Sb and stores the result in D) FUN 4 D P (/) Example 2 32-bit division Ladder Diagram Key Operations Mnemonic Codes X 4D.(/) Sa: R Sb: R 2 D= X FUN 4D Sa: R U/S D : R 4 ERR Sb: R 2 D: R 4 Sa R R Dividend Sb R R2 Divisor D R7 R6 R5 R Remainder Quotient 6-3

32 FUN 5 D P (+) INCREMT (Adds to the D value) FUN 5 D P (+) D : The register to be increased D may combine with V, Z, P~P9 to serve indirect addressing Range WY WM WS TMR CTR HR OR SR ROR DR XR WY WY24 WM WM896 WS WS984 T T255 C C255 R R3839 R394 R3967 R3968 R467 R5 R87 D D495 V Z P~P9 D * * Adds to the register D when the increment control input "" = or from to ( P instruction). If the value of D is already at the upper limit of positive number or , adding one to this value will change it to the lower limit of negative number or At the same time, the overflow flag FO (OVF) is set to. Example 6-bit increment register Ladder diagram Key operations Mnemonic code TU X X 5P. (+) R V OVF FUN 5 D : R V When V=,+= D R X= D R

33 FUN 6 D P (-) DECREMT (Subtracts from the D value) FUN 6 D P (-) Ladder symbol 6DP. Decrement control (-) D UDF Underflow(FO) D : The register to be decreased D may combine with V, Z, P~P9 to serve indirect addressing Range WY WM WS TMR CTR HR OR SR ROR DR XR WY WY24 WM WM896 WS WS984 T T255 C C255 R R3839 R394 R3967 R3968 R467 R5 R87 D D495 V Z P~P9 D * * Subtracts from the register D when the decrement control input "" = or from to ( P instruction). If the value of D is already at the lower limit of negative number or , subtracting one from this value will change it to the upper limit of positive number or At the same time, the underflow flag FO (UDF) is set to. Example 6-bit decrement register Ladder diagram Key operations Mnemonic code X X 6P. (-) R UDF FUN 6P D : R D R X= D R

34 FUN 7 D P CMP COMPARE (Compares the data of Sa and Sb and outputs the results to function Outputs) FUN 7 D P CMP Ladder symbol 7DP.CMP Compare control Sa : a = b Sa=Sb (FO) Sa: The register to be compared Unsign/Sign U/S Sb : a > b Sa>Sb (FO) Sb: The register to be compared Sa, Sb may combine with V, Z, P~P9 to serve indirect addressing a < b Sa<Sb (FO2) Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K XR WX WY WM WS T C R R384 R394 R3968 R5 D 6/32 bit V Z Ope- rand +/-number WX24 WY24 WM896 WS984 T255 C255 R3839 R393 R3967 R467 R87 D495 P~P9 Sa Sb Compares the data of Sa and Sb when the compare control input "" = or from to ( P instruction). If the data of Sa is equal to Sb, then set FO to. If the data of Sa>Sb, then set FO to. If the data of Sa<Sb, then set FO2 to. If the data of Sa < Sb, then set the FO2 to. Example Compares the data of 6-bit register Ladder diagram Key operations Mnemonic code X 7.CMP X U/S Sa : Sb : R R a=b a>b Y FUN 7 Sa : R Sb : R a<b FO 2 Y From the above example, we first assume the data of R is and R is 2, and then compare the data by executing the CMP instruction. The FO and FO are set to and FO2 (a<b) is set to since a<b. If you want to have the compound results, such as < > etc., please send = < and > results to relay first and then combine the result from the relays. M99=, when this command in not executed, FO, FO, FO2 will remain in the status at last execution. M99=, when this command in not executed, FO, FO, FO2 are all cleared to. Control M99 properly to obtain memory-holding function for functional command output. 6-34

35 FUN 8 D P AND LOGICAL AND FUN 8 D P AND Sa: The register to be ANDed Sb: The register to be ANDed D : The register to store the result of AND The Sa, Sb, D may combine with V, Z, P~P9 to serve indirect addressing application Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K XR WX WY WM WS T C R R384 R394 R3968 R5 D 6/32 bit V Z Ope- rand +/-number WX24 WY24 WM896 WS984 T255 C255 R3839 R393 R3967 R467 R87 D495 P~P9 Sa Sb D * * Performs logical AND operation for the data of Sa and Sb when the operation control input "" = or from to ( P instruction). This operation compares the corresponding bits of Sa and Sb (B~B5 or B~B3). The bit in the D is set to if both of the corresponding bits data of Sa and Sb is. The bit in the D is set to if one of the corresponding bits is. Example Operation of 6-bit logical AND Ladder diagram Key operations Mnemonic code X X 8P.AND Sa : R Sb : R D= FUN 8P Sa : R D : R 2 Sb : R D : R 2 B5 B Sa R Sb R X= B5 B D R2 6-35

36 FUN 9 D P OR LOGICAL OR FUN 9 D P OR Sa: The register to be ORed Sb: The register to be ORed D : The register to store the result of OR The Sa, Sb, D may combine with V, Z, P~P9 to serve indirect addressing Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K XR WX WY WM WS T C R R384 R394 R3968 R5 D 6/32 bit V Z Ope- rand +/-number WX24 WY24 WM896 WS984 T255 C255 R3839 R393 R3967 R467 R87 D495 P~P9 Sa Sb D * * Performs logical OR operation for the data of Sa and Sb when the operation control input "" = or from to ( P instruction). This operation compares the corresponding bits of Sa and Sb (B~B5 or B~B3). The bit in the D is set to if one of the corresponding of Sa or Sb is. The bit in the D is set to if both of the corresponding bits of Sa and Sb is. Example Operation of 6-bit logical OR Ladder diagram Key operations Mnemonic code X 9.OR Sa : Sb : R R D= X FUN 9 Sa : R D : R 2 Sb : R D : R 2 B5 B Sa R Sb R X= B5 B D R2 6-36

37 FUN 2 D P BCD BIN TO BCD CONVERSION (Converts BIN data of the device specified at S into BCD and stores the result in D) FUN 2 D P BCD S : The register to be converted D : The register to store the converted data (BCD code) The S, D may combine with V, Z, P~P9 to serve indirect addressing Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K XR WX WY WM WS T C R R384 R394 R3968 R5 D 6/32 bit V Z Ope- +/- number rand WX24 WY24 WM896 WS984 T255 C255 R3839 R393 R3967 R467 R87 D495 P~P9 S D * * FB-PLC uses binary code to store and to execute calculations. If want to send the internal PLC data to the external displays such as seven-segment displays, it is more convenient for us to read the result on screen by converting the BIN data to BCD data. For example, it is more clear for us to read the reading "2" instead of the binary code "." Converts BIN data of the device specified at S into BCD and writes the result in D when the operation control input "" = or from to ( P instruction). If the data in S is not a BCD value (~9999 or ~ ), then the error flag FO is set to and the old data of D are retained. Example 6-bit BIN to BCD conversion Ladder diagram Key operations Mnemonic code X 2. BCD S : 9999 D : R ERR X FUN 2 S : 9999 D : R B5 B S K X= B5 B D R 6-37

38 FUN 2 D P BIN BCD TO BIN CONVERSION (Converts BCD data of the device specified at S into BIN and stores the result in D) FUN 2 D P BIN S : The register to be converted D : The register to store the converted data (BIN code) The S, D may combine with V, Z, P~P9 to serve indirect addressing Range WX WY WM WS TMR CTR HR IR OR SR ROR DR XR WX WY WM WS T C R R384 R394 R3968 R5 D V Z WX24 WY24 WM896 WS984 T255 C255 R3839 R393 R3967 R467 R87 D495 P~P9 S D * * The decimal (BCD) data must be converted to binary (BIN) data first in order for PLC to accept the data which is originally in decimal unit (BCD code) inputted from external device such as digital switch because the BCD data can not be accepted by PLC for its operations. Converts BCD data of the device specified at S into BIN and writes the result in D when the operation control input "" = or from to ( P instruction). If the data in S is not in BCD, then the error flag FO is set to and the old data of D are retained. Constant is converted to BIN automatically when store in program and can not be used as a source operand of this function. Example 6-bit BCD to BIN conversion Ladder diagram Key operations Mnemonic code X 2P. BIN S : WX D : R ERR X FUN 2P S : WX D : R X5 X S WX X= B5 B D R 6-38