8-1. Fig. 8-1 ASM Chart Elements 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

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1 8-1 Name Binary code IDLE 000 Register operation or output R 0 RUN Condition (a) State box (b) Example of state box (c) Decision box IDLE R 0 From decision box START Register operation or output PC 0 (d) Conditional output box (e) Example of decision and condition output box Fig. 8-1 ASM Chart Elements

2 8-2 IDLE Entry ASM BLOCK AVAIL Exit START A 0 Q 0 Exit Exit MUL0 MUL1 Fig. 8-2 ASM Block

3 8-3 Clock cycle 1 Clock cycle 2 Clock cycle 3 Clock START Q 0 State IDLE MUL1 AVAIL A Fig. 8-3 ASM Timing Behavior

4 Multiplicand Multiplier Product Fig. 8-4 Hand Multiplication Example

5 Multiplicand Multiplier Initial partial product Add multiplicand, since multiplier bit is Partial product after add and before shift Partial product after shift Add multiplicand, since multiplier bit is Partial product after add and before shift a Partial product after shift Partial product after shift Partial product after shift Add multiplicand, since multiplier bit is Partial product after add and before shift Product after final shift a. Note that overflow temporarily occurred. Fig. 8-5 Hardware Multiplication Example

6 8-6 n 1 Counter P IN n Multiplicand Register B log 2 n n Zero detect G (Go) C out Parallel adder Control unit 4 Z Q o n Multiplier 0 C Shift register A Shift register Q n n Control signals Product OUT Fig. 8-6 Block Diagram for Binary Multiplier

7 8-7 IDLE G C 0, A 0 P n 1 MUL0 Q 0 A A + B, C C out MUL1 C 0, C A Q sr C A Q, P P 1 Z Fig. 8-7 ASM Chart for Binary Multiplier

8 8-8 TABLE 8-1 Control Signals for Binary Multiplier Block Diagram Module Microoperation Control Signal Name Control Expression Register A: A 0 A A+ B CAQ sr CAQ Initialize Load Shift_dec IDLE G MUL0 Q 0 MUL1 Register B: B IN Load_B LOADB Flip-Flop C: C 0 Clear_C IDLE G + MUL1 C Load C out Register Q: Q IN CAQ sr CAQ Load_Q Shift_dec LOADQ Counter P: P n 1 Initialize P P 1 Shift_dec Table 8-1 Control Signals for Binary Multiplier

9 8-9 IDLE 00 G MUL0 01 MUL1 10 Z Fig. 8-8 Sequencing Part of ASM Chart for the Binary Multiplier

10 8-10 TABLE 8-2 State Table for Sequence Register and Decoder Part of Multiplier Control Unit Present state Inputs Next state Decoder Outputs Name M 1 M 0 G Z M 1 M 0 IDLE MUL0 MUL1 IDLE MUL MUL Table 8-2 State Table for Sequence Register and Decoder Part of Multiplier Control Unit

11 8-11 G Z D M 0 C DECODER IDLE A0 0 MUL0 1 2 MUL1 A1 3 Initialize Clear_C Shift_dec D M 1 C Q 0 Load Clock Fig. 8-9 Control Unit for Binary Multiplier Using a Sequence Register and a Decoder

12 8-12 State Entry Entry State D C Exit Entry X (a) State box Exit X Entry Exit 0 Exit 1 (b) Decision box Exit 0 Exit 1 Entry 1 Entry 2 Entry 1 Entry 2 Exit (c) Junction Exit Entry Entry X 1 X Exit 1 Control Exit 1 (d) Conditional output box Fig Transformation Rules for Control Unit with One Flip-Flop per State

13 IDLE D 1 C G 2 4 Initialize 3 MUL0 D 1 Q 0 4 Clear _C Load C MUL1 D 1 4 Shift_dec C Clock Z 2 Fig Control Unit with One Flip-Flop per State for the Binary Multiplier

14 Binary Multiplier with n = 4: VHDL Description -- See Figures 8-6 and 8-7 for block diagram and ASM Chart library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity binary_multiplier is port(clk, RESET, G, LOADB, LOADQ: in std_logic; MULT_IN: in std_logic_vector(3 downto 0); MULT_OUT: out std_logic_vector(7 downto 0)); end binary_multiplier; architecture behavior_4 of binary_multiplier is type state_type is (IDLE, MUL0, MUL1); signal state, next_state : state_type; signal A, B, Q: std_logic_vector(3 downto 0); signal P: std_logic_vector(1 downto 0); signal C, Z: std_logic; begin Z <= P(1) NOR P(0); MULT_OUT <= A & Q; state_register: process (CLK, RESET) begin if (RESET = '1') then state <= IDLE; elsif (CLK event and CLK = '1') then state <= next_state; end if; end process; next_state_func: process (G, Z, state) begin case state is when IDLE => if G = '1' then next_state <= MUL0; else next_state <= IDLE; end if; when MUL0 => next_state <= MUL1; when MUL1 => if Z = '1' then next_state <= IDLE; else next_state <= MUL0; end if; Fig VHDL Description of a Binary Multiplier

15 8-15 end case; end process; datapath_func: process (CLK) variable CA: std_logic_vector(4 downto 0); begin if (CLK event and CLK = '1') then if LOADB = '1' then B <= MULT_IN; end if; if LOADQ = '1' then Q <= MULT_IN; end if; case state is when IDLE => if G = '1' then C <= '0'; A <= "0000"; P <= "11"; end if; when MUL0 => if Q(0) = '1' then CA := ('0' & A) + ('0' & B); else CA := C & A; end if; C <= CA(4); A <= CA(3 downto 0); when MUL1 => C <= '0'; A <= C & A(3 downto 1); Q <= A(0) & Q(3 downto 1); P <= P - "01"; end case; end if; end process; end behavior_4; Fig VHDL Description of a Binary Multiplier (Continued)

16 8-16 // Binary Multiplier with n = 4: Verilog Description // See Figures 8-6 and 8-7 for block diagram and ASM Chart module binary_multiplier_v (CLK, RESET, G, LOADB, LOADQ, MULT_IN, MULT_OUT); input CLK, RESET, G, LOADB, LOADQ; input [3:0] MULT_IN; output [7:0] MULT_OUT; reg [1:0] state, next_state, P; parameter IDLE = 2 b00, MUL0 = 2 b01, MUL1 = 2 b10; reg [3:0] A, B, Q; reg C; wire Z; assign Z = ~ P; assign MULT_OUT = {A,Q}; //state register always@(posedge CLK or posedge RESET) begin if (RESET == 1) state <= IDLE; else state <= next_state; end //next state function always@(g or Z or state) begin case (state) IDLE: if (G == 1) next_state <= MUL0; else next_state <= IDLE; MUL0: next_state <= MUL1; MUL1: if (Z == 1) next_state <= IDLE; else next_state <= MUL0; endcase end //datapath function always@(posedge CLK) Fig Verilog Description of a Binary Multiplier

17 8-17 begin if (LOADB == 1) B <= MULT_IN; if (LOADQ == 1) Q <= MULT_IN; case (state) IDLE: if (G == 1) begin C <= 0; A <= 4 b0000; P <= 2 b11; end MUL0: if (Q[0] == 1) {C, A} = A + B; MUL1: begin C <= 1 b0; A <= {C, A[3:1]}; Q <= {A[0], Q[3:1]}; P <= P - 2 b01; end endcase end endmodule Fig Verilog Description of a Binary Multiplier (Continued)

18 8-18 Control inputs Status signals from datapath Next-address generator Control address register Sequencer Control address Address Control memory (ROM) Data Next-address information Control data register (optional) Control outputs Microinstruction Control signals to datapath Fig Microprogrammed Control Unit Organization

19 8-19 IDLE 000 G INIT 001 A 0, C 0 P n 1 MUL0 010 Q 0 ADD 011 A A + B, C C out MUL1 100 C 0, C A Q sr C A Q, P P 1 Z Fig ASM Chart for Microprogrammed Binary Multiplier Control Unit

20 NXTADD1 NXTADD0 SEL DATAPATH Fig Microinstruction Control Word Format

21 8-21 TABLE 8-3 Control Signals for Microprogrammed Multiplier Control Control Signal Register Transfers States in Which Signal is Active Microinstruction Bit Position Symbolic Notation Initialize A 0, P n 1 INIT 0 IT Load A A+ B, C C out ADD 1 LD Clear_C C 0 INIT, MUL1 2 CC Shift_dec CAQ sr CAQP, P 1 MUL1 3 SD Table 8-3 Control Signals for Microprogrammed Multiplier Control

22 8-22 TABLE 8-4 SEL Field Definition for Binary Multiplier Control Sequencing SEL Symbolic notation Binary Code Sequencing Microoperations NXT 00 DG 01 DQ 10 DZ 11 CAR NXTADD0 G: CAR NXTADD0 G: CAR NXTADD1 Q 0 : CAR NXTADD0 Q 0 : CAR NXTADD1 Z: CAR NXTADD0 Z: CAR NXTADD1 Table 8-4 SEL Field Definition for Binary Multiplier Control Sequencing

23 8-23 IN n 2 Datapath 4 n OUT MUX1 2 to 1 MUX DATAPATH 0 G Z Q 0 MUX2 4 to 1 MUX S 3 CAR x 12 Control Memory (ROM) SEL NXTADD0 NXTADD1 S 1 S 0 2 Fig Microprogrammed Control Unit for Multiplier

24 8-24 TABLE 8-5 Register Transfer Description of Binary Multiplier Microprogram Address IDLE INIT MUL0 ADD MUL1 Symbolic transfer statement G: CAR INIT, G: CAR IDLE C 0, A 0, P n 1, CAR MUL0 Q 0 : CAR ADD, Q 0 : CAR MUL1 A A+ B, C C out, CAR MUL1 C 0, CAQ sr CAQ, Z: CAR IDLE, Z: CAR MUL0, P P 1 Table 8-5 Register Transfer Description of Binary Multiplier Microprogram

25 8-25 TABLE 8-6 Symbolic Microprogram and Binary Microprogram for Multiplier Address NXTADD1 NXTADD0 SEL DATAPATH Address NXTADD1 NXTADD0 SEL DATAPATH IDLE INIT IDLE DG None INIT MUL0 NXT IT, CC MUL0 ADD MUL1 DQ None ADD MUL1 NXT LD MUL1 IDLE MUL0 DZ CC, SD Table 8-6 Symbolic Microprogram and Binary Microprogram for Multiplier

26 Opcode Destination register (DR) Source register A (SA) Source register B (SB) (a) Register Opcode Destination register (DR) Source register A (SA) Operand (OP) (b) Immediate Opcode Address (AD) (Left) Source register A (SA) Address (AD) (Right) (c) Jump and Branch Fig Three Instruction Formats

27 8-27 Decimal address Memory contents Decimal opcode Other specified fields Operation (Subtract) DR:1, SA:2 SB:3 R1 R2 R (Store) SA:4 SB:5 M [R4] R (Add Immediate) DR:2 SA:7 OP:3 R2 R (Branch on zero) AD: 44 SA:6 If R6 = 0, PC PC Data = 192. After execution of instruction in 35, Data = 80. Fig Memory Representation of Instructions and Data

28 8-28 Instruction memory 2 15 x 16 Program counter (PC) Register file 8 x 16 Data memory 2 15 x 16 Fig Storage Resource Diagram for a Simple Computer

29 8-29 V C N Z Branch Control PC Extend IR(8:6) IR(2:0) L P J B B C Address Instruction memory Instruction RW DA AA D Register file A B BA Instruction decoder IR(2:0) Zero fill Constant in 1 0 MUX B MB D A B A A A M B F S M D R W M W P L J B B C CONTROL FS V C N Z Bus A A Bus B Function unit F B Address out Data out Data in MW Data memory Data out Address Data in Bus D MD MUX D DATAPATH Fig Block Diagram for a Single-Cycle Computer

30 8-30 Instruction Opcode DR SA SB DA AA BA MB FS MD RW MW PL JB BC Control word Fig Diagram of Instruction Decoder

31 8-31 TABLE 8-7 Truth Table for Instruction Decoder Logic Instruction Bits Control Word Bits Instruction Function Type Bit 15 Bit 14 Bit 13 MB MD RW MW PL JB ALU function using registers X Shifter function using registers X Memory write using register data 0 0 X 0 X Memory read using register data X ALU operation using a constant X Shifter function using a constant X Conditional Branch X X 0 0 Unconditional Jump X X 0 1 Table 8-7 Truth Table for Instruction Decoder Logic

32 8-32 TABLE 8-8 Six Instructions for the Single-Cycle Computer Operation code Symbolic name Format Description Function MB MD RW MW PL JB ADI Immediate Add immediate R[ DR] R[ SA] + zf I(2:0) operand LD Register Load memory content into register R[ DR] MRSA [ [ ]] ST Register Store register MRSA [ [ ]] R[ SB] 0 0 content in memory SL Register Shift left R[ DR] slr[ SB] NOT Register Complement register BRZ Jump/Branch If R[SA] = 0, branch to PC + se AD R[ DR] R[ SA] If R[SA] = 0, PC PC + sead, If R[SA] 0, PC PC Table 8-8 Six Instructions for the Single-Cycle Computer

33 8-33 PC 1 ns Instruction memory 4 ns Register file (Read) 3 ns MUX B 1 ns Function unit or Data memory 4 ns MUX D 1 ns Register file (Write) 3 ns Fig Worst Case Delay Path in Single-Cycle Computer

34 8-34 Extend PL PI PC ZCNZVC MUX S 3 MS 16 TD DR RW 4 DA D 9 x 16 Register file 8 IL Opcode IR DR SA SB TD SA 4 Zero fill AA A B BA 4 TB SB MC MUX C 1 0 MUX B MB CAR 8 Bus A Bus B MM MUX M Control memory 256 x 28 FS V C N A Function unit B Data MW Address out out Data in Address Memory M N A M S M C I L P I Sequence control P L T D T A T B M B F S M D R W M M M W 4 Datapath control Z MD Bus D F MUX D Data in Data out MICROPROGRAMMED CONTROL DATAPATH Fig Multiple-Cycle Microprogrammed Computer

35 NA MS M C I L P I P L T D T A T B M B FS M D R W M M M W Fig Format for Microinstruction

36 8-36 TABLE 8-9 Control Word Information for Datapath TD TA TB MB FS MD RW MM MW Select Select Select Select Code Function Code Select Function Select Function Code R[DR] R[SA] R[SB] Register 0 F = A FnUt No write (NW) Address No write (NW) 0 R8 R8 R8 Constant 1 F = A Data In Write (WR) PC Write (WR) 1 F = A + B F = A + B+ 1 F = A + B F = A + B+ 1 F = A 1 F = A F = A B F = A B F = A B F = A F = B F = sr B F = sl B Table 8-9 Control Word Information for Datapath

37 8-37 TABLE 8-10 Control Information for Sequence Control Fields MS MC IL PI PL Action Symbolic Notation Code Select Symbolic Notation Action Symbolic Notation Action Symbolic Notation Action Symbolic Notation Code Increment CAR CNT 000 NA NXA No load NLI No load NLP No load NLP 0 Load CAR NXT 001 Opcode OPC Load instr. LDI Increment PC INP Load PC LDP 1 If C 1, load CAR; BC 010 else increment CAR If V 1, load CAR; BV 011 else increment CAR If Z 1, load CAR; BZ 100 else increment CAR If N 1, load CAR; BN 101 else increment CAR If C 0, load CAR; BNC 110 else increment CAR If Z 0, load CAR, else increment CAR BNZ 111 Table 8-10 Control Information for Sequence Control Fields

38 8-38 EX IF IR M [PC] PC PC + 1 IR = ? ADl R [DR] R [SA] + zf IR [2:0] IR = ? LD R [DR] M [R [SA] ] IR = ? ST M [R [SA] ] R [SB] IR = ? INC R [DR] R [SA] + 1 IR = ? NOT R [DR] R [SA] IR = ? ADD R [DR] R [SA] + R [SB] IR = ? IR = ? Fig ASM Chart for Multiple-Cycle Microprogrammed Computer

39 8-39 TABLE 8-11 Symbolic Microprogram for Fetch and Execution of Six Instructions Address NXT ADD MS MC IL PI PL TD TA TB MB FS MD RW MM MW IF EX0 CNT LDI INP NLP NW PC NW EXO NXT OPC NLI NLP NLP NW NW ADI IF NXT NXA NLI NLP NLP DR SA Constant F = A + B FnUt WR NW LD IF NXT NXA NLI NLP NLP DR SA Data WR MA NW ST IF NXT NXA NLI NLP NLP SA SB Register NW MA WR INC IF NXT NXA NLI NLP NLP DR SA F = A + 1 FnUt WR NW NOT IF NXT NXA NLI NLP NLP DR SA F = A FnUt WR NW ADD IF NXT NXA NLI NLP NLP DR SA SB Register F = A + B FnUt WR NW Table 8-11 Symbolic Microprogram for Fetch and Execution of Six Instructions

40 8-40 TABLE 8-12 Binary Microprogram for Fetch and Execution of Six Instructions Address NXT ADD MS MC IL PI PL TD TA TB MB FS MD RW MM MW Table 8-12 Binary Microprogram for Fetch and Execution of Six Instructions

41 8-41 IR = ? LRI0 R8 M [R [ SA] ] LRI R [DR] M [R8] Fig ASM Chart for Register Indirect Instruction To IF

42 8-42 IR = ? SRM R8 zf IR [2:0] zf IR [2:0] = 0? 1 T0 IF 0 SRM R [DR] sr R [SA], NOTE: SA = DR SRM R8 R8 1 R8 = 0? 1 T0 IF 0 Fig ASM Chart for Right-Shift Multiple Instruction

43 8-43 EX0 01 IF 00 IR M [PC], PC PC + 1 IR = ? (ADl) R [DR] R [SA] + zf IR [2:0] IR = ? (LD) R [DR] M [R [SA] ] IR = ? (ST) M [R [SA] ] R [SB] IR = ? (INC) R [DR] R [SA] + 1 IR = ? (NOT) R [DR] R [SA] IR = ? (ADD) R [DR] R [SA] + R [SB] IR = ? (LRI) R8 M [R [SA] ] EX1 10 R [DR] M [R8] Fig ASM Chart for Multiple-Cycle, Decoder-Based Computer

44 8-44 CR Syn. reset Counter IL Decoder I R Decoder ADI LD ST INC NOT ADD LRI 2 I F E X E X Control logic C R I L P I T D T A T B M B F S M D R M W M M W Fig Block Diagram of Hardwired Counter and Decoder-Based, Multiple-Cycle Control Unit

45 8-45 WAREHOUSE Fig Assembly Line Analogy to Computer Pipeline

46 8-46 IF PC Stage 1 Address Instruction memory Instruction IF DOF IR AA Register file A data B data BA Stage 2 Instruction decoder Zero fill MUX B MB DOF AA BA MB Data A Data B EX FS MW Address out Stage 3 FS C V N 5 A B Function unit Data memory Address Z F Data in Data out EX WB Data F Data I Data out Data in MW Address Stage 4 WB DA MD RW CONTROL RW D DATAPATH MD MUX D D data register file (same as above) Data memory (same as above) Fig Block Diagram of Pipelined Computer

47 Clock cycle IF DOF EX WB 2 IF DOF EX WB 3 IF DOF EX WB 4 IF DOF EX WB 5 IF DOF EX WB 6 IF DOF EX WB 7 IF DOF EX WB Instruction Fig Pipeline Execution Pattern of Register Number Program

48 , 01 S , 11 01, S , 10, 11 S , 10 Fig State Diagram for Problem 8-1

8-1. Fig. 8-1 ASM Chart Elements 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

8-1. Fig. 8-1 ASM Chart Elements 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated. 8-1 Name Binary code IDLE 000 Register operation or output R 0 RUN 0 1 Condition (a) State box (b) Example of state box (c) Decision box IDLE R 0 From decision box 0 1 START Register operation or output