EE 209 in Context. Spiral 0 Review of EE 109L. Digital System Spectrum. Where Does Digital Design Fit In

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1 . EE 9 in Context. EE 9L Hardware / Software Systems (ssembly Language Programming) Spiral Review of EE 9L Class Overview nalog to Digital Conversion inary Representation MIPS ssembly and CPU Organization EE 47 Computer rchitecture Caching, multicore, and other techniques to improve processor performance EE 4 Parallel & Distributed Computing Programming paradigms & other considerations to leverage parallel systems EE 9 EE 34L Introduction to Digital System Design EE 44L System On Chip (SoC) Design uilding chips with embedded processors and custom processing hardware More Digital System Design EE 477L VLSI Physically building and fabricating chips that implement the more abstract logic designs Mark Redekopp EE 49L Capstone Project Course.3.4 Where Does Digital Design Fit In Digital System Spectrum Electrical, biomedical, or computer scientists/engineers develop algorithms for Wireless and communication systems Media and imaging systems iomedical devices Digital design engineers take these general algorithms and architect/design a HW/SW system to implement them dealing with constraints of size, speed, weight, power, etc. Other electrical engineers may help with the final fabrication of the chip Key idea: ny algorithm can be implemented in HW or SW or some mixture of both digital systems can be located anywhere in a spectrum of: LL HW: (a.k.a. pplication Specific IC s) LL SW: n embedded computer system dvantages of application specific HW Faster, less power dvantages of an embedded computer system (i.e. general purpose HW for executing SW) Reprogrammable (i.e. make a mistake, fix it) Less expensive than a dedicated hardware system (single computer system can be used for multiple designs) Phone: System on Chip (SoC) approach Some dedicated HW for intensive camera/radio/etc. decoding operations Programmable processor for UI & other simple tasks Computing System Spectrum pplication Specific Hardware (no software) Flexibility, Design Time General Purpose HW w/ Software Performance, Low Power Cost

2 Processing Logic pproaches Custom Logic Logic that directly implements a specific task Example above may use separate adders and a multiplier unit General Purpose Processor Logic designed to execute SW instructions Provides basic processing resources that are reused by each instruction Design Decision: HW only or HW/SW HW only = faster HW/SW = much more flexible X Y Instruc. Store DD X,Y DD, MUL X, * Custom Logic Circuit Implementation storage * GPP Implementation of (XY)*() Out. HW/SW Design Example Suppose you need to design a JPEG encoder (converts raw pixels to JPG format consisting of a preprocessing stage encoding stage) for the camera on your mobile phone Your design considerations requirements second max. latency (time) mw max power Energy (Power * Time) as low as possible Consider time to market (design time) and cost Options. Software only running on microcontroller/processor. Hardware preprocessor Software encoder 3. Hardware preprocessor Fixed point software encoder 4. Hardware preprocessor encoder Option Option Option 3 Option 4 Performance (sec.) > 9... Power (milliwatt) < Size (gates) N/ 98, 9, 8, Energy (Joules=sec*watt).3..4 Time to Market 3 months 6 months 8 months months.6 Taken from "Embedded System Design" by Vahid and Givargis, Wiley and Sons Publishing..7.8 Integrated Solutions: Systems On Chip Mobile Phone lock Diagram Chips now combine general purpose processing, hardware accelerated engines for things like comm., video, security, etc., and integrated I/O peripherals Some contain customizable hardware resources (FPGs) for custom hardware processing engines Qualcomm Snapdragon TM nalog Inputs (Radio, WiFi, sensors) Digital Inputs (US, uttons) Sensors nalog to Digital Conversion (DC) Interconnect Clock Reset Digital Processing Microprocessors (Software for User Interface Control) Custom Logic (JPEG Encoding) Interconnect Outputs Digital to nalog Conversion (DC) Speaker, LCD Display, ntenna US Xilinx Zynq MPSoC

3 Digital System bstraction Levels Software Code Chips (Processors) Functional Units Logic Transistors if (x > ) x = x y - z; a = b*x; x y z - - Controlling - Input (Gate ) ND gate S F Output (Drain ) Source CMPR X, JLE SKIP DD X,X,Y SU X,X,Z SKIP MUL,,X HW SW C / C / Java ssembly / Machine Code Logic Gates Transistors pplications OS Processor / Memory / I/O Voltage / Currents.9 Libraries Functional Units (Registers, dders, Muxes) Our Focus in EE 9 How are we going to go about this class LERNING. Reflecting on Learning Spiral Model (Interleaving) We need to be a team? I need you You need me What do you want to learn? I will be your guide and try to build experiences. SoC / MPSoC Standard Cell Layout SIC Custom or Semi Custom Layout dders VLSI CMOS Multiplexers oolean lgebra Combinational Logic (Gates) Process / Technology MOSFET State Machines Programmable Logic (FPG) Target Implementation Technology Constructs Sequential Logic Concept Map Registers & Counters Structural (Gate) Level ehavioral vs. Cycle ccurate Digital HW Design RTL Code Synthesis Design Entry ED (CD) Tools High Level Synthesis Hardware Description Languages SystemC Simulation Physical Design (Layout & Routing) Verilog / System Verilog Schematic Entry VHDL HW / SW Co Simulation Power / Timing nalysis.

4 Spiral Content Mapping.3.4 Spiral Theory Combinational Design Sequential Design System Level Design Implementation and Tools Project Performance metrics (latency vs. throughput) oolean lgebra Canonical Representations Shannon's Theorem Decoders and muxes Synthesis with min/maxterms Synthesis with Karnaugh Maps Synthesis with muxes & memory dder and comparator design Edge triggered flip flops Registers (with enables) istables, latches, and Flipflops Counters Memories Encoded State machine design One hot state machine design Control and datapath decomposition 3 HW/SW partitioning us interfacing Single cycle CPU Structural Verilog HDL CMOS gate implementation Fabrication process MOS Theory Capacitance, delay and sizing Memory constructs Power and other logic families ED design process REVIEW..6 nalog to Digital Conversion DC Conversion nalog signal can be converted to a set of digital signals ( s and s) 3 Step Process Sample Quantize (Measure) Digitize Sampling converts continuous time scale to a discrete (finite) set of voltage samples Quantization converts continuous voltage scale to a discrete (finite) set of numbers Each number is then output as bits volts nalog to Digital Converter 77= nalog time Digital time t Sampled Signal Each sample is quantized

5 .7.8 Interpreting inary Strings Given a string of s and s, you need to know the representation system being used, before you can understand the value of those s and s. Information (value) = its Context (System) Unsigned and Signed Variables Unsigned variables use unsigned binary (normal power of place values) to represent numbers = 47 Unsigned inary system =? SCII system Signed variables use the s complement system (Neg. MS weight) to represent numbers 6 SCII Signed System = s Complement System MS has negative weight MS determines sign of the number = negative = positive Positive numbers retain same representation as unsigned = 6 in unsigned and in 's complement To take the negative of a number requires taking the complement and Sign Extension Extension is the process of increasing the number of bits used to represent a number without changing its value Unsigned = Extension (lways add leading s): = Increase a 6-bit number to 8-bit number by zero extending s complement = Sign Extension (Replicate sign bit): x = 7 x = -7 pos. = Sign bit is just repeated as many times as necessary it flip ( s comp.) dd -x = -(7) = -7 it flip ( s comp.) dd -x = -(-7) = 7 neg. =

6 .. and Sign Truncation Representation Range Truncation is the process of decreasing the number of bits used to represent a number without changing its value Unsigned = Truncation (Remove leading s): = s complement = Sign Truncation (Remove copies of sign bit): pos. neg. = = Decrease an 8-bit number to 6-bit number by truncating s. Can t remove a because value is changed ny copies of the MS can be removed without changing the numbers value. e careful not to change the sign by cutting off LL the sign bits. Given an n bit system we can represent n unique numbers In unsigned systems we use all combinations to represent positive numbers [ to n ] In s complement we use half for positive and half for negative [ n to n ] n n Hexadecimal Representation Since values in modern computers are many bits, we use hexadecimal as a shorthand notation (4 bits = hex digit) = D hex = 76C hex REVIEW OF MIPS SSEMLY

7 ..6 MIPS Instruction Set MIPS Sizes 3 bit data and address Memory supports yte, Halfword ( bytes), and Word (4 bytes) access 3 General Purpose Registers ($ $3) $ = Constant value of Fixed Size Instructions of 3 bits (4 bytes) Three formats (ways to partition and interpret those 3 bits) R Type (Register Type) [ex. DD $, $, $] I Type (Immediate Type) [ex. LW $, x3($6)] J Type (Jump Type) [ex. J ] Integer 3 Sizes Defined yte () 8 bits Halfword (H) 6 bits = bytes Word (W) 3 bits = 4 bytes Floating Point 3 Sizes Defined Single (S) 3 bits = 4 bytes Double (D) 64 bits = 8 bytes (For a 3 bit data bus, a double would be accessed from memory in reads).7.8 MIPS GPR s MIPS Programmer Visible Registers ssembler Name Reg. Number Description $zero $ Constant value $at $ ssembler temporary $v $v $ $3 Procedure return values or expression evaluation $a $a3 $4 $7 rguments/parameters $t $t7 $8 $ Temporaries $s $s7 $6 $3 Saved Temporaries $t8 $t9 $4 $ Temporaries $k $k $6 $7 Reserved for OS kernel $gp $8 Global Pointer (Global and static variables/data) $sp $9 Stack Pointer $fp $3 Frame Pointer $ra $3 Return address for current procedure General Purpose Registers (GPR s) Hold data operands or addresses (pointers) to data stored in memory Special Purpose Registers : Program Counter (3 bits) Holds the address of the next instruction to be fetched from memory & executed HI: Hi Half Reg. (3 bits) For MUL, holds 3 MS s of result. For DIV, holds 3 bit remainder LO: Lo Half Reg. (3 bits) For MUL, holds 3 LS s of result. For DIV, holds 3 bit quotient Memory Stores instructions and data GPR s $ - $3 3-bits DD SU LW MIPS Core : HI: LO: a 3fc 3fc Memory 4 Special Purpose Registers x4 x44 x48 x

8 Instruction Format.9 R Type Instructions.3 3 bit Fixed Size Instructions R Type 3 register operands I Type register 6 bit const. J Type 6 bit jump address R-Type I-Type J-Type -bits -bits -bits rs (src) rt (src) rd (dest) -bits -bits rs (src) rt (src/dst) Jump address -bits shamt immediate function add $,$7,$8 lw $8, -4($3) j x48 Format -bits rs (src) rs, rt, rd are bit fields for register numbers shamt = shift amount and is used for shift instructions indicating # of places to shift bits and func identify actual operation Example: DD $, $4, $7 rs -bits rt (src) rt -bits rd (dest) rd -bits shamt shamt function func rith. Inst. $4 $7 $ unused DD R Type rithmetic/logic Instructions C operator ssembly Notes DD Rd, Rs, Rt - SU Rd, Rs, Rt Order: R[s] R[t]. SUU for unsigned * MULT Rs, Rt MULTU Rs, Rt Result in HI/LO. Use mfhi and mflo instruction to move results * MUL Rd, Rs, Rt If multiply won t overflow 3-bit result / DIV Rs, Rt DIVU Rs, Rt & ND Rd, Rs, Rt OR Rd, Rs, Rt ^ XOR Rd, Rs, Rt R[s] / R[t]. Remainder in HI, quotient in LO ~( ) NOR Rd, Rs, Rt Can be used for bitwise-not (~) << SLL Rd, Rs, shamt SLLV Rd, Rs, Rt >> (signed) SR Rd, Rs, shamt SRV Rd, Rs, Rt >> (unsigned) SRL Rd, Rs, shamt SRLV Rd, Rs, Rt <, >, <=, >= SLT Rd, Rs, Rt SLTU Rd, Rs, Rt Shifts R[s] left by shamt (shift amount) or R[t] bits Shifts R[s] right by shamt or R[t] bits replicating sign bit to maintain sign Shifts R[s] left by shamt or R[t] bits shifting in s Order: R[s] R[t]. Sets R[d]= if R[s] < R[t], otherwise.3 Format I Type Instructions -bits -bits rs (src) rt (src/dst) immediate rs, rt are bit fields for register numbers immediate is a 6 bit constant identifies actual operation Example: rs rt DDI $, $4, DDI $4 $ LW $, 8($3) LW $3 $ immediate -8.3

9 Load Format (LW) Store Format (SW) LW Rt, offset(rs) Rt = Destination register offset(rs) = ddress of desired data Shorthand: R[t] = M[ offset R[s] ] offset limited to 6 bit signed number Examples LW $, x4($3) // R[] = xf8e97cd LW $, xfffc($4) // R[] = xc7 SW Rt, offset(rs) Rt = Source register offset(rs) = ddress to store data Shorthand: M[ offset R[s] ] = R[t] offset limited to 6 bit signed number Examples SW $, x4($3) SW $, xfff8($4) R[] R[3] old val. x4 x44 F8E97CD 3498FE R[] R[3] 3489 x4 x R[4] 4C x48 C7 R[4] 4C x Loading an Immediate ranch Instructions If immediate (constant) 6 bits or less Use ORI or DDI instruction with $ register Examples DDI $, $, // R[] = = ORI $, $, xf // R[] = xf = xf If immediate more than 6 bits Immediates limited to 6 bits so we must load constant with a instruction sequence using the special LUI (Load Upper Immediate) instruction To load $ with x34678 LUI ORI $,x34 $,$,x678 R[] R[] 34 OR LUI ORI dd a displacement to the ( = disp.) Conditional ranches ranches only if a particular condition is true Fundamental Instrucs.: EQ (if equal), NE (not equal) Syntax: NE/EQ Rs, Rt, label Compares Rs, Rt and if EQ/NE, branch to label, else continue Unconditional ranches lways branches to a new location in the code Instruction: EQ $,$,label EQ $,$3,x8 -bits rs (src) rt (src/dst) ----!= beq $,$3,label label: ---- = -bits immediate label: b label ----

10 Two Operand Compare & ranches Jump Instructions Two operand comparison is accomplished using the SLT/SLTI instruction Syntax: SLT Rd,Rs,Rt or SLT Rd,Rs,imm If Rs < Rt then Rd =, else Rd = Use appropriate NE/EQ instruction to infer relationship ranch if SLT NE/EQ $ < $3 SLT $,$,$3 NE $,$,label $ $3 SLT $,$3,$ EQ $,$,label $ > $3 SLT $,$3,$ NE $,$,label $ $3 SLT $,$,$3 EQ $,$,label Jumps provide method of branching beyond range of 6 bit displacement Syntax: J label/address Operation: = address ddress is appended with two s just like branch displacement yielding a 8 bit address with upper 4 bits of unaffected New instruction format: J Type Old [3:8] Jump address Sample Jump instruction Old before execution of Jump 4-bits -bits Jump address New after execution of Jump.39.4 Jump Register jr instruction can be used if a full 3 bit jump is needed or variable jump address is needed Syntax: JR rs Operation: = R[s] R Type machine code format Usage: Can load rs with an immediate address Can calculate rs for a variable jump (class member functions, switch statements, etc.) Instruction Ordering Identify which components each instruction type would use and in what order: LU Type, LW, SW, EQ LU-Type (DD $,$6,$7) I-Cache / I-MEM LW (LW $,4($7) ) General Purpose Registers SW (SW $,4($7) ) D-Cache / D-MEM EQ (EQ $,$3,disp) LU

11 .4.4 Single Cycle CPU path Multiplexers Each instruction will execute in one LONG clock cycle To understand the whole datapath we ll walk through it in five phases (Fetch, Decode, Execute, Memory, back) Your first HW building block Traffic cop Selects data input and passes it to the output Fetch Decode Exec. Mem W 4 Instruc. I-Cache Reg. # Reg. # Reg. # data data Register File Sign 6 Extend 3 Sh. Left LU D-Cache Thus, input = [3:] is selected and passed to the output [3:] [3:] -to- Mux i y i s Select bits = =. [3:] CLK DD $,$3,$4 LW $9,x4($6) 4 of DD Instruc. I-Cache 4 $3 $4 $ Reg. # Reg. # Reg. # data data Register File Sign 6 Extend 3 $3 value $4 value Sh. Left LU sum sum D-Cache sum 4 of LW Instruc. I-Cache 4 x4 6 9 Reg. # Reg. # Reg. # data data Register File $6 value Sign x4 6 Extend 3 Sh. Left x4 LU $6 x4 D-Cache Fetch DD Decode instruction and fetch operands dd $3 $4 Just pass sum through sum to $t4 Fetch LW Decode instruction and fetch operands dd offset x4 to $6 word from memory word to $9

12 .4.46 SW $9,x4($6) EQ $4,$,disp. 4 of LW Instruc. I-Cache 4 x4 6 9 Reg. # Reg. # Reg. # data data Register File $6 value Sign x4 6 Extend 3 Sh. Left x4 LU $9 value $6 x4 D-Cache 4 Instruc. I-Cache displacement $4 $ Reg. # Reg. # Reg. # data data Register File Sign 6 Extend 3 4 displacement Sh. Left $4 value $ value LU 4disp. (ranch ) D-Cache Fetch LW Decode instruction and fetch operands dd offset x4 to $6 word to memory Fetch EQ, increment, pass on 4 Decode instruction and fetch operands, pass on 4 Do $4-$ and check if result = Calculate branch target address Update Do Nothing.47 ND, OR, NOT Gates.48 X Z X Y Z X Y Z NOT (Inverter) ND OR Z X ' or X or ~X Z X Y Z X Y SMPLE PROLEMS (IF TIME LLOWS) X Z X Y Z ND = LL (true when LL inputs are true) X Y Z OR = NY (true when NY input is true)

13 .49. Staircase Light Switch Logic Water Tank Problem Light S uild a control system for a pump to keep the tank from going empty Pump Pump S Sensor High Sensor Low Sensor. Instruction Ordering Solutions Identify which components each instruction type would use and in what order: LU Type, LW, SW, EQ General Purpose Registers LU I-Cache / I-MEM D-Cache / D-MEM LU-Type (DD $,$6,$7).. I-Memory 3. Registers 4. LU. W to Reg. LW (LW $,4($7)).. I-Memory 3. ase. Reg. 4. LU. Mem. 6. W to Reg. SW (SW $,4($7)).. I-Memory 3. ase. Reg. 4. LU. Mem. EQ (EQ $,$3,disp).. I-Memory 3. Register ccess 4. Compare. If, Update =d