Computer and Information Sciences College / Computer Science Department The Processor: Datapath and Control

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1 Computer and Information Sciences College / Computer Science Department The Processor: Datapath and Control Chapter 5 The Processor: Datapath and Control

2 Big Picture: Where are We Now? Performance of a machine is determined by: ISA CLK time CPI Processor design (Datapath and control) will determine: CLK time CPI Single Cycle Processor Advantage: one CLK per instruction Disadvantage: Long cycle time Arithmetic- Logic nit (AL) Processor (CP) Control ( brain ) Datapath ( brawn ) Ex: What are the single cycle processor advantage and disadvantage?

3 REGISTER TRANSFER LANGAGE ICROOPERATION The operations on the data in registers are called microoperations. The functions built into registers are examples of microoperations Shift Load Clear Increment REGISTER TRANSFER LANGAGE For any function of the computer, the register transfer language can be used to describe the (sequence of) microoperations A symbolic language for describing the internal organization of digital computers RTL: An elementary operation performed (during one clock pulse), on the information stored in one or more registers R f(r, R) Registers (R) f: shift, load, clear, increment, add, subtract, complement, and, or, xor, clock cycle Ex: Define the microoperation? Define the RTL? AL (f)

4 Implementing IPS We're ready to look at an implementation of the IPS instruction set Simplified to contain only arithmetic-logic instructions: add, sub, and, or, slt memory-reference instructions: lw, sw control-flow instructions: beq, j 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits op rs rt rd shamt funct R-Format 6 bits 5 bits 5 bits 6 bits op rs rt offset 6 bits 26 bits op address I-Format J-Format Ex: What are the main IPS instruction sets and its format types?

5 Register Transfer Language RTL The Fetch/Execute Cycle High-level abstract view of fetch/execute implementation use the program counter (PC) to read instruction address fetch the instruction from memory and increment PC use fields of the instruction to select registers to read execute depending on the instruction repeat First step is to fetch the instruction from memory IR E[PC] Ex: Write the RTL for fetch and execute for each instruction?

6 Overview: Processor Implementation Styles Single Cycle perform each instruction in clock cycle clock cycle must be long enough for slowest instruction; therefore, disadvantage: only as fast as slowest instruction ulti-cycle break fetch/execute cycle into multiple steps perform step in each clock cycle advantage: each instruction uses only as many cycles as it needs Pipelined execute each instruction in multiple steps perform step / instruction in each clock cycle process multiple instructions in parallel assembly line Ex: What are the Processor Implementation Styles?

7 Clock cycle Functional Elements Two types of functional elements in the hardware: ) elements that operate on data (called combinational elements) 2) elements that contain data (called state or sequential elements) Combinational Elements and Sequential Elements Works as an input output function, e.g., AL Combinational logic reads input data from one register and writes output data to another, or same, register read/write happens in a single cycle combinational element cannot store data from one cycle to a future one Flipflops and latches are -bit state elements, equivalently, they are -bit memories The output(s) of a flipflop or latch always depends on the bit value stored, i.e., its state, and can be called / or high/low or true/false The input to a flipflop or latch can change its state depending on whether it is clocked or not State element Combinational logic State element 2 Combinational logic hardware units State element Combinational logic

8 Building a Datapath Datapath: Elements that process data and addresses in the CP (Registers, ALs, mux s, memories.) Build a IPS datapath: Fetch s operands and execute instructions. Datapath address PC Add Sum 4 A d d memory P C R e a d a d d r e s s a. memory b. Program counter c. Adder Three elements used to store and fetch instructions and increment the PC I n s t r u c t i o n m e m o r y I n s t r u c t i o n Ex: Draw the datapath for fetch instruction process?

9 Ex: Write the RTL, draw the datapath and draw with color pen the dataflow for instruction fetch process? Datapath for Fetch ADD We don t know if instruction is a Branch/Jump or one of the other instructions until we have fetched and interpreted the instruction from memory 4 <- E[PC] PC <- PC + 4 PC ADDR emory RD

10 Datapath: R-Type R[rd] R[rs] op R[rt] ; op : add; sub; or; slt Register numbers Data register data 5 register 2 Registers Write register Write data data 2 Data AL AL control AL result Two elements used to implement R-type instructions a. Registers b. AL register register 2 Registers Write register Write data data data 2 3 AL operation AL AL result Datapath Ex: Write the RTL, draw the datapath for R-type instruction execution process?

11 Ex: Write the RTL, draw the datapath and color with pen the data flow for R-type instruction execution process? Datapath for R-Type op rs rt rd shamt funct add rd, rs, rt R[rd] <- R[rs] + R[rt]; RN RN2 WN RD Register File Operation 3 AL RD2

12 Datapath: Load/Store s ) register operands 2) Calculate address using 6-bit offset 3) se AL, and sign extend offset Load: memory and update register R[rt] <- E[R[rs] + s_extend(offset)]; Two additional elements used To implement load/stores Address Write data emwrite Data memory data 6 Sign 32 extend Store: write register value to memory E[R[rs] + sign_extend(offset)] <- R[rt] register register 2 Registers Write register Write data data data 2 6 Sign 32 extend 3 AL AL operation AL result em a. Data memory unit Address Write data Datapath b. Sign-extension unit emwrite Data memory data em

13 Ex: Write the RTL, draw the datapath and color with pen the data flow for load instruction execution process? Datapath for Load s lw rt, offset(rs) R[rt] <- E[R[rs] + s_extend(offset)];

14 Ex: Write the RTL, draw the datapath and color with pen the data flow for store instruction execution process? Datapath for Store s sw rt, offset(rs) E[R[rs] + sign_extend(offset)] <- R[rt]

15 Datapath: Branch ) register operands 2) Compare operands (use AL, subtract and check zero flag) 3) Calculate target address ) Sign extended displacement 2) Shift left 2 places 3) PC PC+4 No shift hardware required: simply connect wires from input to output, each shifted left 2 bits PC + 4 from instruction datapath Shift left 2 Add Sum Branch target register register 2 Registers Write register Write data data data 2 6 Sign 32 extend 3 AL AL operation Datapath To branch control logic Ex: Draw the datapath for branch instruction execution process?

16 Datapath for Branch op rs rt offset/immediate 6 PC +4 from instruction datapath ADD 5 5 RN RN2 WN Register File RD Operation AL <<2 RD2 beq rs, rt, offset E T N D 6 32 if (R[rs] == R[rt]) then PC <- PC+4 + s_extend(offset<<2) Ex: Write the RTL, draw the datapath and color with pen the data flow for branch instruction execution process?

17 IPS Datapath I: Single-Cycle Input is either register (R-type) or sign-extended lower half of instruction (load/store) Data is either from AL (R-type) or memory (load) Combining the datapaths for R-type instructions and load/stores using two multiplexors Chapter 5 The Processor: Datapath and Control

18 Ex: Write the RTL, draw the datapath and color with pen the data flow for R-type instruction execution process? Datapath for R-type add rd,rs,rt RN RN2 WN RD Register File 5 Operation 3 AL RD2 E 6 32 T N D ALSrc emwrite ADDR Data emory em RD emtoreg

19 Ex: Write the RTL, draw the datapath and color with pen the data flow for Load instruction execution process? Datapath for Load lw rt,offset(rs) RN RN2 WN RD Register File 5 Operation 3 AL RD2 E 6 32 T N D ALSrc emwrite ADDR Data emory em RD emtoreg

20 Ex: Write the RTL, draw the datapath and color with pen the data flow for Store instruction execution process? Datapath for Store sw rt,offset(rs) RN RN2 WN RD Register File 5 Operation 3 AL RD2 E 6 32 T N D ALSrc emwrite ADDR Data emory em RD emtoreg

21 IPS Datapath II: Single-Cycle Add Separate adder as AL operations and PC increment occur in the same clock cycle 4 PC address memory register register 2 Write register Write data Registers data data 2 ALSrc u x 3 AL operation AL AL result Address Write data emwrite data Data memory emtoreg u x 6 Sign 32 extend em Separate instruction memory as instruction and data read occur in the same clock cycle Adding instruction fetch Chapter 5 The Processor: Datapath and Control

22 IPS Datapath III: Single-Cycle PCSrc New multiplexor PC 4 address Add memory address is either PC+4 or branch target address register register 2 Write register Write data Registers data data 2 6 Sign 32 extend Shift left 2 ALSrc u x Add AL result 3 AL operation AL AL result u x Extra adder needed as both adders operate in each cycle Address Write data em emwrite data Data memory emtoreg u x Adding branch capability and another multiplexor Important note: in a single-cycle implementation data cannot be stored during an instruction it only moves through combinational logic Question: is the em signal really needed?! Think of! Ex: Draw the complete datapath for fetch and execute IPS instruction in single cycle processor?

23 Ex: Draw the complete datapath for fetch and execute R-type IPS instruction in single cycle processor and color the data flow? Datapath Executing add ADD 4 ADD PC ADDR emory RD RN RN2 WN RD Register File 5 <<2 Operation 3 AL PCSrc add rd, rs, rt RD2 E 6 32 T N D ALSrc emwrite ADDR Data emory em RD emtoreg

24 Datapath Executing lw ADD 4 ADD PC ADDR emory RD RN RN2 WN RD Register File 5 <<2 Operation 3 AL PCSrc lw rt,offset(rs) RD2 E 6 32 T N D ALSrc emwrite ADDR Data emory em RD emtoreg Ex: Draw the complete datapath for fetch and execute Load IPS instruction in single cycle processor and color the data flow?

25 Ex: Draw the complete datapath for fetch and execute store IPS instruction in single cycle processor and color the data flow? Datapath Executing sw ADD 4 ADD PC ADDR emory RD RN RN2 WN RD Register File 5 <<2 Operation 3 AL PCSrc sw rt,offset(rs) RD2 E 6 32 T N D ALSrc emwrite ADDR Data emory em RD emtoreg

26 Ex: Draw the complete datapath for fetch and execute branch IPS instruction in single cycle processor and color the data flow? Datapath Executing beq ADD 4 ADD PC ADDR emory RD RN RN2 WN RD Register File 5 <<2 Operation 3 AL PCSrc beq r,r2,offset RD2 E 6 32 T N D ALSrc emwrite ADDR Data emory em RD emtoreg

27 Processor = Datapath + Control CP = Datapath+ Control Control unit takes input from the instruction code Control unit tasks Selecting the operations to perform (AL control input) write enable (possibly, read enable also) signals for each storage element Controlling the flow of data for each multiplexor op rs rt rd shamt funct 6 6 Control Logic R-format instruction To datapath Ex: What are the control unit tasks?

28 Defining Control Note that funct field only present in R-format instruction - funct controls AL only To simplify control, define ain, AL control separately using multiple levels will also increase speed important optimization technique ALop inputs will be defined op funct Control Logic op ain Control ALop AL control ALcon funct Ex: What are the main control and AL control units inputs and outputs?

29 Defining AL Control ALcon AL function (s) supported ALcon AND R-format (and) OR R-format (or) add R-format (add), lw, sw subtract R-format (sub), beq set on less than R-format (slt) NOR R-format (nor) A B A L Result Desired opcode AL Action ALOp funct ALcon lw add xxxxxx sw add xxxxxx beq subtract xxxxxx R-type add (add) R-type subtract (sub) R-type logical AND (and) R-type logical OR (or) R-type set on less (slt) Chapter 5 The Processor: Datapath and Control

30 Design AL Control A L O p A L O p A L O p funct F 3 F 2 F F O p e r a t i o n 2 O p e r a t i o n O p e r a t i o n ALcon 4th bit= Operation2 (msb) = ALOp OR (ALOp AND F) Operation = ALOp NOR F2 Operation (lsb) = ALOp AND (F3 OR F) ALOp Funct Field a a f5 f4 f3 f2 f f ALcon x x x x x x x x x x x x x x x x x x x x x x x x x x x x

31 Design the ain Control derived from the instruction code ain Control RegDst Branch em emtoreg ALop emwrite ALSrc op 2 Ex: What are the main control inputs and outputs?

32 Ex: What are the control signals for each instruction type? Design the ain Control R-Type emory Access s Branch on Equal beq lw sw RegDst = = ALSrc = Branch = emtoreg = em = emwrite = ALOp = RegDst = = ALSrc = Branch = emtoreg = em = emwrite = ALOp = RegDst = = ALSrc = Branch = emtoreg = em = emwrite = ALOp = RegDst = = ALSrc = Branch = emtoreg = em = emwrite = ALOp =

33 Outputs Inputs Design the ain Control Truth table for main control signals Signal R- lw sw beq name format Inputs Op5 * Op5 Op4 Op4 Op3 Op3 Op2 Op2 Op Op Op Op RegDst x x Outputs R-format Iw sw beq ALSrc RegDst emtoreg x x ALSrc em em emwrite emwrite Branch Branch ALOp ALOp ALOpO ALOP2 RegDst ALSrc emto- Reg Reg Write em em Write Branch ALOp ALp R-format lw sw beq emtoreg

34 Ex: Draw the complete datapath for fetch, execute with control signals for IPS instruction in single cycle processor? Datapath with Control II 4 Add [3 26] Control RegDst Branch em emtoreg ALOp emwrite ALSrc Shift left 2 Add result AL u x PCSrc PC address memory [3 ] [25 2] [2 6] [5 ] u x register Write data data register 2 Registers Write data 2 register u x AL AL result Address Write data Data memory data u x [5 ] 6 Sign 32 extend AL control [5 ] IPS datapath with the control unit: input to control is the 6-bit instruction opcode field, output is seven -bit signals and the 2-bit ALOp signal

35 Control Signals: R-Type PC 4 ADDR ADD emory RD immediate/ offset I[5:] Control signals shown in blue I 32 6 rs I[25:2] rt I[2:6] 5 5 RN RN2 WN RD Register File rd I[5:] 5 5 RD2 E 6 32 T N D RegDst ALSrc <<2??? Operation 3 AL ADD Value depends on funct PCSrc emwrite ADDR Data emory em RD emtoreg Ex: Draw with color pen the data flow and determine the control signals for R-type instruction type?

36 Control Signals:lw PC 4 ADDR ADD emory RD immediate/ offset I[5:] Control signals shown in blue I 32 6 rs I[25:2] rt I[2:6] 5 5 RN RN2 WN RD Register File rd I[5:] 5 5 RD2 E 6 32 T N D RegDst ALSrc <<2 Operation 3 AL ADD PCSrc emwrite ADDR Data emory em RD emtoreg Ex: Draw with color pen the data flow and determine the control signals for Load instruction?

37 Control Signals:sw PC 4 ADDR ADD emory RD immediate/ offset I[5:] Control signals shown in blue I 32 6 rs I[25:2] rt I[2:6] 5 5 RN RN2 WN RD Register File rd I[5:] 5 5 RD2 E 6 32 T N D RegDst ALSrc <<2 Operation 3 AL ADD PCSrc emwrite ADDR Data emory em RD emtoreg Ex: Draw with color pen the data flow and determine the control signals for store instruction?

38 Control Signals: beq PC 4 ADDR ADD emory RD immediate/ offset I[5:] Control signals shown in blue I 32 6 rs I[25:2] rt I[2:6] 5 5 RN RN2 WN RD Register File rd I[5:] 5 5 RD2 E 6 32 T N D RegDst ALSrc <<2 Operation 3 AL ADD PCSrc if = emwrite ADDR Data emory em RD emtoreg Ex: Draw with color pen the data flow and determine the control signals for branch instruction?

39 Single-Cycle Design Problems Performance Issues o Longest delay determines clock period Critical path: load instruction memory register file AL data memory register file o o o o Not feasible to vary period for different instructions Violates design principle aking the common case fast We will improve performance by pipelining Ex: What is the longest instruction path in single cycle processor

40 Summary 5 steps to design a processor. Analyze instruction set => datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer 5. Assemble the control logic IPS makes it easier s same size Source registers always in same place Immediate same size, location Operations always on registers/ immediates Single cycle datapath => CPI=, Clock Cycle Time =>Long The IPS architecture was designed to be pipelined Ex: Write the five steps to design a processor? Why IPS is easier to implement Pipeline processor?