CMSC Computer Architecture Lecture 4: Single-Cycle uarch and Pipelining. Prof. Yanjing Li University of Chicago

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1 CMSC Computer Architecture Lecture 4: Single-Cycle uarch and Pipelining Prof. Yanjing Li University of Chicago

2 Administrative Stuff! Lab1 due at 11:59pm today! Lab2 out " Pipeline ARM simulator " Build on top of lab1 " Start early!! Stick with the same partner as Lab1! Unless you have approval from me to change partner 2

3 Lecture Outline! Single-cycle uarch " Implementation " Evaluation! Pipelining basics 3

4 Recap: Single-Cycle uarch, What Is To Come **Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.] 4

5 Single-Cycle Datapath for Arithmetic and Logical Instructions 5

6 R-Type ALU Instructions opcode Rm shamt Rn Rd 11 bits 5 bits 6 bits 5 bits 5 bits! Example: Assembly ADD Rd reg, Rn reg, Rm reg! Semantics if MEM[PC] == ADD Rd, Rn, Rm GPR[Rd] GPR[Rn] + GPR[Rm] PC PC + 4 6

7 ADD Datapath ADD 9:5 20:16 4:0 1 if MEM[PC] == ADD Rd, Rn, Rm GPR[Rd] GPR[Rn] + GPR[Rm] **Based on original figure PC from [P&H PC CO&D, COPYRIGHT Elsevier. ALL RIGHTS RESERVED.] **Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.] 7

8 Single-Cycle Datapath for Data Movement Instructions 8

9 Load Instruction opcode Offset op2 Rn Rt 11 bits 9 bits 2 bits 5 bits 5 bits D-type! Assembly LDUR Rt reg, [Rn reg, offset]! Semantics if MEM[PC]==LDUR Rt, [Rn, offset] EA = sign-extend(offset) + GPR[Rn] GPR[Rt] MEM[EA] PC PC + 4 9

10 LDUR Datapath ADD 0 9:5 4:0 20: if MEM[PC]==LDUR Rt, [Rn reg, offset] EA = sign-extend(offset) + GPR[Rn] GPR[Rt] MEM[EA] PC PC + 4

11 Store Instruction opcode addoffset op2 Rn Rt 11 bits 9 bits 2 bits 5 bits 5 bits D-type! Assembly STUR Rt reg, [Rn reg, offset]! Semantics if MEM[PC]==STUR Rt, [Rn, offset] EA = sign-extend(offset) + GPR[Rn] MEM[EA] GPR[Rt] PC PC

12 STUR Datapath add 1 9:5 4:0 20: if MEM[PC]==STUR Rt, [Rn, offset] EA = sign-extend(offset) + GPR[Rn] MEM[EA] GPR[Rt] PC PC + 4

13 LDUR and STUR Datapath add isstore 9:5 4:0 4:0!isStore 20: isload **Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]

14 Datapath for R-Type and Load/Store Insts ALUop isstore 20:16 9:5 4:0 RFSrc2!isStore isstore 20: ALUSrc isload isstore isload MemtoReg isload **Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]

15 Single-Cycle Datapath for Control Flow Instructions 15

16 Unconditional Branch Instruction! Assembly B immediate 26! Machine encoding opcode BR_address B-type! Semantics if MEM[PC]==B immediate 26 target = { 36{immediate 26 [25]}, immediate 26, 2 b00 } PC PC+target 6 bits 26 bits 16

17 Unconditional Branch Datapath isb PCSrc 25:0 Sign extend and concat ALUop isstore 20:16 9:5 4:0 RFSrc2!isStore &!isb isstore 20: ALUSrc isload isstore isload if MEM[PC]==B immediate 26 target = {36{immediate 26 [25]}, immediate 26, 2 b00} PC PC+target MemtoReg isload **Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]

18 Other Instructions! What about BR, BL?! What about conditional branch instructions?! I type? WI type?

19 Your Scratchpad

20 Single-Cycle Control Logic 20

21 What Is To Come **Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.] 21

22 What is in That Control Box?! Combinational Logic: a function of Inst=MEM[PC]! Consider " R-type ALU instructions " LDUR and STUR " B 22

23 Review: Single-Cycle Datapath isb PCSrc 25:0 Sign extend and concat ALUop isstore 20:16 9:5 4:0 RFSrc2 isstore 20:12!isStore &!isb 9 64 ALUSrc isload isstore isload MemtoReg isload **Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]

24 Single-Bit Control Signals When De-asserted (0) When asserted (1) Equa`on RFsrc2 GPR reads register from inst[20:16] GPR reads register from inst[4:0] RFsrc2 = (opcode==stur) ALUSrc 2 nd ALU input from 2 nd GPR read port 2 nd ALU input from signextended 9-bit immediate ALUSrc = (opcode == LDUR) (opcode ==STUR) MemtoReg RegWrite Steer ALU result to GPR write port steer memory load to GPR wr. port MemtoReg= (opcode==ldur) GPR write disabled GPR write enabled RegWrite = (opcode!=stur) & (opcode!=b) 24

25 Single-Bit Control Signals When De-asserted (0) When asserted (1) Equa`on MemRead Memory read disabled Memory read port return load value MemRead = (opcode==ldur) MemWrite Memory write disabled Memory write enabled MemWrite = (opcode==stur) PCSrc next PC = PC + 4 next PC is PC+ branch target PCSrc = (opcode==b) 25

26 ALU Control! case opcode ALU selection operation according to opcode //ADD, SUB, AND, OR, XOR, NOR, etc. LDUR add STUR add CBZ cmp //compare register value to 0 don t care 26

27 Putting It All Together **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 27

28 Putting It All Together: R-Type ALU 1 0 ALUop 0 **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 28

29 Putting It All Together: LDUR 1 0 ADD 1 **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 29

30 Putting It All Together: STUR 0 1 ADD 0 **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 30

31 Putting It All Together: B 0 0 X 0 **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 31

32 Putting It All Together: CBZ (Taken) control signals dependent on data 0 0 cmp 0 **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 32

33 Putting It All Together: CBZ (Not Taken) control signals dependent on data 0 0 cmp 0 **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 33

34 Evaluating the Single-Cycle Machine 34

35 A Single-Cycle Microarchitecture! Is this a good idea/design? 35

36 Single-Cycle uarch Performance! Every instruction takes 1 cycle to execute! How long each instruction takes is determined by how long the slowest instruction takes to execute " Even if many other instructions do not need that long to execute! Clock cycle time of the microarchitecture is determined by how long it takes to complete the slowest instruction " Critical path of the design is determined by the processing time of the slowest instruction 36

37 What is the Slowest Instruction to Process?! All 5 steps take a single machine clock cycle to complete 1. Instruction fetch (IF) 2. Instruction decode and register operand fetch (ID/RF) 3. Execute/Evaluate memory address (EX/AG) 4. Memory operand fetch (MEM) 5. Store/writeback result (WB)! Do each of the above steps take the same time (latency) for all instructions? 37

38 Datapath Performance Analysis! Assume " memory units (read or write): 200 ps " ALU and adders: 100 ps " register file (read or write): 50 ps " other combinational logic: 0 ps steps IF ID EX MEM WB resources mem RF ALU / branch addr mem RF Delay R-type LDUR STUR B CBZ

39 R-Type ALU Datapath Delay 100ps 100ps 200ps 250ps 350ps 400ps **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 39

40 LDUR Datapath Delay 100ps 100ps 200ps 250ps 350ps 550ps 600ps **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 40

41 STUR Datapath Delay 100ps 100ps 200ps 250ps 550ps 350ps **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 41

42 CBZ (Taken) Datapath Delay 200ps 300ps 300ps 200ps **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 42

43 What About Control Logic?! How does that affect the critical path? 43

44 CBZ (Taken) Datapath and Control Delay 300ps 200ps 300ps 350ps 200ps 200ps 250ps 350ps **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 44

45 Assumption Revisited! Memory is not magic! What if memory sometimes takes 100ms to access?! Does it make sense to have a simple register to register add or branch to take {100ms+all else to do a memory operation}? 45

46 A Single-Cycle Microarchitecture! Is this a good idea/design? 46

47 Single Cycle uarch: Summary! Inefficient " All instructions run as slow as the slowest instruction! Not necessarily the simplest way to implement an ISA " Single-cycle implementation of REP MOVS (x86)?! Not easy to optimize/improve performance " Optimizing the common case (e.g. common instructions) does not work " Need to optimize the worst case all the time! All resources are not fully utilized " e.g., data memory access can t overlap with ALU operation! How to do better? 47

48 The Multi Cycle Approach! Break the execution of each instruction into multiple stages " E.g., IF, ID/RF, EX/AG, MEM, WB " Instead of 1 cycle to process all 5 stages " Take 5 cycles to process 5 stages, 1 cycle each! What determines the cycle time? " The slowest stage 48

49 Single-Cycle vs. Multi-Cycle! Single-cycle: 1 cycle per instruction " Cycle time is long F D E M W F D E M W Time! Multi-cycle: 5 cycles per instruction " Cycle time is short F D E M W F D E M W F D E M W Time 49

50 Can We Do Better?! What limitations do you see with the multi-cycle design?! Limited concurrency " Some hardware resources are idle during certain instruction processing stages " Fetch logic is idle when an instruction is being decoded or executed " Most of the datapath is idle when a memory access is happening 50

51 Can We Use the Idle Hardware to Improve Concurrency?! Goal: More concurrency # Higher instruction throughput (i.e., more work completed in one cycle)! Idea: When an instruction is using some resources in its processing phase, process other instructions on idle resources not needed by that instruction " E.g., when an instruction is being decoded, fetch the next instruction " E.g., when an instruction is being executed, decode another instruction " E.g., when an instruction is accessing data memory (ld/st), execute the next instruction " E.g., when an instruction is writing its result into the register file, access data memory for the next instruction 51

52 The Laundry Analogy! place one dirty load of clothes in the washer! when the washer is finished, place the wet load in the dryer! when the dryer is finished, take out the dry load and fold! when folding is finished, ask your roommate (??) to put the clothes away Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.] 52

53 Pipelining Multiple Loads of Laundry - 4 loads of laundry in parallel - no additional resources - throughput increased by 4 - latency per load is the same Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.] 53

54 Instruction Pipelining: Basic Idea! Pipeline the execution of multiple instructions! Idea: " Divide the instruction processing cycle into distinct stages of processing " Ensure there are enough hardware resources to process one instruction in each stage " Process a different instruction in each stage! Instructions consecutive in program order are processed in consecutive stages! Benefit: Increases instruction processing throughput! Downside: Start thinking about this 54

55 Multi-Cycle vs. Pipeline Illustration! Multi-cycle: 5 cycles per instruction F D E M W F D E M W F D E M W Time! Pipelined: 5 cycles per 5 instructions (steady state) F D E M W F D E M W F D E M W F D E M W F D E M W Time 55

56 Pipelining Instruction Processing 56

57 Remember: Instruction Processing Steps 1. Instruction fetch (IF) 2. Instruction decode and register operand fetch (ID/RF) 3. Execute/Evaluate memory address (EX/AG) 4. Memory operand fetch (MEM) 5. Store/writeback result (WB) 57

58 Remember the Single-Cycle Uarch Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 58

59 Review: LEGv8 Single-Cycle Datapath **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 59

60 Adding Pipeline Registers! Registers between stages to hold information produced in previous cycle Imm E B M Aout W B E IR D PC D +4 A E PC E +4 Aout M npc M MDR W Is this a good partitioning? Why not 4 or 6 stages? Why not different boundaries? **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 60

61 Pipeline Operation Examples! We ll look at load & store " Show pipeline usage in a single cycle " Highlight resources used 61

62 IF for Load, Store, **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 62

63 ID for Load, Store, **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 63

64 EX for Load **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 64

65 MEM for Load **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 65

66 WB for Load Wrong register number **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 66

67 Corrected Datapath for Load **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 67

68 EX for Store **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 68

69 MEM for Store **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 69

70 WB for Store **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 70

71 Pipeline Operation Examples! Consider the following instruction sequences " LDUR X10, [X1, 40] " SUB X11, X2, X3 " ADD X12, X3, X4 " LDUR X13, [X1, 48] " ADD X14, X5, X6 71

72 Single-Cycle Pipeline Diagram! State of pipeline at the 5th cycles **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 72

73 Multi-Cycle Pipeline Diagram **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 73

74 Illustrating Pipeline Operation: Operation View t 0 t 1 t 2 t 3 t 4 t 5 Inst 0 Inst 1 Inst 2 Inst 3 Inst 4 IF ID IF EX ID IF MEM EX ID IF WB MEM EX ID IF steady state (full pipeline) WB MEM EX ID IF WB MEM EX ID IF WB MEM EX ID IF 74

75 Illustrating Pipeline Operation: Resource View t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 IF I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 I 8 I 9 I 10 ID I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 I 8 I 9 EX I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 I 8 MEM I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 WB I 0 I 1 I 2 I 3 I 4 I 5 I 6 75

76 Pipelined Control Identical set of control points as the single-cycle uarch!! **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 76

77 Pipelined Control! Control signals derived from instruction " Decode once as in single-cycle implementation " Buffer signals until consumed What other options are there to derive pipeline control signals? **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 77

78 Pipelined Control **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 78

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