CMSC Computer Architecture Lecture 4: Single-Cycle uarch and Pipelining. Prof. Yanjing Li University of Chicago
|
|
- Roderick Burke
- 6 years ago
- Views:
Transcription
1 CMSC Computer Architecture Lecture 4: Single-Cycle uarch and Pipelining Prof. Yanjing Li University of Chicago
2 Administrative Stuff! Lab1 due at 11:59pm today! Lab2 out " Pipeline ARM simulator " Build on top of lab1 " Start early!! Stick with the same partner as Lab1! Unless you have approval from me to change partner 2
3 Lecture Outline! Single-cycle uarch " Implementation " Evaluation! Pipelining basics 3
4 Recap: Single-Cycle uarch, What Is To Come **Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.] 4
5 Single-Cycle Datapath for Arithmetic and Logical Instructions 5
6 R-Type ALU Instructions opcode Rm shamt Rn Rd 11 bits 5 bits 6 bits 5 bits 5 bits! Example: Assembly ADD Rd reg, Rn reg, Rm reg! Semantics if MEM[PC] == ADD Rd, Rn, Rm GPR[Rd] GPR[Rn] + GPR[Rm] PC PC + 4 6
7 ADD Datapath ADD 9:5 20:16 4:0 1 if MEM[PC] == ADD Rd, Rn, Rm GPR[Rd] GPR[Rn] + GPR[Rm] **Based on original figure PC from [P&H PC CO&D, COPYRIGHT Elsevier. ALL RIGHTS RESERVED.] **Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.] 7
8 Single-Cycle Datapath for Data Movement Instructions 8
9 Load Instruction opcode Offset op2 Rn Rt 11 bits 9 bits 2 bits 5 bits 5 bits D-type! Assembly LDUR Rt reg, [Rn reg, offset]! Semantics if MEM[PC]==LDUR Rt, [Rn, offset] EA = sign-extend(offset) + GPR[Rn] GPR[Rt] MEM[EA] PC PC + 4 9
10 LDUR Datapath ADD 0 9:5 4:0 20: if MEM[PC]==LDUR Rt, [Rn reg, offset] EA = sign-extend(offset) + GPR[Rn] GPR[Rt] MEM[EA] PC PC + 4
11 Store Instruction opcode addoffset op2 Rn Rt 11 bits 9 bits 2 bits 5 bits 5 bits D-type! Assembly STUR Rt reg, [Rn reg, offset]! Semantics if MEM[PC]==STUR Rt, [Rn, offset] EA = sign-extend(offset) + GPR[Rn] MEM[EA] GPR[Rt] PC PC
12 STUR Datapath add 1 9:5 4:0 20: if MEM[PC]==STUR Rt, [Rn, offset] EA = sign-extend(offset) + GPR[Rn] MEM[EA] GPR[Rt] PC PC + 4
13 LDUR and STUR Datapath add isstore 9:5 4:0 4:0!isStore 20: isload **Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]
14 Datapath for R-Type and Load/Store Insts ALUop isstore 20:16 9:5 4:0 RFSrc2!isStore isstore 20: ALUSrc isload isstore isload MemtoReg isload **Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]
15 Single-Cycle Datapath for Control Flow Instructions 15
16 Unconditional Branch Instruction! Assembly B immediate 26! Machine encoding opcode BR_address B-type! Semantics if MEM[PC]==B immediate 26 target = { 36{immediate 26 [25]}, immediate 26, 2 b00 } PC PC+target 6 bits 26 bits 16
17 Unconditional Branch Datapath isb PCSrc 25:0 Sign extend and concat ALUop isstore 20:16 9:5 4:0 RFSrc2!isStore &!isb isstore 20: ALUSrc isload isstore isload if MEM[PC]==B immediate 26 target = {36{immediate 26 [25]}, immediate 26, 2 b00} PC PC+target MemtoReg isload **Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]
18 Other Instructions! What about BR, BL?! What about conditional branch instructions?! I type? WI type?
19 Your Scratchpad
20 Single-Cycle Control Logic 20
21 What Is To Come **Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.] 21
22 What is in That Control Box?! Combinational Logic: a function of Inst=MEM[PC]! Consider " R-type ALU instructions " LDUR and STUR " B 22
23 Review: Single-Cycle Datapath isb PCSrc 25:0 Sign extend and concat ALUop isstore 20:16 9:5 4:0 RFSrc2 isstore 20:12!isStore &!isb 9 64 ALUSrc isload isstore isload MemtoReg isload **Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]
24 Single-Bit Control Signals When De-asserted (0) When asserted (1) Equa`on RFsrc2 GPR reads register from inst[20:16] GPR reads register from inst[4:0] RFsrc2 = (opcode==stur) ALUSrc 2 nd ALU input from 2 nd GPR read port 2 nd ALU input from signextended 9-bit immediate ALUSrc = (opcode == LDUR) (opcode ==STUR) MemtoReg RegWrite Steer ALU result to GPR write port steer memory load to GPR wr. port MemtoReg= (opcode==ldur) GPR write disabled GPR write enabled RegWrite = (opcode!=stur) & (opcode!=b) 24
25 Single-Bit Control Signals When De-asserted (0) When asserted (1) Equa`on MemRead Memory read disabled Memory read port return load value MemRead = (opcode==ldur) MemWrite Memory write disabled Memory write enabled MemWrite = (opcode==stur) PCSrc next PC = PC + 4 next PC is PC+ branch target PCSrc = (opcode==b) 25
26 ALU Control! case opcode ALU selection operation according to opcode //ADD, SUB, AND, OR, XOR, NOR, etc. LDUR add STUR add CBZ cmp //compare register value to 0 don t care 26
27 Putting It All Together **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 27
28 Putting It All Together: R-Type ALU 1 0 ALUop 0 **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 28
29 Putting It All Together: LDUR 1 0 ADD 1 **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 29
30 Putting It All Together: STUR 0 1 ADD 0 **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 30
31 Putting It All Together: B 0 0 X 0 **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 31
32 Putting It All Together: CBZ (Taken) control signals dependent on data 0 0 cmp 0 **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 32
33 Putting It All Together: CBZ (Not Taken) control signals dependent on data 0 0 cmp 0 **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 33
34 Evaluating the Single-Cycle Machine 34
35 A Single-Cycle Microarchitecture! Is this a good idea/design? 35
36 Single-Cycle uarch Performance! Every instruction takes 1 cycle to execute! How long each instruction takes is determined by how long the slowest instruction takes to execute " Even if many other instructions do not need that long to execute! Clock cycle time of the microarchitecture is determined by how long it takes to complete the slowest instruction " Critical path of the design is determined by the processing time of the slowest instruction 36
37 What is the Slowest Instruction to Process?! All 5 steps take a single machine clock cycle to complete 1. Instruction fetch (IF) 2. Instruction decode and register operand fetch (ID/RF) 3. Execute/Evaluate memory address (EX/AG) 4. Memory operand fetch (MEM) 5. Store/writeback result (WB)! Do each of the above steps take the same time (latency) for all instructions? 37
38 Datapath Performance Analysis! Assume " memory units (read or write): 200 ps " ALU and adders: 100 ps " register file (read or write): 50 ps " other combinational logic: 0 ps steps IF ID EX MEM WB resources mem RF ALU / branch addr mem RF Delay R-type LDUR STUR B CBZ
39 R-Type ALU Datapath Delay 100ps 100ps 200ps 250ps 350ps 400ps **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 39
40 LDUR Datapath Delay 100ps 100ps 200ps 250ps 350ps 550ps 600ps **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 40
41 STUR Datapath Delay 100ps 100ps 200ps 250ps 550ps 350ps **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 41
42 CBZ (Taken) Datapath Delay 200ps 300ps 300ps 200ps **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 42
43 What About Control Logic?! How does that affect the critical path? 43
44 CBZ (Taken) Datapath and Control Delay 300ps 200ps 300ps 350ps 200ps 200ps 250ps 350ps **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 44
45 Assumption Revisited! Memory is not magic! What if memory sometimes takes 100ms to access?! Does it make sense to have a simple register to register add or branch to take {100ms+all else to do a memory operation}? 45
46 A Single-Cycle Microarchitecture! Is this a good idea/design? 46
47 Single Cycle uarch: Summary! Inefficient " All instructions run as slow as the slowest instruction! Not necessarily the simplest way to implement an ISA " Single-cycle implementation of REP MOVS (x86)?! Not easy to optimize/improve performance " Optimizing the common case (e.g. common instructions) does not work " Need to optimize the worst case all the time! All resources are not fully utilized " e.g., data memory access can t overlap with ALU operation! How to do better? 47
48 The Multi Cycle Approach! Break the execution of each instruction into multiple stages " E.g., IF, ID/RF, EX/AG, MEM, WB " Instead of 1 cycle to process all 5 stages " Take 5 cycles to process 5 stages, 1 cycle each! What determines the cycle time? " The slowest stage 48
49 Single-Cycle vs. Multi-Cycle! Single-cycle: 1 cycle per instruction " Cycle time is long F D E M W F D E M W Time! Multi-cycle: 5 cycles per instruction " Cycle time is short F D E M W F D E M W F D E M W Time 49
50 Can We Do Better?! What limitations do you see with the multi-cycle design?! Limited concurrency " Some hardware resources are idle during certain instruction processing stages " Fetch logic is idle when an instruction is being decoded or executed " Most of the datapath is idle when a memory access is happening 50
51 Can We Use the Idle Hardware to Improve Concurrency?! Goal: More concurrency # Higher instruction throughput (i.e., more work completed in one cycle)! Idea: When an instruction is using some resources in its processing phase, process other instructions on idle resources not needed by that instruction " E.g., when an instruction is being decoded, fetch the next instruction " E.g., when an instruction is being executed, decode another instruction " E.g., when an instruction is accessing data memory (ld/st), execute the next instruction " E.g., when an instruction is writing its result into the register file, access data memory for the next instruction 51
52 The Laundry Analogy! place one dirty load of clothes in the washer! when the washer is finished, place the wet load in the dryer! when the dryer is finished, take out the dry load and fold! when folding is finished, ask your roommate (??) to put the clothes away Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.] 52
53 Pipelining Multiple Loads of Laundry - 4 loads of laundry in parallel - no additional resources - throughput increased by 4 - latency per load is the same Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.] 53
54 Instruction Pipelining: Basic Idea! Pipeline the execution of multiple instructions! Idea: " Divide the instruction processing cycle into distinct stages of processing " Ensure there are enough hardware resources to process one instruction in each stage " Process a different instruction in each stage! Instructions consecutive in program order are processed in consecutive stages! Benefit: Increases instruction processing throughput! Downside: Start thinking about this 54
55 Multi-Cycle vs. Pipeline Illustration! Multi-cycle: 5 cycles per instruction F D E M W F D E M W F D E M W Time! Pipelined: 5 cycles per 5 instructions (steady state) F D E M W F D E M W F D E M W F D E M W F D E M W Time 55
56 Pipelining Instruction Processing 56
57 Remember: Instruction Processing Steps 1. Instruction fetch (IF) 2. Instruction decode and register operand fetch (ID/RF) 3. Execute/Evaluate memory address (EX/AG) 4. Memory operand fetch (MEM) 5. Store/writeback result (WB) 57
58 Remember the Single-Cycle Uarch Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 58
59 Review: LEGv8 Single-Cycle Datapath **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 59
60 Adding Pipeline Registers! Registers between stages to hold information produced in previous cycle Imm E B M Aout W B E IR D PC D +4 A E PC E +4 Aout M npc M MDR W Is this a good partitioning? Why not 4 or 6 stages? Why not different boundaries? **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 60
61 Pipeline Operation Examples! We ll look at load & store " Show pipeline usage in a single cycle " Highlight resources used 61
62 IF for Load, Store, **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 62
63 ID for Load, Store, **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 63
64 EX for Load **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 64
65 MEM for Load **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 65
66 WB for Load Wrong register number **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 66
67 Corrected Datapath for Load **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 67
68 EX for Store **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 68
69 MEM for Store **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 69
70 WB for Store **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 70
71 Pipeline Operation Examples! Consider the following instruction sequences " LDUR X10, [X1, 40] " SUB X11, X2, X3 " ADD X12, X3, X4 " LDUR X13, [X1, 48] " ADD X14, X5, X6 71
72 Single-Cycle Pipeline Diagram! State of pipeline at the 5th cycles **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 72
73 Multi-Cycle Pipeline Diagram **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 73
74 Illustrating Pipeline Operation: Operation View t 0 t 1 t 2 t 3 t 4 t 5 Inst 0 Inst 1 Inst 2 Inst 3 Inst 4 IF ID IF EX ID IF MEM EX ID IF WB MEM EX ID IF steady state (full pipeline) WB MEM EX ID IF WB MEM EX ID IF WB MEM EX ID IF 74
75 Illustrating Pipeline Operation: Resource View t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 IF I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 I 8 I 9 I 10 ID I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 I 8 I 9 EX I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 I 8 MEM I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 WB I 0 I 1 I 2 I 3 I 4 I 5 I 6 75
76 Pipelined Control Identical set of control points as the single-cycle uarch!! **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 76
77 Pipelined Control! Control signals derived from instruction " Decode once as in single-cycle implementation " Buffer signals until consumed What other options are there to derive pipeline control signals? **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 77
78 Pipelined Control **Based on original figure from [P&H CO&D, COPYRIGHT 2017 Elsevier. ALL RIGHTS RESERVED.] 78
COMPUTER ORGANIZATION AND DESIGN
ARM COMPUTER ORGANIZATION AND DESIGN Edition The Hardware/Software Interface Chapter 4 The Processor Modified and extended by R.J. Leduc - 2016 To understand this chapter, you will need to understand some
More informationComputer Architecture
Compter Architectre Lectre 4: Intro to icroarchitectre: Single- Cycle Dr. Ahmed Sallam Sez Canal University Based on original slides by Prof. Onr tl Review Compter Architectre Today and Basics (Lectres
More informationComputer Architecture
Compter Architectre Lectre 4: Intro to icroarchitectre: Single- Cycle Dr. Ahmed Sallam Sez Canal University Spring 25 Based on original slides by Prof. Onr tl Review Compter Architectre Today and Basics
More informationELEC 5200/6200 Computer Architecture and Design Spring 2017 Lecture 4: Datapath and Control
ELEC 52/62 Computer Architecture and Design Spring 217 Lecture 4: Datapath and Control Ujjwal Guin, Assistant Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849
More informationLecture 3: Single Cycle Microarchitecture. James C. Hoe Department of ECE Carnegie Mellon University
8 447 Lecture 3: Single Cycle Microarchitecture James C. Hoe Department of ECE Carnegie Mellon University 8 447 S8 L03 S, James C. Hoe, CMU/ECE/CALCM, 208 Your goal today Housekeeping first try at implementing
More informationLecture 12: Single-Cycle Control Unit. Spring 2018 Jason Tang
Lecture 12: Single-Cycle Control Unit Spring 2018 Jason Tang 1 Topics Control unit design Single cycle processor Control unit circuit implementation 2 Computer Organization Computer Processor Memory Devices
More informationThe Processor. Z. Jerry Shi Department of Computer Science and Engineering University of Connecticut. CSE3666: Introduction to Computer Architecture
The Processor Z. Jerry Shi Department of Computer Science and Engineering University of Connecticut CSE3666: Introduction to Computer Architecture Introduction CPU performance factors Instruction count
More informationCO Computer Architecture and Programming Languages CAPL. Lecture 18 & 19
CO2-3224 Computer Architecture and Programming Languages CAPL Lecture 8 & 9 Dr. Kinga Lipskoch Fall 27 Single Cycle Disadvantages & Advantages Uses the clock cycle inefficiently the clock cycle must be
More informationCMSC Computer Architecture Lecture 2: ISA. Prof. Yanjing Li Department of Computer Science University of Chicago
CMSC 22200 Computer Architecture Lecture 2: ISA Prof. Yanjing Li Department of Computer Science University of Chicago Administrative Stuff! Lab1 is out! " Due next Thursday (10/6)! Lab2 " Out next Thursday
More informationCSCI-564 Advanced Computer Architecture
CSCI-564 Advanced Computer Architecture Lecture 6: Pipelining Review Bo Wu Colorado School of Mines Wake up! Time to do laundry! The Laundry Analogy Place one dirty load of clothes in the washer When the
More informationCOMP2611: Computer Organization. The Pipelined Processor
COMP2611: Computer Organization The 1 2 Background 2 High-Performance Processors 3 Two techniques for designing high-performance processors by exploiting parallelism: Multiprocessing: parallelism among
More informationLecture 9: Microcontrolled Multi-Cycle Implementations. Who Am I?
18-447 Lecture 9: Microcontrolled Multi-Cycle Implementations S 10 L9-1 James C. Hoe José F. Martínez Electrical & Computer Engineering Carnegie Mellon University February 1, 2010 Who Am I? S 10 L9-2 Associate
More informationDatapath & Control. Readings: Computer Processor. Control. Input. Datapath. Output
Datapath & Control Readings: 4.1-4.4 Computer Processor Devices Control Input Datapath Output Datapath: System for performing operations on data, plus memory access. Control: Control the datapath in response
More informationFull Datapath. CSCI 402: Computer Architectures. The Processor (2) 3/21/19. Fengguang Song Department of Computer & Information Science IUPUI
CSCI 42: Computer Architectures The Processor (2) Fengguang Song Department of Computer & Information Science IUPUI Full Datapath Branch Target Instruction Fetch Immediate 4 Today s Contents We have looked
More informationDesign of Digital Circuits Lecture 13: Multi-Cycle Microarch. Prof. Onur Mutlu ETH Zurich Spring April 2017
Design of Digital Circuits Lecture 3: Multi-Cycle Microarch. Prof. Onur Mutlu ETH Zurich Spring 27 6 April 27 Agenda for Today & Next Few Lectures! Single-cycle Microarchitectures! Multi-cycle and Microprogrammed
More informationCOMPUTER ORGANIZATION AND DESIGN. The Hardware/Software Interface. Chapter 4. The Processor: A Based on P&H
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface Chapter 4 The Processor: A Based on P&H Introduction We will examine two MIPS implementations A simplified version A more realistic pipelined
More informationLecture 8: Control COS / ELE 375. Computer Architecture and Organization. Princeton University Fall Prof. David August
Lecture 8: Control COS / ELE 375 Computer Architecture and Organization Princeton University Fall 2015 Prof. David August 1 Datapath and Control Datapath The collection of state elements, computation elements,
More informationDesign of the MIPS Processor
Design of the MIPS Processor We will study the design of a simple version of MIPS that can support the following instructions: I-type instructions LW, SW R-type instructions, like ADD, SUB Conditional
More informationCSCI 402: Computer Architectures. Fengguang Song Department of Computer & Information Science IUPUI. Today s Content
3/6/8 CSCI 42: Computer Architectures The Processor (2) Fengguang Song Department of Computer & Information Science IUPUI Today s Content We have looked at how to design a Data Path. 4.4, 4.5 We will design
More informationChapter 4 The Processor 1. Chapter 4A. The Processor
Chapter 4 The Processor 1 Chapter 4A The Processor Chapter 4 The Processor 2 Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware
More informationWorking on the Pipeline
Computer Science 6C Spring 27 Working on the Pipeline Datapath Control Signals Computer Science 6C Spring 27 MemWr: write memory MemtoReg: ALU; Mem RegDst: rt ; rd RegWr: write register 4 PC Ext Imm6 Adder
More informationCENG 3420 Lecture 06: Datapath
CENG 342 Lecture 6: Datapath Bei Yu byu@cse.cuhk.edu.hk CENG342 L6. Spring 27 The Processor: Datapath & Control q We're ready to look at an implementation of the MIPS q Simplified to contain only: memory-reference
More informationProcessor Design Pipelined Processor (II) Hung-Wei Tseng
Processor Design Pipelined Processor (II) Hung-Wei Tseng Recap: Pipelining Break up the logic with pipeline registers into pipeline stages Each pipeline registers is clocked Each pipeline stage takes one
More informationChapter 4. The Processor. Computer Architecture and IC Design Lab
Chapter 4 The Processor Introduction CPU performance factors CPI Clock Cycle Time Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS
More informationDesign of the MIPS Processor (contd)
Design of the MIPS Processor (contd) First, revisit the datapath for add, sub, lw, sw. We will augment it to accommodate the beq and j instructions. Execution of branch instructions beq $at, $zero, L add
More informationCSE Computer Architecture I Fall 2009 Lecture 13 In Class Notes and Problems October 6, 2009
CSE 30321 Computer Architecture I Fall 2009 Lecture 13 In Class Notes and Problems October 6, 2009 Question 1: First, we briefly review the notion of a clock cycle (CC). Generally speaking a CC is the
More informationLecture 7 Pipelining. Peng Liu.
Lecture 7 Pipelining Peng Liu liupeng@zju.edu.cn 1 Review: The Single Cycle Processor 2 Review: Given Datapath,RTL -> Control Instruction Inst Memory Adr Op Fun Rt
More informationProcessor (I) - datapath & control. Hwansoo Han
Processor (I) - datapath & control Hwansoo Han Introduction CPU performance factors Instruction count - Determined by ISA and compiler CPI and Cycle time - Determined by CPU hardware We will examine two
More informationCENG 3420 Computer Organization and Design. Lecture 06: MIPS Processor - I. Bei Yu
CENG 342 Computer Organization and Design Lecture 6: MIPS Processor - I Bei Yu CEG342 L6. Spring 26 The Processor: Datapath & Control q We're ready to look at an implementation of the MIPS q Simplified
More informationCS 61C: Great Ideas in Computer Architecture Control and Pipelining
CS 6C: Great Ideas in Computer Architecture Control and Pipelining Instructors: Vladimir Stojanovic and Nicholas Weaver http://inst.eecs.berkeley.edu/~cs6c/sp6 Datapath Control Signals ExtOp: zero, sign
More informationCC 311- Computer Architecture. The Processor - Control
CC 311- Computer Architecture The Processor - Control Control Unit Functions: Instruction code Control Unit Control Signals Select operations to be performed (ALU, read/write, etc.) Control data flow (multiplexor
More informationLecture 13: Multi-Cycle Control Unit. Spring 2018 Jason Tang
Lecture 13: Multi-Cycle Control Unit Spring 2018 Jason Tang 1 Topics Multi-cycle path Multi-cycle implementation Multi-cycle control 2 Single-Cycle path A single-cycle path has, by necessity multiple s,
More informationLecture 15: Pipelining. Spring 2018 Jason Tang
Lecture 15: Pipelining Spring 2018 Jason Tang 1 Topics Overview of pipelining Pipeline performance Pipeline hazards 2 Sequential Laundry 6 PM 7 8 9 10 11 Midnight Time T a s k O r d e r A B C D 30 40 20
More informationCSEN 601: Computer System Architecture Summer 2014
CSEN 601: Computer System Architecture Summer 2014 Practice Assignment 5 Solutions Exercise 5-1: (Midterm Spring 2013) a. What are the values of the control signals (except ALUOp) for each of the following
More informationChapter 4. Instruction Execution. Introduction. CPU Overview. Multiplexers. Chapter 4 The Processor 1. The Processor.
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor The Processor - Introduction
More information3/12/2014. Single Cycle (Review) CSE 2021: Computer Organization. Single Cycle with Jump. Multi-Cycle Implementation. Why Multi-Cycle?
CSE 2021: Computer Organization Single Cycle (Review) Lecture-10b CPU Design : Pipelining-1 Overview, Datapath and control Shakil M. Khan 2 Single Cycle with Jump Multi-Cycle Implementation Instruction:
More informationCOMPUTER ORGANIZATION AND DESIGN. 5 th Edition. The Hardware/Software Interface. Chapter 4. The Processor
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition The Processor - Introduction
More informationMajor CPU Design Steps
Datapath Major CPU Design Steps. Analyze instruction set operations using independent RTN ISA => RTN => datapath requirements. This provides the the required datapath components and how they are connected
More informationComputer Architecture. Lecture 6.1: Fundamentals of
CS3350B Computer Architecture Winter 2015 Lecture 6.1: Fundamentals of Instructional Level Parallelism Marc Moreno Maza www.csd.uwo.ca/courses/cs3350b [Adapted from lectures on Computer Organization and
More informationInput. Output. Datapath: System for performing operations on data, plus memory access. Control: Control the datapath in response to instructions.
path & Control Readings: 4.1-4.4 Computer Processor Devices Control Input path Output path: System for performing operations on data, plus memory access. Control: Control the datapath in response to instructions.
More informationCOMPUTER ORGANIZATION AND DESIGN. 5 th Edition. The Hardware/Software Interface. Chapter 4. The Processor
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle
More informationLECTURE 5. Single-Cycle Datapath and Control
LECTURE 5 Single-Cycle Datapath and Control PROCESSORS In lecture 1, we reminded ourselves that the datapath and control are the two components that come together to be collectively known as the processor.
More informationEECS150 - Digital Design Lecture 10- CPU Microarchitecture. Processor Microarchitecture Introduction
EECS150 - Digital Design Lecture 10- CPU Microarchitecture Feb 18, 2010 John Wawrzynek Spring 2010 EECS150 - Lec10-cpu Page 1 Processor Microarchitecture Introduction Microarchitecture: how to implement
More informationLecture 3: The Processor (Chapter 4 of textbook) Chapter 4.1
Lecture 3: The Processor (Chapter 4 of textbook) Chapter 4.1 Introduction Chapter 4.1 Chapter 4.2 Review: MIPS (RISC) Design Principles Simplicity favors regularity fixed size instructions small number
More informationCS 351 Exam 2 Wed. 4/5/2017
CS 351 Exam 2 Wed. 4/5/2017 Name: Rules and Hints You may use one handwritten 8.5 11 cheat sheet (front and back). This is the only additional resource you may consult during this exam. No calculators.
More informationCS/COE0447: Computer Organization
CS/COE0447: Computer Organization and Assembly Language Datapath and Control Sangyeun Cho Dept. of Computer Science A simple MIPS We will design a simple MIPS processor that supports a small instruction
More informationCS/COE0447: Computer Organization
A simple MIPS CS/COE447: Computer Organization and Assembly Language Datapath and Control Sangyeun Cho Dept. of Computer Science We will design a simple MIPS processor that supports a small instruction
More informationCOMP303 - Computer Architecture Lecture 8. Designing a Single Cycle Datapath
COMP33 - Computer Architecture Lecture 8 Designing a Single Cycle Datapath The Big Picture The Five Classic Components of a Computer Processor Input Control Memory Datapath Output The Big Picture: The
More informationEE 457 Unit 6a. Basic Pipelining Techniques
EE 47 Unit 6a Basic Pipelining Techniques 2 Pipelining Introduction Consider a drink bottling plant Filling the bottle = 3 sec. Placing the cap = 3 sec. Labeling = 3 sec. Would you want Machine = Does
More informationLecture 4: Review of MIPS. Instruction formats, impl. of control and datapath, pipelined impl.
Lecture 4: Review of MIPS Instruction formats, impl. of control and datapath, pipelined impl. 1 MIPS Instruction Types Data transfer: Load and store Integer arithmetic/logic Floating point arithmetic Control
More informationLecture 10: Simple Data Path
Lecture 10: Simple Data Path Course so far Performance comparisons Amdahl s law ISA function & principles What do bits mean? Computer math Today Take QUIZ 6 over P&H.1-, before 11:59pm today How do computers
More informationEITF20: Computer Architecture Part2.2.1: Pipeline-1
EITF20: Computer Architecture Part2.2.1: Pipeline-1 Liang Liu liang.liu@eit.lth.se 1 Outline Reiteration Pipelining Harzards Structural hazards Data hazards Control hazards Implementation issues Multi-cycle
More information4.1.3 [10] < 4.3>Which resources (blocks) produce no output for this instruction? Which resources produce output that is not used?
2.10 [20] < 2.2, 2.5> For each LEGv8 instruction in Exercise 2.9 (copied below), show the value of the opcode (Op), source register (Rn), and target register (Rd or Rt) fields. For the I-type instructions,
More informationInf2C - Computer Systems Lecture 12 Processor Design Multi-Cycle
Inf2C - Computer Systems Lecture 12 Processor Design Multi-Cycle Boris Grot School of Informatics University of Edinburgh Previous lecture: single-cycle processor Inf2C Computer Systems - 2017-2018. Boris
More informationLecture 16: Pipeline Controls. Spring 2018 Jason Tang
Lecture 16: Pipeline Controls Spring 2018 Jason Tang 1 Topics Designing pipelined path Controlling pipeline operations 2 Pipelining Fetch Decode Execute Write ack Time Fetch Decode Execute Write ack Fetch
More informationCS 110 Computer Architecture. Pipelining. Guest Lecture: Shu Yin. School of Information Science and Technology SIST
CS 110 Computer Architecture Pipelining Guest Lecture: Shu Yin http://shtech.org/courses/ca/ School of Information Science and Technology SIST ShanghaiTech University Slides based on UC Berkley's CS61C
More informationLecture 3. Pipelining. Dr. Soner Onder CS 4431 Michigan Technological University 9/23/2009 1
Lecture 3 Pipelining Dr. Soner Onder CS 4431 Michigan Technological University 9/23/2009 1 A "Typical" RISC ISA 32-bit fixed format instruction (3 formats) 32 32-bit GPR (R0 contains zero, DP take pair)
More information361 control.1. EECS 361 Computer Architecture Lecture 9: Designing Single Cycle Control
36 control. EECS 36 Computer Architecture Lecture 9: Designing Single Cycle Control Recap: The MIPS Subset ADD and subtract add rd, rs, rt sub rd, rs, rt OR Imm: ori rt, rs, imm6 3 3 26 2 6 op rs rt rd
More informationMark Redekopp and Gandhi Puvvada, All rights reserved. EE 357 Unit 15. Single-Cycle CPU Datapath and Control
EE 37 Unit Single-Cycle CPU path and Control CPU Organization Scope We will build a CPU to implement our subset of the MIPS ISA Memory Reference Instructions: Load Word (LW) Store Word (SW) Arithmetic
More informationEECS150 - Digital Design Lecture 9- CPU Microarchitecture. Watson: Jeopardy-playing Computer
EECS150 - Digital Design Lecture 9- CPU Microarchitecture Feb 15, 2011 John Wawrzynek Spring 2011 EECS150 - Lec09-cpu Page 1 Watson: Jeopardy-playing Computer Watson is made up of a cluster of ninety IBM
More informationEITF20: Computer Architecture Part2.2.1: Pipeline-1
EITF20: Computer Architecture Part2.2.1: Pipeline-1 Liang Liu liang.liu@eit.lth.se 1 Outline Reiteration Pipelining Harzards Structural hazards Data hazards Control hazards Implementation issues Multi-cycle
More informationMIPS-Lite Single-Cycle Control
MIPS-Lite Single-Cycle Control COE68: Computer Organization and Architecture Dr. Gul N. Khan http://www.ee.ryerson.ca/~gnkhan Electrical and Computer Engineering Ryerson University Overview Single cycle
More informationPipelining Analogy. Pipelined laundry: overlapping execution. Parallelism improves performance. Four loads: Non-stop: Speedup = 8/3.5 = 2.3.
Pipelining Analogy Pipelined laundry: overlapping execution Parallelism improves performance Four loads: Speedup = 8/3.5 = 2.3 Non-stop: Speedup =2n/05n+15 2n/0.5n 1.5 4 = number of stages 4.5 An Overview
More informationCOMP303 Computer Architecture Lecture 9. Single Cycle Control
COMP33 Computer Architecture Lecture 9 Single Cycle Control A Single Cycle Datapath We have everything except control signals (underlined) RegDst busw Today s lecture will look at how to generate the control
More informationCPE 335 Computer Organization. Basic MIPS Architecture Part I
CPE 335 Computer Organization Basic MIPS Architecture Part I Dr. Iyad Jafar Adapted from Dr. Gheith Abandah slides http://www.abandah.com/gheith/courses/cpe335_s8/index.html CPE232 Basic MIPS Architecture
More informationComputer Systems Architecture Spring 2016
Computer Systems Architecture Spring 2016 Lecture 01: Introduction Shuai Wang Department of Computer Science and Technology Nanjing University [Adapted from Computer Architecture: A Quantitative Approach,
More informationChapter 4. The Processor
Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations A simplified
More informationChapter 4. The Processor
Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware 4.1 Introduction We will examine two MIPS implementations
More informationThe overall datapath for RT, lw,sw beq instrucution
Designing The Main Control Unit: Remember the three instruction classes {R-type, Memory, Branch}: a) R-type : Op rs rt rd shamt funct 1.src 2.src dest. 31-26 25-21 20-16 15-11 10-6 5-0 a) Memory : Op rs
More informationMIPS Pipelining. Computer Organization Architectures for Embedded Computing. Wednesday 8 October 14
MIPS Pipelining Computer Organization Architectures for Embedded Computing Wednesday 8 October 14 Many slides adapted from: Computer Organization and Design, Patterson & Hennessy 4th Edition, 2011, MK
More informationProcessor: Multi- Cycle Datapath & Control
Processor: Multi- Cycle Datapath & Control (Based on text: David A. Patterson & John L. Hennessy, Computer Organization and Design: The Hardware/Software Interface, 3 rd Ed., Morgan Kaufmann, 27) COURSE
More informationCS 351 Exam 2, Section 1 Wed. 11/2/2016
CS 351 Exam 2, Section 1 Wed. 11/2/2016 Name: Rules and Hints You may use one handwritten 8.5 11 cheat sheet (front and back). This is the only additional resource you may consult during this exam. No
More informationThe Processor: Datapath & Control
Orange Coast College Business Division Computer Science Department CS 116- Computer Architecture The Processor: Datapath & Control Processor Design Step 3 Assemble Datapath Meeting Requirements Build the
More informationCPE 335. Basic MIPS Architecture Part II
CPE 335 Computer Organization Basic MIPS Architecture Part II Dr. Iyad Jafar Adapted from Dr. Gheith Abandah slides http://www.abandah.com/gheith/courses/cpe335_s08/index.html CPE232 Basic MIPS Architecture
More informationCS 152 Computer Architecture and Engineering
CS 152 Computer Architecture and Engineering Lecture 7 Pipelining I 2006-9-19 John Lazzaro (www.cs.berkeley.edu/~lazzaro) TAs: Udam Saini and Jue Sun www-inst.eecs.berkeley.edu/~cs152/ Last Time: ipod
More informationChapter 5: The Processor: Datapath and Control
Chapter 5: The Processor: Datapath and Control Overview Logic Design Conventions Building a Datapath and Control Unit Different Implementations of MIPS instruction set A simple implementation of a processor
More informationChapter 4. The Processor
Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations A simplified
More informationLecture Topics. Announcements. Today: Single-Cycle Processors (P&H ) Next: continued. Milestone #3 (due 2/9) Milestone #4 (due 2/23)
Lecture Topics Today: Single-Cycle Processors (P&H 4.1-4.4) Next: continued 1 Announcements Milestone #3 (due 2/9) Milestone #4 (due 2/23) Exam #1 (Wednesday, 2/15) 2 1 Exam #1 Wednesday, 2/15 (3:00-4:20
More informationCPU Organization (Design)
ISA Requirements CPU Organization (Design) Datapath Design: Capabilities & performance characteristics of principal Functional Units (FUs) needed by ISA instructions (e.g., Registers, ALU, Shifters, Logic
More informationPage 1. Pipelining: Its Natural! Chapter 3. Pipelining. Pipelined Laundry Start work ASAP. Sequential Laundry A B C D. 6 PM Midnight
Pipelining: Its Natural! Chapter 3 Pipelining Laundry Example Ann, Brian, Cathy, Dave each have one load of clothes to wash, dry, and fold Washer takes 30 minutes A B C D Dryer takes 40 minutes Folder
More informationPipelining. Maurizio Palesi
* Pipelining * Adapted from David A. Patterson s CS252 lecture slides, http://www.cs.berkeley/~pattrsn/252s98/index.html Copyright 1998 UCB 1 References John L. Hennessy and David A. Patterson, Computer
More information361 datapath.1. Computer Architecture EECS 361 Lecture 8: Designing a Single Cycle Datapath
361 datapath.1 Computer Architecture EECS 361 Lecture 8: Designing a Single Cycle Datapath Outline of Today s Lecture Introduction Where are we with respect to the BIG picture? Questions and Administrative
More informationDesigning a Multicycle Processor
Designing a Multicycle Processor Arquitectura de Computadoras Arturo Díaz D PérezP Centro de Investigación n y de Estudios Avanzados del IPN adiaz@cinvestav.mx Arquitectura de Computadoras Multicycle-
More informationSystems Architecture
Systems Architecture Lecture 15: A Simple Implementation of MIPS Jeremy R. Johnson Anatole D. Ruslanov William M. Mongan Some or all figures from Computer Organization and Design: The Hardware/Software
More informationCS3350B Computer Architecture Quiz 3 March 15, 2018
CS3350B Computer Architecture Quiz 3 March 15, 2018 Student ID number: Student Last Name: Question 1.1 1.2 1.3 2.1 2.2 2.3 Total Marks The quiz consists of two exercises. The expected duration is 30 minutes.
More informationThe Processor (1) Jinkyu Jeong Computer Systems Laboratory Sungkyunkwan University
The Processor (1) Jinkyu Jeong (jinkyu@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu Jeong (jinkyu@skku.edu)
More informationInf2C - Computer Systems Lecture Processor Design Single Cycle
Inf2C - Computer Systems Lecture 10-11 Processor Design Single Cycle Boris Grot School of Informatics University of Edinburgh Previous lectures Combinational circuits Combinations of gates (INV, AND, OR,
More informationRISC Pipeline. Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University. See: P&H Chapter 4.6
RISC Pipeline Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University See: P&H Chapter 4.6 A Processor memory inst register file alu PC +4 +4 new pc offset target imm control extend =? cmp
More informationCPS104 Computer Organization and Programming Lecture 19: Pipelining. Robert Wagner
CPS104 Computer Organization and Programming Lecture 19: Pipelining Robert Wagner cps 104 Pipelining..1 RW Fall 2000 Lecture Overview A Pipelined Processor : Introduction to the concept of pipelined processor.
More informationReview: Abstract Implementation View
Review: Abstract Implementation View Split memory (Harvard) model - single cycle operation Simplified to contain only the instructions: memory-reference instructions: lw, sw arithmetic-logical instructions:
More informationCSE 2021 COMPUTER ORGANIZATION
CSE 22 COMPUTER ORGANIZATION HUGH CHESSER CHESSER HUGH CSEB 2U 2U CSEB Agenda Topics:. Sample Exam/Quiz Q - Review 2. Multiple cycle implementation Patterson: Section 4.5 Reminder: Quiz #2 Next Wednesday
More informationCS Computer Architecture Spring Week 10: Chapter
CS 35101 Computer Architecture Spring 2008 Week 10: Chapter 5.1-5.3 Materials adapated from Mary Jane Irwin (www.cse.psu.edu/~mji) and Kevin Schaffer [adapted from D. Patterson slides] CS 35101 Ch 5.1
More informationComputer Organization and Structure. Bing-Yu Chen National Taiwan University
Computer Organization and Structure Bing-Yu Chen National Taiwan University The Processor Logic Design Conventions Building a Datapath A Simple Implementation Scheme An Overview of Pipelining Pipelined
More informationDesign of Digital Circuits Lecture 15: Pipelining. Prof. Onur Mutlu ETH Zurich Spring April 2017
Design of Digital Circuits Lecture 5: Pipelining Prof. Onur Mutlu ETH Zurich Spring 27 3 April 27 Agenda for Today & Next Few Lectures! Single-cycle Microarchitectures! Multi-cycle and Microprogrammed
More informationLecture 5 and 6. ICS 152 Computer Systems Architecture. Prof. Juan Luis Aragón
ICS 152 Computer Systems Architecture Prof. Juan Luis Aragón Lecture 5 and 6 Multicycle Implementation Introduction to Microprogramming Readings: Sections 5.4 and 5.5 1 Review of Last Lecture We have seen
More informationCOMPUTER ORGANIZATION AND DESIGN
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle
More informationCOSC 6385 Computer Architecture - Pipelining
COSC 6385 Computer Architecture - Pipelining Fall 2006 Some of the slides are based on a lecture by David Culler, Instruction Set Architecture Relevant features for distinguishing ISA s Internal storage
More informationEITF20: Computer Architecture Part2.2.1: Pipeline-1
EITF20: Computer Architecture Part2.2.1: Pipeline-1 Liang Liu liang.liu@eit.lth.se 1 Outline Reiteration Pipelining Harzards Structural hazards Data hazards Control hazards Implementation issues Multi-cycle
More informationSingle Cycle Data Path
Single ycle ata Path S 365 Lecture 6 Prof. Yih Huang S365 1 MIPS Lite We're ready to look at an implementation of the MIPS Simplified to support only: memory-reference instructions: lw, sw arithmetic-logical
More informationENE 334 Microprocessors
ENE 334 Microprocessors Lecture 6: Datapath and Control : Dejwoot KHAWPARISUTH Adapted from Computer Organization and Design, 3 th & 4 th Edition, Patterson & Hennessy, 2005/2008, Elsevier (MK) http://webstaff.kmutt.ac.th/~dejwoot.kha/
More information