CS 2630 Computer Organization. Meeting 13: Faster arithmetic and more operations Brandon Myers University of Iowa

Size: px
Start display at page:

Download "CS 2630 Computer Organization. Meeting 13: Faster arithmetic and more operations Brandon Myers University of Iowa"

Transcription

1 CS 2630 Computer Organization Meeting 13: Faster arithmetic and more operations Brandon Myers University of Iowa

2 Where we are going Compiler Instruction set architecture (e.g., MIPS) translating source code (C or Java) Programs to assembly language And linking your code to Library code How the software talks To the hardware Memory system Processor Datapath & Control Digital logic I/O system How a processor runs MIPS Programs! How switches (1 or 0) can be used to build Interesting functions: from integer arithmetic to programmable computers

3 Ingredients for a processor Combinational logic arithmetic and bitwise operations multiplexors (pick 1 out of of N inputs) control logic branch calculation address calculation start learning how to build these combinational logic circuits Synchronous logic (we ll get to these later) registers program counter, or PC data memory instruction memory

4 How do we add two numbers addu $t0, $t1, $t2 We know: The numbers are physically stored in registers as bits The sum of two numbers is a function we can implement using combinational logic

5 Delay of adder circuit 1-bit adder delay: sum=2 1-bit adder delay: carry=1 0 A0 B0 A1 B1 A2 B2 A31 B Sum0 Sum1 Sum2 Sum31 This adder is called ripple carry adder

6 Carry-select adder

7 Peer instruction 1 time signal is available shown in red/bold delays: sum: 1 carry: 1 mux: What is the delay from the time A and B are available to when Sum is available? 2

8 Administrivia Review session last night (get notes from peers if you were not there) No DYB today Midterm this Thursday, 10/6, in class open notes / open textbook (recommend making a single sheet of important information rather than flipping through book) no electronics allowed

9 Best case delay of adders? O(log n) compute carries p means propagate a carry g means generate a carry use carries to finish the sums important: p and g are not functions of c

10 Best case delay of adders? O(log n) compute carries critical path use carrys to finish the sums

11 Shifting by a constant

12 Variable shifter: first attempt with 1-bit muxes

13 Variable shifter, similar design with 8-bit mux hardwired shifts by each possible shift amount Can you think of a design that avoids using a huge 8-bit x 8-choice mux? e.g., using only 8-bit x 2-choice muxes and hardwired shifters? pick which one using the shift amount

14 Multi-stage shifter using the magic of binary decision-making Hint: Recall the envelopes from HW1 another solution (but uses more 2-input MUXs) is to build the 8-input MUX on the previous slide using 2-input MUXs, like a soccer tournament with 8 teams and one champion

15 Multiplication Evaluate x on paper Evaluate x on paper

16 Peer instruction Build a 2-bit multiplier (4-bit output) you may use any number of example test cases: 01 * 01 = * 01 = * 11 = * 11 = 1001

17 Ingredients for a processor Combinational logic arithmetic and bitwise operations multiplexors (pick 1 out of of N inputs) control logic branch calculation address calculation Synchronous logic registers program counter, or PC data memory instruction memory

18

19 Basic memory element: flip-flop clock pulse rising edge value to store D Q stored value on the rising edge of the clock signal, the value on input D is captured into the flip-flop value of the output Q is the value stored in the flip-flop

20 Clock signal Analogy with a clock on the wall: every tick happens instantaneously at the rising edge the period is the time between ticks period of a wall clock: 1 second period of a typical digital logic clock: nanoseconds or less

21 Peer instruction D Q 0 NAND 1 T0 T1 T2 Q 0 1 0??? What is the value of Q after T0, after T1, and after T2? (enter three numbers: 0 or 1, 0 or 1, 0 or 1)

22 Next steps use 32 flip-flops in parallel to create 32-bit registers for our MIPS processor learn about Finite State Machines, a way of thinking about circuits with flip-flops and combinational logic arrange stored bits into large memories and learn how to lookup values using an address

Many ways to build logic out of MOSFETs

Many ways to build logic out of MOSFETs Many ways to build logic out of MOSFETs pass transistor logic (most similar to the first switch logic we saw) static CMOS logic (what we saw last time) dynamic CMOS logic Clock=0 precharges X through the

More information

ECE 341 Midterm Exam

ECE 341 Midterm Exam ECE 341 Midterm Exam Time allowed: 75 minutes Total Points: 75 Points Scored: Name: Problem No. 1 (8 points) For each of the following statements, indicate whether the statement is TRUE or FALSE: (a) A

More information

Where we are going (today)

Where we are going (today) Where we are going (today) Q: How do we arrange bits in the memory of the computer? (why do we care? we want the computer to store many individual numbers) A: bytes and words 10110000 00001110 01000010

More information

Where we are going (today)

Where we are going (today) Where we are going (today) Q: How do we arrange bits in the memory of the computer? (why do we care? we want the computer to store many individual numbers) A: bytes and words 10110000 00001110 01000010

More information

Where are we? Compiler. translating source code (C or Java) Programs to assembly language And linking your code to Library code

Where are we? Compiler. translating source code (C or Java) Programs to assembly language And linking your code to Library code Where are we? Compiler Instruction set architecture (e.g., MIPS) translating source code (C or Java) Programs to assembly language And linking your code to Library code How the software talks To the hardware

More information

CS 31: Intro to Systems Digital Logic. Kevin Webb Swarthmore College February 2, 2016

CS 31: Intro to Systems Digital Logic. Kevin Webb Swarthmore College February 2, 2016 CS 31: Intro to Systems Digital Logic Kevin Webb Swarthmore College February 2, 2016 Reading Quiz Today Hardware basics Machine memory models Digital signals Logic gates Circuits: Borrow some paper if

More information

Levels in Processor Design

Levels in Processor Design Levels in Processor Design Circuit design Keywords: transistors, wires etc.results in gates, flip-flops etc. Logical design Putting gates (AND, NAND, ) and flip-flops together to build basic blocks such

More information

ECE 341 Midterm Exam

ECE 341 Midterm Exam ECE 341 Midterm Exam Time allowed: 90 minutes Total Points: 75 Points Scored: Name: Problem No. 1 (10 points) For each of the following statements, indicate whether the statement is TRUE or FALSE: (a)

More information

CS 31: Intro to Systems Digital Logic. Kevin Webb Swarthmore College February 3, 2015

CS 31: Intro to Systems Digital Logic. Kevin Webb Swarthmore College February 3, 2015 CS 31: Intro to Systems Digital Logic Kevin Webb Swarthmore College February 3, 2015 Reading Quiz Today Hardware basics Machine memory models Digital signals Logic gates Circuits: Borrow some paper if

More information

6.1 Combinational Circuits. George Boole ( ) Claude Shannon ( )

6.1 Combinational Circuits. George Boole ( ) Claude Shannon ( ) 6. Combinational Circuits George Boole (85 864) Claude Shannon (96 2) Signals and Wires Digital signals Binary (or logical ) values: or, on or off, high or low voltage Wires. Propagate digital signals

More information

CSC258: Computer Organization. Memory Systems

CSC258: Computer Organization. Memory Systems CSC258: Computer Organization Memory Systems 1 Summer Independent Studies I m looking for a few students who will be working on campus this summer. In addition to the paid positions posted earlier, I have

More information

CS61C : Machine Structures

CS61C : Machine Structures inst.eecs.berkeley.edu/~cs61c/su06 CS61C : Machine Structures Lecture #14: Combinational Logic, Gates, and State 2006-07-20 CS 61C L14 Combinational Logic (1) Andy Carle What are Machine Structures? Software

More information

University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences. Spring 2010 May 10, 2010

University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences. Spring 2010 May 10, 2010 University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS150 J. Wawrzynek Spring 2010 May 10, 2010 Final Exam Name: ID number: This is

More information

1. Prove that if you have tri-state buffers and inverters, you can build any combinational logic circuit. [4]

1. Prove that if you have tri-state buffers and inverters, you can build any combinational logic circuit. [4] HW 3 Answer Key 1. Prove that if you have tri-state buffers and inverters, you can build any combinational logic circuit. [4] You can build a NAND gate from tri-state buffers and inverters and thus you

More information

CS 2630 Computer Organization. Meeting 4: Intro to Architecture (specifically, MIPS) Brandon Myers University of Iowa

CS 2630 Computer Organization. Meeting 4: Intro to Architecture (specifically, MIPS) Brandon Myers University of Iowa CS 2630 Computer Organization Meeting 4: Intro to Architecture (specifically, MIPS) Brandon Myers University of Iowa Where we are going Compiler Instruction set architecture (e.g., MIPS) translating source

More information

Topics. Computer Organization CS Exam 2 Review. Infix Notation. Reverse Polish Notation (RPN)

Topics. Computer Organization CS Exam 2 Review. Infix Notation. Reverse Polish Notation (RPN) Computer Organization CS 231-01 Exam 2 Review Dr. William H. Robinson October 11, 2004 http://eecs.vanderbilt.edu/courses/cs231/ Topics Education is a progressive discovery of our own ignorance. Will Durant

More information

CS311 Lecture: CPU Implementation: The Register Transfer Level, the Register Set, Data Paths, and the ALU

CS311 Lecture: CPU Implementation: The Register Transfer Level, the Register Set, Data Paths, and the ALU CS311 Lecture: CPU Implementation: The Register Transfer Level, the Register Set, Data Paths, and the ALU Last revised October 15, 2007 Objectives: 1. To show how a CPU is constructed out of a regiser

More information

Design Example: 4-bit Multiplier

Design Example: 4-bit Multiplier Design Example: 4-bit Multiplier Consider how we normally multiply numbers: 123 x 264 492 7380 24600 32472 Binary multiplication is similar. (Note that the product of two 4-bit numbers is potentially an

More information

Digital Circuit Design and Language. Datapath Design. Chang, Ik Joon Kyunghee University

Digital Circuit Design and Language. Datapath Design. Chang, Ik Joon Kyunghee University Digital Circuit Design and Language Datapath Design Chang, Ik Joon Kyunghee University Typical Synchronous Design + Control Section : Finite State Machine + Data Section: Adder, Multiplier, Shift Register

More information

ASIC = Application specific integrated circuit

ASIC = Application specific integrated circuit ASIC = Application specific integrated circuit CS 2630 Computer Organization Meeting 19: Building a MIPS processor Brandon Myers University of Iowa The goal: implement most of MIPS So far Implementing

More information

University of California, Berkeley College of Engineering Department of Electrical Engineering and Computer Science

University of California, Berkeley College of Engineering Department of Electrical Engineering and Computer Science University of California, Berkeley College of Engineering Department of Electrical Engineering and Computer Science Spring 2000 Prof. Bob Brodersen Midterm 1 March 15, 2000 CS152: Computer Architecture

More information

6.1 Combinational Circuits. George Boole ( ) Claude Shannon ( )

6.1 Combinational Circuits. George Boole ( ) Claude Shannon ( ) 6. Combinational Circuits George Boole (85 864) Claude Shannon (96 2) Digital signals Binary (or logical ) values: or, on or off, high or low voltage Wires. Propagate logical values from place to place.

More information

REGISTER TRANSFER LANGUAGE

REGISTER TRANSFER LANGUAGE REGISTER TRANSFER LANGUAGE The operations executed on the data stored in the registers are called micro operations. Classifications of micro operations Register transfer micro operations Arithmetic micro

More information

CS Computer Architecture Spring Week 10: Chapter

CS Computer Architecture Spring Week 10: Chapter CS 35101 Computer Architecture Spring 2008 Week 10: Chapter 5.1-5.3 Materials adapated from Mary Jane Irwin (www.cse.psu.edu/~mji) and Kevin Schaffer [adapted from D. Patterson slides] CS 35101 Ch 5.1

More information

CS 151 Midterm. (Last Name) (First Name)

CS 151 Midterm. (Last Name) (First Name) CS 151 Midterm Name Student ID Signature :, (Last Name) (First Name) : : Instructions: 1. Please verify that your paper contains 13 pages including this cover. 2. Write down your Student-Id on the top

More information

Lecture Topics. Announcements. Today: Integer Arithmetic (P&H ) Next: continued. Consulting hours. Introduction to Sim. Milestone #1 (due 1/26)

Lecture Topics. Announcements. Today: Integer Arithmetic (P&H ) Next: continued. Consulting hours. Introduction to Sim. Milestone #1 (due 1/26) Lecture Topics Today: Integer Arithmetic (P&H 3.1-3.4) Next: continued 1 Announcements Consulting hours Introduction to Sim Milestone #1 (due 1/26) 2 1 Overview: Integer Operations Internal representation

More information

Chapter 5: The Processor: Datapath and Control

Chapter 5: The Processor: Datapath and Control Chapter 5: The Processor: Datapath and Control Overview Logic Design Conventions Building a Datapath and Control Unit Different Implementations of MIPS instruction set A simple implementation of a processor

More information

CS61C : Machine Structures

CS61C : Machine Structures inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #22 CPU Design: Pipelining to Improve Performance II 2007-8-1 Scott Beamer, Instructor CS61C L22 CPU Design : Pipelining to Improve Performance

More information

ECE260: Fundamentals of Computer Engineering

ECE260: Fundamentals of Computer Engineering Datapath for a Simplified Processor James Moscola Dept. of Engineering & Computer Science York College of Pennsylvania Based on Computer Organization and Design, 5th Edition by Patterson & Hennessy Introduction

More information

Question Total Possible Test Score Total 100

Question Total Possible Test Score Total 100 Computer Engineering 2210 Final Name 11 problems, 100 points. Closed books, closed notes, no calculators. You would be wise to read all problems before beginning, note point values and difficulty of problems,

More information

Microcomputers. Outline. Number Systems and Digital Logic Review

Microcomputers. Outline. Number Systems and Digital Logic Review Microcomputers Number Systems and Digital Logic Review Lecture 1-1 Outline Number systems and formats Common number systems Base Conversion Integer representation Signed integer representation Binary coded

More information

University of Toronto Mississauga. Flip to the back cover and write down your name and student number.

University of Toronto Mississauga. Flip to the back cover and write down your name and student number. University of Toronto Mississauga Midterm Test Course: CSC258H5 Winter 2016 Instructor: Larry Zhang Duration: 50 minutes Aids allowed: None Last Name: Given Name: Flip to the back cover and write down

More information

LECTURE 4. Logic Design

LECTURE 4. Logic Design LECTURE 4 Logic Design LOGIC DESIGN The language of the machine is binary that is, sequences of 1 s and 0 s. But why? At the hardware level, computers are streams of signals. These signals only have two

More information

Fast Arithmetic. Philipp Koehn. 19 October 2016

Fast Arithmetic. Philipp Koehn. 19 October 2016 Fast Arithmetic Philipp Koehn 19 October 2016 1 arithmetic Addition (Immediate) 2 Load immediately one number (s0 = 2) li $s0, 2 Add 4 ($s1 = $s0 + 4 = 6) addi $s1, $s0, 4 Subtract 3 ($s2 = $s1-3 = 3)

More information

CSE140: Components and Design Techniques for Digital Systems

CSE140: Components and Design Techniques for Digital Systems CSE4: Components and Design Techniques for Digital Systems Tajana Simunic Rosing Announcements and Outline Check webct grades, make sure everything is there and is correct Pick up graded d homework at

More information

Review. Pipeline big-delay CL for faster clock Finite State Machines extremely useful You ll see them again in 150, 152 & 164

Review. Pipeline big-delay CL for faster clock Finite State Machines extremely useful You ll see them again in 150, 152 & 164 CS61C L17 Combinatorial Logic Blocks (1) inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #17 Combinatorial Logic Blocks 2007-7-24 Scott Beamer, Instructor Review Pipeline big-delay CL

More information

Philadelphia University Department of Computer Science. By Dareen Hamoudeh

Philadelphia University Department of Computer Science. By Dareen Hamoudeh Philadelphia University Department of Computer Science By Dareen Hamoudeh 1.REGISTERS WHAT IS REGISTER? register is a quickly accessible location available to a computer's central processing unit (CPU).

More information

Where we are going (today)

Where we are going (today) Where we are going (today) Q: How do we arrange bits in the memory of the computer? (why do we care? we want the computer to store many individual numbers) A: bytes and words 10110000 00001110 01000010

More information

CS/COE0447: Computer Organization

CS/COE0447: Computer Organization CS/COE0447: Computer Organization and Assembly Language Chapter 3 Sangyeun Cho Dept. of Computer Science Five classic components I am like a control tower I am like a pack of file folders I am like a conveyor

More information

CS/COE0447: Computer Organization

CS/COE0447: Computer Organization Five classic components CS/COE0447: Computer Organization and Assembly Language I am like a control tower I am like a pack of file folders Chapter 3 I am like a conveyor belt + service stations I exchange

More information

Department of Electrical and Computer Engineering Introduction to Computer Engineering I (ECSE-221) Assignment 3: Sequential Logic

Department of Electrical and Computer Engineering Introduction to Computer Engineering I (ECSE-221) Assignment 3: Sequential Logic Available: February 16, 2009 Due: March 9, 2009 Department of Electrical and Computer Engineering (ECSE-221) Assignment 3: Sequential Logic Information regarding submission and final deposition time can

More information

Truth Table! Review! Use this table and techniques we learned to transform from 1 to another! ! Gate Diagram! Today!

Truth Table! Review! Use this table and techniques we learned to transform from 1 to another! ! Gate Diagram! Today! CS61C L17 Combinational Logic Blocks and Intro to CPU Design (1)! inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 17 Combinational Logic Blocks and Intro to CPU Design 2010-07-20!!!Instructor

More information

BUILDING BLOCKS OF A BASIC MICROPROCESSOR. Part 1 PowerPoint Format of Lecture 3 of Book

BUILDING BLOCKS OF A BASIC MICROPROCESSOR. Part 1 PowerPoint Format of Lecture 3 of Book BUILDING BLOCKS OF A BASIC MICROPROCESSOR Part PowerPoint Format of Lecture 3 of Book Decoder Tri-state device Full adder, full subtractor Arithmetic Logic Unit (ALU) Memories Example showing how to write

More information

FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1

FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1 FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1 Anurag Dwivedi Digital Design : Bottom Up Approach Basic Block - Gates Digital Design : Bottom Up Approach Gates -> Flip Flops Digital

More information

CSE 141L Computer Architecture Lab Fall Lecture 3

CSE 141L Computer Architecture Lab Fall Lecture 3 CSE 141L Computer Architecture Lab Fall 2005 Lecture 3 Pramod V. Argade November 1, 2005 Fall 2005 CSE 141L Course Schedule Lecture # Date Day Lecture Topic Lab Due 1 9/27 Tuesday No Class 2 10/4 Tuesday

More information

Cpr E 281 FINAL PROJECT ELECTRICAL AND COMPUTER ENGINEERING IOWA STATE UNIVERSITY. FINAL Project. Objectives. Project Selection

Cpr E 281 FINAL PROJECT ELECTRICAL AND COMPUTER ENGINEERING IOWA STATE UNIVERSITY. FINAL Project. Objectives. Project Selection Objectives The main objective of the final project is to teach you how to put together all of the class material that you have learned so far in order to program the Altera DE2 board to carry out an independent

More information

Review. N-bit adder-subtractor done using N 1- bit adders with XOR gates on input. Lecture #19 Designing a Single-Cycle CPU

Review. N-bit adder-subtractor done using N 1- bit adders with XOR gates on input. Lecture #19 Designing a Single-Cycle CPU CS6C L9 CPU Design : Designing a Single-Cycle CPU () insteecsberkeleyedu/~cs6c CS6C : Machine Structures Lecture #9 Designing a Single-Cycle CPU 27-7-26 Scott Beamer Instructor AI Focuses on Poker Review

More information

11/22/1999 7pm - 9pm. Name: Login Name: Preceptor Name: Precept Number:

11/22/1999 7pm - 9pm. Name: Login Name: Preceptor Name: Precept Number: Login Preceptor Precept Number: Computer Science 126 Second Midterm Exam 11/22/1999 7pm - 9pm This exam has 10 questions. The weight of each question is printed in the table below and next to each question.

More information

CPS311 Lecture: CPU Implementation: The Register Transfer Level, the Register Set, Data Paths, and the ALU

CPS311 Lecture: CPU Implementation: The Register Transfer Level, the Register Set, Data Paths, and the ALU CPS311 Lecture: CPU Implementation: The Register Transfer Level, the Register Set, Data Paths, and the ALU Objectives: Last revised August 5, 2015 1. To show how a CPU is constructed out of a register

More information

ECE 2300 Digital Logic & Computer Organization. More Sequential Logic Verilog

ECE 2300 Digital Logic & Computer Organization. More Sequential Logic Verilog ECE 2300 Digital Logic & Computer Organization Spring 2018 More Sequential Logic Verilog Lecture 7: 1 Announcements HW3 will be posted tonight Prelim 1 Thursday March 1, in class Coverage: Lectures 1~7

More information

Mark Redekopp, All rights reserved. EE 352 Unit 8. HW Constructs

Mark Redekopp, All rights reserved. EE 352 Unit 8. HW Constructs EE 352 Unit 8 HW Constructs Logic Circuits Combinational logic Perform a specific function (mapping of 2 n input combinations to desired output combinations) No internal state or feedback Given a set of

More information

CENG 3420 Computer Organization and Design. Lecture 06: MIPS Processor - I. Bei Yu

CENG 3420 Computer Organization and Design. Lecture 06: MIPS Processor - I. Bei Yu CENG 342 Computer Organization and Design Lecture 6: MIPS Processor - I Bei Yu CEG342 L6. Spring 26 The Processor: Datapath & Control q We're ready to look at an implementation of the MIPS q Simplified

More information

CS 261 Fall Mike Lam, Professor. Combinational Circuits

CS 261 Fall Mike Lam, Professor. Combinational Circuits CS 261 Fall 2017 Mike Lam, Professor Combinational Circuits The final frontier Java programs running on Java VM C programs compiled on Linux Assembly / machine code on CPU + memory??? Switches and electric

More information

University of Technology

University of Technology University of Technology Lecturer: Dr. Sinan Majid Course Title: microprocessors 4 th year Lecture 13 Counters Overview Counters are important components in computers The increment or decrement by one

More information

a, b sum module add32 sum vector bus sum[31:0] sum[0] sum[31]. sum[7:0] sum sum overflow module add32_carry assign

a, b sum module add32 sum vector bus sum[31:0] sum[0] sum[31]. sum[7:0] sum sum overflow module add32_carry assign I hope you have completed Part 1 of the Experiment. This lecture leads you to Part 2 of the experiment and hopefully helps you with your progress to Part 2. It covers a number of topics: 1. How do we specify

More information

Topic #6. Processor Design

Topic #6. Processor Design Topic #6 Processor Design Major Goals! To present the single-cycle implementation and to develop the student's understanding of combinational and clocked sequential circuits and the relationship between

More information

378: Machine Organization and Assembly Language

378: Machine Organization and Assembly Language 378: Machine Organization and Assembly Language Spring 2010 Luis Ceze Slides adapted from: UIUC, Luis Ceze, Larry Snyder, Hal Perkins 1 What is computer architecture about? Computer architecture is the

More information

Injntu.com Injntu.com Injntu.com R16

Injntu.com Injntu.com Injntu.com R16 1. a) What are the three methods of obtaining the 2 s complement of a given binary (3M) number? b) What do you mean by K-map? Name it advantages and disadvantages. (3M) c) Distinguish between a half-adder

More information

CS61C : Machine Structures

CS61C : Machine Structures inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #17 Single Cycle CPU Datapath CPS today! 2005-10-31 There is one handout today at the front and back of the room! Lecturer PSOE, new dad

More information

EECE 321: Computer Organization

EECE 321: Computer Organization EECE 321: Computer Organization Mohammad M. Mansour Dept. of Electrical and Compute Engineering American University of Beirut Lecture 1: Introduction Administrative Instructor Dr. Mohammad M. Mansour,

More information

inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 18 CPU Design: The Single-Cycle I ! Nasty new windows vulnerability!

inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 18 CPU Design: The Single-Cycle I ! Nasty new windows vulnerability! inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 18 CPU Design: The Single-Cycle I CS61C L18 CPU Design: The Single-Cycle I (1)! 2010-07-21!!!Instructor Paul Pearce! Nasty new windows vulnerability!

More information

Arithmetic Logic Unit. Digital Computer Design

Arithmetic Logic Unit. Digital Computer Design Arithmetic Logic Unit Digital Computer Design Arithmetic Circuits Arithmetic circuits are the central building blocks of computers. Computers and digital logic perform many arithmetic functions: addition,

More information

Written exam for IE1204/5 Digital Design Thursday 29/

Written exam for IE1204/5 Digital Design Thursday 29/ Written exam for IE1204/5 Digital Design Thursday 29/10 2015 9.00-13.00 General Information Examiner: Ingo Sander. Teacher: William Sandqvist phone 08-7904487 Exam text does not have to be returned when

More information

Chapter 3 Arithmetic for Computers

Chapter 3 Arithmetic for Computers Chapter 3 Arithmetic for Computers 1 Arithmetic Where we've been: Abstractions: Instruction Set Architecture Assembly Language and Machine Language What's up ahead: Implementing the Architecture operation

More information

UC Berkeley CS61C : Machine Structures

UC Berkeley CS61C : Machine Structures inst.eecs.berkeley.edu/~cs61c UC Berkeley CS61C : Machine Structures Lecture 25 CPU Design: Designing a Single-cycle CPU Lecturer SOE Dan Garcia www.cs.berkeley.edu/~ddgarcia T-Mobile s Wi-Fi / Cell phone

More information

CS61C : Machine Structures

CS61C : Machine Structures inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #19 Designing a Single-Cycle CPU 27-7-26 Scott Beamer Instructor AI Focuses on Poker CS61C L19 CPU Design : Designing a Single-Cycle CPU

More information

CS61C Machine Structures. Lecture 12 - MIPS Procedures II & Logical Ops. 2/13/2006 John Wawrzynek. www-inst.eecs.berkeley.

CS61C Machine Structures. Lecture 12 - MIPS Procedures II & Logical Ops. 2/13/2006 John Wawrzynek. www-inst.eecs.berkeley. CS61C Machine Structures Lecture 12 - MIPS Procedures II & Logical Ops 2/13/2006 John Wawrzynek (www.cs.berkeley.edu/~johnw) www-inst.eecs.berkeley.edu/~cs61c/ CS 61C L12 MIPS Procedures II / Logical (1)

More information

ELCT 501: Digital System Design

ELCT 501: Digital System Design ELCT 501: Digital System Lecture 4: CAD tools (Continued) Dr. Mohamed Abd El Ghany, Basic VHDL Concept Via an Example Problem: write VHDL code for 1-bit adder 4-bit adder 2 1-bit adder Inputs: A (1 bit)

More information

One and a half hours. Section A is COMPULSORY UNIVERSITY OF MANCHESTER SCHOOL OF COMPUTER SCIENCE

One and a half hours. Section A is COMPULSORY UNIVERSITY OF MANCHESTER SCHOOL OF COMPUTER SCIENCE One and a half hours Section A is COMPULSORY UNIVERSITY OF MANCHESTER SCHOOL OF COMPUTER SCIENCE Fundamentals of Computer Engineering Date: Thursday 21st January 2016 Time: 14:00-15:30 Answer BOTH Questions

More information

CS 151 Final. (Last Name) (First Name)

CS 151 Final. (Last Name) (First Name) CS 151 Final Name Student ID Signature :, (Last Name) (First Name) : : Instructions: 1. Please verify that your paper contains 20 pages including this cover. 2. Write down your Student-Id on the top of

More information

Ripple Counters. Lecture 30 1

Ripple Counters. Lecture 30 1 Ripple Counters A register that goes through a prescribed sequence of states upon the application of input pulses is called a counter. The input pulses may be clock pulses, or they may originate from some

More information

The plot thickens. Some MIPS instructions you can write cannot be translated to a 32-bit number

The plot thickens. Some MIPS instructions you can write cannot be translated to a 32-bit number The plot thickens Some MIPS instructions you can write cannot be translated to a 32-bit number some reasons why 1) constants are too big 2) relative addresses are too big 3) absolute addresses are outside

More information

CS 152 Computer Architecture and Engineering Lecture 1 Single Cycle Design

CS 152 Computer Architecture and Engineering Lecture 1 Single Cycle Design CS 152 Computer Architecture and Engineering Lecture 1 Single Cycle Design 2014-1-21 John Lazzaro (not a prof - John is always OK) TA: Eric Love www-inst.eecs.berkeley.edu/~cs152/ Play: 1 Today s lecture

More information

ECE331: Hardware Organization and Design

ECE331: Hardware Organization and Design ECE331: Hardware Organization and Design Lecture 15: Midterm 1 Review Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Basics Midterm to cover Book Sections (inclusive) 1.1 1.5

More information

Binary Arithmetic Intro to Assembly Language CS 64: Computer Organization and Design Logic Lecture #3

Binary Arithmetic Intro to Assembly Language CS 64: Computer Organization and Design Logic Lecture #3 Binary Arithmetic Intro to Assembly Language CS 64: Computer Organization and Design Logic Lecture #3 Ziad Matni Dept. of Computer Science, UCSB Adding this Class The class is full I will not be adding

More information

Data paths for MIPS instructions

Data paths for MIPS instructions You are familiar with how MIPS programs step from one instruction to the next, and how branches can occur conditionally or unconditionally. We next examine the machine level representation of how MIPS

More information

ENGR 3410: MP #1 MIPS 32-bit Register File

ENGR 3410: MP #1 MIPS 32-bit Register File ENGR 3410: MP #1 MIPS 32-bit Register File Due: October 12, 2007, 5pm 1 Introduction The purpose of this machine problem is to create the first large component of our MIPS-style microprocessor the register

More information

Hardware Design Environments. Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University

Hardware Design Environments. Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University Hardware Design Environments Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University Outline Welcome to COE 405 Digital System Design Design Domains and Levels of Abstractions Synthesis

More information

EXPERIMENT NUMBER 11 REGISTERED ALU DESIGN

EXPERIMENT NUMBER 11 REGISTERED ALU DESIGN 11-1 EXPERIMENT NUMBER 11 REGISTERED ALU DESIGN Purpose Extend the design of the basic four bit adder to include other arithmetic and logic functions. References Wakerly: Section 5.1 Materials Required

More information

CS 31: Intro to Systems Digital Logic

CS 31: Intro to Systems Digital Logic CS 3: Intro to Systems Digital Logic Martin Gagné Swarthmore College January 3, 27 You re going to want scratch papr today borrow some if needed. Quick nnouncements Late Policy Reminder 3 late days total

More information

Computer Architecture Programming the Basic Computer

Computer Architecture Programming the Basic Computer 4. The Execution of the EXCHANGE Instruction The EXCHANGE routine reads the operand from the effective address and places it in DR. The contents of DR and AC are interchanged in the third microinstruction.

More information

CS222: Processor Design

CS222: Processor Design CS222: Processor Design Dr. A. Sahu Dept of Comp. Sc. & Engg. Indian Institute of Technology Guwahati Processor Design building blocks Outline A simple implementation: Single Cycle Data pathandcontrol

More information

COMP 303 Computer Architecture Lecture 6

COMP 303 Computer Architecture Lecture 6 COMP 303 Computer Architecture Lecture 6 MULTIPLY (unsigned) Paper and pencil example (unsigned): Multiplicand 1000 = 8 Multiplier x 1001 = 9 1000 0000 0000 1000 Product 01001000 = 72 n bits x n bits =

More information

Computer Systems. Binary Representation. Binary Representation. Logical Computation: Boolean Algebra

Computer Systems. Binary Representation. Binary Representation. Logical Computation: Boolean Algebra Binary Representation Computer Systems Information is represented as a sequence of binary digits: Bits What the actual bits represent depends on the context: Seminar 3 Numerical value (integer, floating

More information

ENGR 3410: Lab #1 MIPS 32-bit Register File

ENGR 3410: Lab #1 MIPS 32-bit Register File ENGR 3410: Lab #1 MIPS 32-bit Register File Due: October 12, 2005, beginning of class 1 Introduction The purpose of this lab is to create the first large component of our MIPS-style microprocessor the

More information

The plot thickens. Some MIPS instructions you can write cannot be translated to a 32-bit number

The plot thickens. Some MIPS instructions you can write cannot be translated to a 32-bit number The plot thickens Some MIPS instructions you can write cannot be translated to a 32-bit number some reasons why 1) constants are too big 2) relative addresses are too big 3) absolute addresses are outside

More information

CSC 220: Computer Organization Unit 12 CPU programming

CSC 220: Computer Organization Unit 12 CPU programming College of Computer and Information Sciences Department of Computer Science CSC 220: Computer Organization Unit 12 CPU programming 1 Instruction set architectures Last time we built a simple, but complete,

More information

CpE242 Computer Architecture and Engineering Designing a Single Cycle Datapath

CpE242 Computer Architecture and Engineering Designing a Single Cycle Datapath CpE242 Computer Architecture and Engineering Designing a Single Cycle Datapath CPE 442 single-cycle datapath.1 Outline of Today s Lecture Recap and Introduction Where are we with respect to the BIG picture?

More information

CS 61C: Great Ideas in Computer Architecture. MIPS CPU Datapath, Control Introduction

CS 61C: Great Ideas in Computer Architecture. MIPS CPU Datapath, Control Introduction CS 61C: Great Ideas in Computer Architecture MIPS CPU Datapath, Control Introduction Instructor: Alan Christopher 7/28/214 Summer 214 -- Lecture #2 1 Review of Last Lecture Critical path constrains clock

More information

Computer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: Data Paths and Microprogramming

Computer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: Data Paths and Microprogramming Computer Science 324 Computer Architecture Mount Holyoke College Fall 2007 Topic Notes: Data Paths and Microprogramming We have spent time looking at the MIPS instruction set architecture and building

More information

Chapter 4. The Processor. Instruction count Determined by ISA and compiler. We will examine two MIPS implementations

Chapter 4. The Processor. Instruction count Determined by ISA and compiler. We will examine two MIPS implementations Chapter 4 The Processor Part I Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations

More information

Digital Design with FPGAs. By Neeraj Kulkarni

Digital Design with FPGAs. By Neeraj Kulkarni Digital Design with FPGAs By Neeraj Kulkarni Some Basic Electronics Basic Elements: Gates: And, Or, Nor, Nand, Xor.. Memory elements: Flip Flops, Registers.. Techniques to design a circuit using basic

More information

CPU Organization (Design)

CPU Organization (Design) ISA Requirements CPU Organization (Design) Datapath Design: Capabilities & performance characteristics of principal Functional Units (FUs) needed by ISA instructions (e.g., Registers, ALU, Shifters, Logic

More information

KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT

KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT COE 202: Digital Logic Design Term 162 (Spring 2017) Instructor: Dr. Abdulaziz Barnawi Class time: U.T.R.: 11:00-11:50AM Class

More information

Midterm Exam Review. CS 2420 :: Fall 2016 Molly O'Neil

Midterm Exam Review. CS 2420 :: Fall 2016 Molly O'Neil Midterm Exam Review CS 2420 :: Fall 2016 Molly O'Neil Midterm Exam Thursday, October 20 In class, pencil & paper exam Closed book, closed notes, no cell phones or calculators, clean desk 20% of your final

More information

CPS311 Lecture: CPU Implementation: The Registers, ALU and Data Paths

CPS311 Lecture: CPU Implementation: The Registers, ALU and Data Paths CPS311 Lecture: CPU Implementation: The Registers, ALU and Data Paths Objectives: Last revised June 1, 2017 1. To show how a CPU is constructed out of a clock, register set/alu/datapaths and a control

More information

CprE 281: Digital Logic

CprE 281: Digital Logic CprE 281: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Intro to Verilog CprE 281: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev

More information

The Need of Datapath or Register Transfer Logic. Number 1 Number 2 Number 3 Number 4. Numbers from 1 to million. Register

The Need of Datapath or Register Transfer Logic. Number 1 Number 2 Number 3 Number 4. Numbers from 1 to million. Register The Need of Datapath or Register Transfer Logic Number 1 Number 2 Number 3 Number 4 Numbers from 1 to million Register (a) (b) Circuits to add several numbers: (a) combinational circuit to add four numbers;

More information

ECE468 Computer Organization & Architecture. The Design Process & ALU Design

ECE468 Computer Organization & Architecture. The Design Process & ALU Design ECE6 Computer Organization & Architecture The Design Process & Design The Design Process "To Design Is To Represent" Design activity yields description/representation of an object -- Traditional craftsman

More information

Control Unit: Binary Multiplier. Arturo Díaz-Pérez Departamento de Computación Laboratorio de Tecnologías de Información CINVESTAV-IPN

Control Unit: Binary Multiplier. Arturo Díaz-Pérez Departamento de Computación Laboratorio de Tecnologías de Información CINVESTAV-IPN Control Unit: Binary Multiplier Arturo Díaz-Pérez Departamento de Computación Laboratorio de Tecnologías de Información CINVESTAV-IPN Example: Binary Multiplier Two versions Hardwired control Microprogrammed

More information