Example: 2:1 Multiplexer
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1 Exmple: 2:1 Multiplexer Exmple #1 reg ; or or s) egin if (s == 1') egin = ; else egin = ; 1 s B. Bs 114
2 Exmple: 2:1 Multiplexer Exmple #2 Normlly lwys include egin nd sttements even though they re not needed when there is only one sttement in the prticulr lock. Text struck elow could e tken ut lwys dd it nywy in this clss. reg ; or or s) egin if (s == 1') egin = ; else egin = ; 1 s B. Bs 115
3 Exmple: 2:1 Multiplexer Exmple #3 Uncler nd highly discourged, ut it works reg ; or or s) egin = ; if (s == 1') egin = ; 1 s B. Bs 116
4 Exmple: 2:1 Multiplexer Exmple #4 Uncler nd highly discourged, ut it works reg ; or or s) egin = ; if (s == 1'1) egin = ; 1 s B. Bs 117
5 Exmple: 2:1 Multiplexer Exmple #5 Simpler ut less cler wy of writing if/then/else clled "inline if" or "conditionl opertor" which is lso found in some computer lnguges reg ; or or s) egin = s? : ; 1 s B. Bs 118
6 Exmple: 2:1 Multiplexer Exmple #6 The inline conditionl opertor cn lso e used to define wires wire ; ssign = s? : ; 1 s B. Bs 119
7 Exmple: 4:1 Multiplexer Exmple: 4:1 multiplexer reg ; // must e reg to e set in n lwys lock! or or c or d or s1 or s) egin cse ({s1,s}) // conctente two select signls 2 : egin = ; 2 1: egin = ; 2 1: egin = c; 2 11: egin c = d; d defult: egin // does nothing = 1 x; cse // of lwys lock s1,s B. Bs 12
8 Exmple: 4:1 Mux with zero on Exmple #1 two inputs reg ; // must e reg to e set in n lwys lock! or d or s1 or s) egin cse ({s1,s}) 2 : egin = c; 2 1: egin = 1 ; 2 1: egin = 1 ; 2 11: egin = d; defult: egin = 1 ; // zero cse // of lwys lock d s1,s B. Bs 121 c
9 Exmple: 4:1 Mux with zero on two inputs Exmple #2 Here the cse s defult section is used reg ; // must e reg to e set in n lwys lock! or d or s1 or s) egin cse ({s1,s}) 2 : egin = c; 2 11: egin = d; defult: egin = 1 ; cse // of lwys lock c d s1,s B. Bs 122
10 Exmple: 4:1 Mux with zero on two inputs Exmple #3 Here is set to defult vlue efore the cse lock reg ; // must e reg to e set in n lwys lock! or d or s1 or s) egin = 1 ; // set to defult vlue cse ({s1,s}) 2 : egin = c; 2 11: egin = d; cse // of lwys lock c d s1,s B. Bs 123
11 Exmple: 4:1 Mux with zero on two inputs Exmple #4 Here if sttements re used. Clerly there re mny solutions. reg ; // must e reg to e set in n lwys lock! or d or s1 or s) egin = 1 ; // set defult if ({s1,s} == 2 ) egin = c; if (s1==1 1 && s==1 1) egin = d; // of lwys lock c d s1,s B. Bs 124
12 Mistke #1: Inferring Stte In Comintionl Circuits By: An Incomplete Sensitivity List egin // missing = & ; updtes when chnges s expected does not updte when chnges! Put nother wy, cn chnge ll it wnts ut will not updte this requires memory element to rememer the lst vlue of Synthesis tools nd lint checkers will give wrning Using the construct: or elimintes this type of ug, ut it is not supported y ll modern CAD tools edge detector G B. Bs 125
13 Mistke #2: Inferring Stte In Comintionl Circuits By: Not Setting reg In All Pths Exmple comintionl circuit with put freq_c If xyz==4 1, freq_c is function of the inputs If freq==3 or 3 1, freq_c is function of the inputs Otherwise, freq_c keeps its old vlue which implies memory is needed! Which mens our comintionl circuit is roken. // this "lwys" lock does not instntite comintionl logic or xyz or c) egin if (xyz==4 1) egin freq_c = c; logic cse (freq) egin 3 : freq_c = c; 3 1: freq_c = c + 3 1; cse freq c xyz freq_c B. Bs 126
14 Mistke #2: Inferring Stte In Comintionl Circuits By: Not Setting reg In All Pths Exmple comintionl circuit with put c_freq Solution: freq_c is set regrdless of the vlues of ll inputs One solution: lwys declre defult vlues t eginning of lwys locks If helpful, declre defult cse in cse sttements // this "lwys" lock instntites comintionl logic or xyz or c) egin // defult section of lwys lock freq_c = freq; // some defult vlue // min logic lock if (xyz==4 1) egin freq_c = c; else egin // perhps not lwys pplicle freq_c =...; freq c xyz logic freq_c cse (freq) egin 3 : freq_c = c; 3 1: freq_c = c+3 1; defult: freq_c =...; // perhps you know freq should never e nything cse // other thn or 1, or perhps you do wnt // freq_c equl to something in these six cses B. Bs 127
15 Avoid Inferring Stte For Comintionl Circuits 1. Include ll input vriles in the sensitivity list! 2. Set the vlue of ll regs in ll pths through every lwys lock A nice solution is to set defult vlues for ll put vriles immeditely fter entering n lwys lock o You will eliminte the chnce of this ug if you do B. Bs 128
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