April 2002, Version 1.1. Component. PTF File. Component. Component GUI Wizards. Generation. System PTF file Files and Libraries.

Size: px
Start display at page:

Download "April 2002, Version 1.1. Component. PTF File. Component. Component GUI Wizards. Generation. System PTF file Files and Libraries."

Transcription

1 SOPC Builder April 2002, Version 1.1 Data Sheet Introduction SOPC Builder is a tool for composing bus-based systems out of library components such as CPUs, memory interfaces, and peripherals. SOPC Builder can either import directly, or provide an interface to, user-defined blocks of logic. SOPC Builder creates (generates) a single system module that instantiates a list of user-specified components and interfaces. The system module contains automatically-generated bus (interconnection) logic. Figure 1. SOPC Builder Component Library Component PTF File SOPC Generation SOPC Builder GUI Component GUI Wizards Component Generation System Generator Programs System PTF file Files and Libraries HDL Files Software Files Simulation Files... other user defined files Altera Corporation 1 DS-NIOSSOPC-1.1

2 SOPC Builder automatically generates Avalon bus logic between Avalon master and slave ports on all system components. SOPC Builder is most often used to construct embedded microprocessor systems that include CPUs, memories, and I/O peripherals. SOPC Builder can, however, generate useful dataflow systems with no CPU at all. SOPC Builder allows you to specify bus topologies with multiple masters and slaves. Bus logic, including arbitrators, are automatically generated during system construction. SOPC Builder library components can be very simple blocks of fixed logic, or they can be complex, parameterized, dynamically-generated subsystems. Many Altera SOPC Builder library components include (for example) Wizard-based graphical interfaces for configuration, and HDL generator programs that can deliver the component as either synthesizable Verilog or VHDL. SOPC Builder simplifies system-level synthesis and simulation. SOPC Builder includes an integrated synthesis tool (SOPC Builder) incorporates LeonardoSpectrum v2002a_49_oem_altera, and runs synthesis automatically as part of the system-generation process. Starting SOPC Builder Follow these steps to create a new SOPC Builder system: 1. Start the Quartus II software by performing one of the following: v Choose Programs > Altera > Quartus II <version> (Windows Start menu). or v Type quartus r at the command prompt. 2. Choose MegaWizard Plug-In Manager (Tools menu). 3. Select Create a New Megafunction Variation and click Next. 4. Select Altera SOPC Builder version 2.5 from the list of available megafunctions. 5. Choose your preferred HDL Output File (VHDL or Verilog). 6. Enter a name for your system-module, and click Next. 1 A convenient method for re-running SOPC Builder to edit an existing system module is to double-click the system module s symbol in the Quartus schematic editor. f See the Nios Tutorial for a detailed discussion of the SOPC Builder GUI. 2 Altera Corporation

3 The SOPC Builder Tool SOPC Builder consists of two substantially separate pieces: 1. A graphical user interface (GUI) for listing and arranging system components. Within the GUI, each component may also, itself, provide a graphical user interface for its own configuration. The GUI creates a description of the system called the system [peripheral template file (PTF)] file. 2. A generator-program that converts the system description (PTF file) into its hardware implementation. The generator program (among other tasks) creates an HDL description of the system and then synthesizes it for the selected target device. The SOPC Builder GUI SOPC Builder provides a GUI for specifying what components the system will contain and how the components are arranged and generated. The GUI itself does not generate any logic, create any software, or perform any other system-generation task. The GUI is just a front-end or editor for the system-description file (system PTF file). 1 You can edit the system PTF file directly in any text editor. Be sure, however, that the SOPC Builder GUI is closed as the SOPC- GUI is functionally a PTF-editor, and having the same file open simultaneously in two editors may produce unpredictable results. The SOPC Builder s graphical user interface consists of several pages (tabs): System Contents Arbitration Priorities An additional page for every CPU component in the system A final System Generation page The System Contents Page The system contents page consists of two major sections: A pool of all available library components (the Module Pool, on the left) and a list of all modules included in the current system (the Module Table, on the right). The module table allows you to describe: Which components and interfaces are included in the system Which masters are connected to which slaves The system address map The system IRQ assignments Arbitration priorities for shared slaves Altera Corporation 3

4 The left-hand side of the Module Table displays interconnections between masters and slaves. Any module in the system can have one or more master or slave ports. Any master can be connected to any slave if both master and slave use the same bus protocol. Notice that Avalon and Avalon_tristate are different bus-protocols, and therefore a bridgecomponent is required to interface an avalon master to an avalon_tristate slave. Every master in the system has a corresponding column on the left side of the Module Table. Using the View menu, you can change the appearance of the master columns. You can hide the master columns entirely, display them as a patch-panel (interconnection-priority only), or display the numeric arbitration priorities. Arbitration Priorities Whenever two masters share (have access to) the same slave, SOPC Builder automatically inserts an arbiter to control access to the slave. The arbiter determines which master is granted access to the slave when simultaneous requests occur. There will be one arbiter inserted for each shared slave. A slave will have an integer arbitration priority for each of its masters. Conflicts are resolved according to the following rule: If each master has a priority P i, and the sum of all the priorities is P total, then master number i will win arbitration P i times out of every P total conflicts. v To view arbitration priorities, choose Show Arbitration Priorities (View menu). CPU Pages Each CPU in your system will have an associated tab This tab allows you to specify interrelationships (bindings) between a CPU and other modules in your system. For example, every CPU will treat some other system module as its main memory. SOPC Builder will display an additional CPU tab for every component that has a Bind_Program assignment in its class.ptf (library definition) file. This assignment is typically only set for CPUs, but it may be set for any other type of component as well. f See the CPU Data Sheet for more information. The Generator Program Page The SOPC Builder generator program can be run directly from the command-line, or by pressing Generate in the GUI. 4 Altera Corporation

5 The Generator program performs the following tasks: Reads the system description (system PTF file). Creates software files (drivers, libraries, and utilities) for any systemcomponents that provide software support in their library definition. Runs every component s individual generator program. Each component in the system may have its own generator program (which may, for example, create an HDL description of the component). The main SOPC Builder generator program runs the sub-generator program associated with every component that has one. Generates the system-level HDL file (in either VHDL or Verilog) This generation file contains: An instance of every component in the system Bus logic for implementing module interconnect, including: - Address decoders - Data bus multiplexers - Arbiters for shared resources - Reset-generation and conditioning logic - Interrupt prioritization logic - Dynamic bus sizing (for adapting masters to slaves with wider or narrower data busses) - All passive interconnections between master and slave ports A simulation test-bench that: - Instantiates the system module - Drives clock and reset inputs with default behaviors - Instantiates and connects any simulation models for systemexternal components (e.g. memory models) - Creates a symbol (.bsf-file) for the system module - Creates a ModelSim simulation project directory that includes: - Simulation data-files for all memory components that specify contents - A setup_sim.do file that contains useful setup and aliases customized for simulating the generated system - A wave_presets.do file that contains a useful initial set of bus-interface waveforms - A ModelSim project (.mpf file) for the current system Synthesizes the entire system module and all its contents using LeonardoSpectrum. The result is an EDF-file ready for place-androute or inclusion as a module in a larger design. Writes a command-line system-generation script so the system can be conveniently re-generated in the future without using the GUI. Altera Corporation 5

6 Running the Generator Program from the Command Line The SOPC Builder generator program is an executable which can be run from your system s command line. You provide the name of the current system (ptf filename), the system directory, and other parameters as command-line arguments. Every time you generate a system, SOPC Builder creates a script that runs the generator program with the correct arguments needed to generate your system named <your_system_name>_generation_script. Running this script has the same effect as pressing Generate in the SOPC Builder GUI. The SOPC Builder Library When building a system, you can add modules from one of two sources: 1. Predefined modules that are installed in the SOPC Builder library. 2. User-defined modules. You may incorporate blocks of user-defined logic directly into your SOPC Builder system, or you may request an interface customized to fit your block of system-external logic. See Interfacing User-Designed Logic to SOPC Builder on page 7. SOPC Builder is delivered with a set of built-in library components (modules), including a UART, a timer, a PIO, an Avalon Tri-state bridge, and several simple memory interfaces. You can obtain additional SOPC Builder components from Altera or third-party IP developers. When you install new SOPC Builder library components, they will be automatically discovered by SOPC Builder and appear in the Module Pool the next time you run the GUI. f Check Altera s web site for up-to-date information about available SOPC Builder library components. Library Search Path SOPC Builder finds all library components installed on your system by scanning for component directories in a search-path. The order of the search is as follows: The components directory within the SOPC Builder installation The current project directory One or more user-specified directories (File > Setup menu) Components found latest in the search have priority over those found earliest. This allows project- and user-specified components to override any built-in components. 6 Altera Corporation

7 Library class.ptf Files All valid library components are recognized by the presence of a single file in their directory named class.ptf. A component s class.ptf file declares and defines all the information about that component so it can appear in, and be used by, SOPC Builder. A class.ptf file will, for example, contain the formal name of a component, a description of its master- and slave-ports, and a default configuration for all new instances of that component. It may also contain a complete declaration of all I/O ports on that component, and it may even contain a complete description of a GUI for configuring the component. f IP developers can check for up-to-date documents that detail all of the recognized sections and assignments in class.ptf files. In addition to the class.ptf file, a components library directory may also contain the logic that implements the component (for example, a VHDL, Verilog, or encrypted netlist file), software libraries and drivers that support the component, documentation, and any other componentspecific information provided by the vendor. Many Altera library components contain a generator program that emit synthesizable Verilog or VHDL. Interfacing User-Designed Logic to SOPC Builder Most practical SOPC Builder systems include both modules taken from the library and some custom (user-designed) logic. There are three broad mechanisms for using an SOPC Builder system module with userdesigned logic: 1. Simple PIO Connection Include one or more PIO devices in the SOPC Builder system. The PIO s input- and output-pins will appear as I/O ports at the top level (i.e. as pins on the aggregate system module). If you connect these pins to other logic, the system-module software can directly control (or read) the logic level on each pin. 2. Instantiation Inside the System Module SOPC Builder can incorporate a block of user-logic by instantiating it directly within the system module. SOPC Builder will create bus-logic and connect it to all designated bus-ports on the user-designed block. All I/O pins not designated as bus-connections will be promoted to the top level, and appear as I/O pins on the system module. The userdesigned block can be instantiated either as a black-box, or as HDL which is synthesized along with the rest of the system during the generation phase. Altera Corporation 7

8 3. Bus Interface to External Logic SOPC Builder can add a set of bus-interface pins customized to fit an external logic block. The bus interface includes address, data, and control signals (including decoded device-select) suitable for direct connection to a businterface on the device. Instantiating a User-Logic Block Inside the System Module The easiest way to include a pre-existing block of user-logic in an SOPC Builder system is to incorporate it directly into the system module. SOPC Builder provides a GUI that allows you to specify the design-files (VHDL, Verilog, schematic (BDF), or netlist (EDF) files) that implement the block. SOPC Builder scans the design files and find all of the block s top-level I/O pins. The GUI provides a simple method for designating which pins are bus-connection ports, and which pins are promoted to I/O pins at the system-module s top level. When you instantiate a block of user-logic inside the system module, SOPC Builder automatically generates all HDL necessary to instantiate, connect, and control your block. To instantiate a block of user-defined logic in an SOPC Builder system module: 1. In the System Contents page, choose Add Interface to User Logic (System menu). The Interface to User Logic window appears. 2. Select the Read IO ports from design files radio button. 3. Check the Instantiate in system module box. 4. Click Import HDL... The Design Import Wizard window appears. 5. In the Design Information pane, click Add... to select each design file (.v,.vhd,.edf, or.bdf) that implements your logic. 6. Enter the name of the top entity (module) in the Top module name field if the default name (the first design file s base name) is incorrect. 7. Click Scan Files to read all the top-level I/O port information from the listed design files. 8. To have your logic synthesized along with the rest of the system module during the SOPC Builder s generation process, leave the Black box this design box unchecked. Check Black box this design if you wish to synthesize the design using your own tools (and subsequently provide a netlist for place-and-route). The box is automatically checked if the design files already contain a synthesized netlist or your design is a schematic file. 8 Altera Corporation

9 1 In order for SOPC Builder to synthesize your logic, you must have a valid LeonardoSpectrum license for synthesizing the design. For example, you must have a license that allows VHDL synthesis if you wish to synthesize VHDL designs. 9. A list of all I/O ports on the specified top-level module appears. The HDL-scanner may erroneously identify and/or miss ports for designs that have parameterized or conditionally-compiled ports (for example, port declarations within ifdef blocks in Verilog). Choose Add Port and Delete Port to edit the port list, if needed. 10. Click in each port s Type field to select its width and direction from a list of valid Avalon port types. 1 The Avalon Bus Specification Reference Manual describes all ports except export. The export type tells SOPC Builder a port is not a bus-interface signal and should be promoted to an I/O pin at the system module s top level. Choose the export type for any ports you do not want automatically connected to the Avalon bus. 11. Once you have assigned a type to every port, click Finish. 12. Click the Timing tab in the Interface to User Logic window to specify the setup, hold, and wait-state requirements for your logic s bus interface. 13. Click Finish. Your module appears in the Module table and a corresponding MODULE section is added to the system s PTF file. f See the Avalon Bus Specification Reference Manual for detailed port types and bus-interface signals. Creating a Bus Interface to External Logic Instead of instantiating a block of logic within the SOPC Builder system module, you may instead request a customized bus-interface port on the system module. You can then instantiate both the system module and your logic block in a wrapper design, and connect the system module s bus-port pins to your block. To add a customized bus-interface port to the system module, click Import underneath the Module Pool on the System Contents page. Make sure the check-box labeled Instantiate in system module is un-checked. For system-external modules, you can describe the bus-interface on your logic using one of two methods: Altera Corporation 9

10 1. The list of bus-interface ports can be read directly from your design file (choose Read IO ports from design file(s)). 2. You can describe the bus-interface directly using the Interface to User Logic GUI (choose Describe Bus Interface Ports). Method (2) provides only limited choices for Avalon bus interface signals. If your block of logic uses more than simple data, address, read, write, and select signals, you may get a more highly customized bus-interface port by using Method (1). To read a list of bus-interface ports directly from your design files, follow the instructions for Instantiating a User-Logic Block Inside the System Module on page 8, except do not check the Instantiate in system module check-box. All I/O ports on your module assigned export type will be ignored. The system module will sprout interface signals suitable for direct connection to all bus-interface (non-export type) signals on your design. Bus Interface Address Alignment Rules When you create a bus-interface to a block of logic, one of the ports on the system module will be an address-bus. The system module will have an address-output port for each external-module interface (except when address ports are shared). For most interfaces, the system module s address-output port will be the same width as the module s address-input port, and there is no ambiguity about how the two should be connected. Sometimes, the address-output port on the system module will be wider than the address-input port on the external module. This typically happens for modules connected to a tri-state data bus. SOPC Builder uses the following rules to determine the width of any outgoing address port: For external modules that do not use a tri-state data bus, (i.e. modules with separate, unidirectional readdata and/or writedata ports) the system module s address-output port will be exactly the same width as the module s input-port. For external modules that do use a tri-state data bus, the system module s address-output port will always carry a byte-address. For example, if you create an interface for an external 32-bit-wide memory chip with 14 address pins (64Kbytes of memory), the corresponding address-output pin on the system module will be 16 bits wide (16 bits are required to address every byte in a 64Kbyte memory). For correct system operation, you must connect pins A[15..2] to the 14 address pins on your 32-bit memory (address bits 1 and 0 are left unconnected in this example). 10 Altera Corporation

11 Connecting to Memory Devices The Interface to User Logic GUI includes a check-box option for connecting to memory devices. If your logic is an interface to a memory device, select this option. Checking the Is this peripheral a memory device? option has two effects: 1. The Avalon bus will implement Dynamic Bus Sizing when connecting this peripheral to any master with a different data bus width. 2. This module will now appear on the available list of available memory devices in (for example) the CPU s Program Memory dropdown setting. f The PTF File See the Avalon Bus Specification Reference Manual for more information about Dynamic Bus Sizing. The system PTF file contains all design-specific data needed to generate an SOPC system out of basic library components. When you create a new system module named, for example, my_system_module, SOPC Builder will create the file my_system_module.ptf in your current Quartus project directory. All settings, choices, and parameters entered through the GUI are recorded in the system PTF file. The primary input to the SOPC Builder generator program is the PTF file. In principle, you should be able to recreate your system module given only its system PTF file (and all the necessary components in the library). System PTF Construction When you first create a system, SOPC Builder makes a new PTF file with only a handful of global system-wide settings (like the system input clock frequency and the target device for synthesis). Every time you add a module to your system, it shows up in the Module Table, and a corresponding MODULE section is added to the system PTF file. The contents of the MODULE section is initially taken from that module s definition in the library. A section of that module s class.ptf file is copied wholesale into the new MODULE section in the system s PTF file. Some library components allow the newly-added module to be parameterized, and may provide their own GUI for configuration. Any changes made by a module s GUI will be recorded in that module s MODULE section in the system PTF file. Altera Corporation 11

12 When the SOPC Builder s generate program is run (for example, by pressing the Generate button in the GUI), each module in the system is checked to see if it has a corresponding Generator_Program (typically in its library directory). If so, SOPC Builder runs it. A module s generator program may modify or add to the contents of a module s MODULE section in the system PTF file. Many library components have generator programs that, for example, create I/O port declarations in the corresponding MODULE sections in the system PTF file. After every module s Generator_Program (if any) has been run, the PTF file contents are considered complete, and bus-generation can begin. In summary, information is added to a system s PTF file by four separate processes: 1. When a system is first created, a small amount of system-global information is added. 2. For each new module added to the system, a new MODULE section is added to the PTF file and initialized with contents taken from that module s library definition. 3. Every time a module is configured (typically through its GUI), settings are modified or added to its MODULE section in the system PTF file. 4. During the generation-phase, every module may run a Generator_Program that can add or modify information in that module s MODULE section. The MODULE section associated with any given module in the system may or may not have information from any of these sources, depending on how the module is implemented in the library. 1 In a module s class.ptf file, the MODULE_DEFAULTS section is copied directly into a system s PTF file every time a new module of that type is added. PTF Syntax PTF files are semi-human-readable, human-editable ASCII-text databases of information about SOPC Builder library components and systems. 12 Altera Corporation

13 PTF Elements A PTF file contains two distinct types of syntactic elements ASSIGNMENTS and SECTIONS. It is best to show examples of each: Example Assignments: data_from_cpu = 16 ; Address_Alignment = --unknown-- ; Has_IRQ= 1 ; Example Sections: HDL_INFO { Simulation_HDL_Files = --unknown-- ; Synthesis_HDL_Files = --unknown-- ; } USER_INTERFACE { USER_LABELS { name= UART (RS-232 serial port) ; } } PTF Assignments Assignments are name-equals-value pairs, and they have this syntax: <assignment-name> = <assignment-value> ; Assignment names may be of arbitrary length, and may contain any alphanumeric character (upper and lower case), as well as underscore ( _ ). Assignment names may not contain spaces or any other punctuation characters. Assignment values are always enclosed by paired double-quotation marks. Assignment values may contain -any- ASCII character -except- quotation marks. If a double-quotation mark appears within an assignment value, it must be preceded by a backslash (\) character. All assignments end in a semicolon. White space (including new lines) are ignored in PTF files (except in quoted assignment-values, of course). PTF Sections Sections are groupings of other PTF-elements, and they have this syntax: <section-type> <section-name> { <section-body> } Altera Corporation 13

14 Section-type and section-name fields each obey the same restrictions as assignment names, above (alphanumeric only, no spaces or punctuation, etc.). Every section must have a curly-brace pair {} enclosing a sectionbody. The section-body can be null (contain no characters). In general, a section body can contain an arbitrary number of assignments, and an arbitrary number of sections. Because sections can contain sections, PTF files are hierarchical in nature. Indentation is often used to make their contents more human-readable (but, being white space, indentation is formally ignored). When documents refer to a particular sub-section in a PTF file, it is conventional to use a / (forward-slash) hierarchy separator (even though such a reference is neither recognized nor required by PTF syntax). So, when a document refers to, for example, a MODULE section named my_module within the SYSTEM section, it would use this notation: SYSTEM/Module my_module/... Recognized PTF Sections and Assignments SOPC Builder recognizes many sections and assignments in system PTF files and in library class.ptf files. For a complete list of all recognized PTF sections and assignments, please visit Altera s web site at Innovation Drive San Jose, CA (408) Applications Hotline: (800) 800-EPLD Literature Services: lit_req@altera.com Copyright 2002 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, mask work rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. 14 Altera Corporation

Simultaneous Multi-Mastering with the Avalon Bus

Simultaneous Multi-Mastering with the Avalon Bus Simultaneous Multi-Mastering with the Avalon Bus April 2002, ver. 1.1 Application Note 184 Introduction The Excalibur Development Kit, featuring the Nios embedded processor version 2.1 supports an enhanced

More information

Practical Hardware Debugging: Quick Notes On How to Simulate Altera s Nios II Multiprocessor Systems Using Mentor Graphics ModelSim

Practical Hardware Debugging: Quick Notes On How to Simulate Altera s Nios II Multiprocessor Systems Using Mentor Graphics ModelSim Practical Hardware Debugging: Quick Notes On How to Simulate Altera s Nios II Multiprocessor Systems Using Mentor Graphics ModelSim Ray Duran Staff Design Specialist FAE, Altera Corporation 408-544-7937

More information

Simulating Nios II Embedded Processor Designs

Simulating Nios II Embedded Processor Designs Simulating Nios II Embedded Processor Designs May 2004, ver.1.0 Application Note 351 Introduction The increasing pressure to deliver robust products to market in a timely manner has amplified the importance

More information

Nios DMA. General Description. Functional Description

Nios DMA. General Description. Functional Description Nios DMA January 2003, Version 1.1 Data Sheet General Functional The Nios DMA module is an Altera SOPC Builder library component included in the Nios development kit. The DMA module allows for efficient

More information

DDR and DDR2 SDRAM Controller Compiler User Guide

DDR and DDR2 SDRAM Controller Compiler User Guide DDR and DDR2 SDRAM Controller Compiler User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com Operations Part Number Compiler Version: 8.1 Document Date: November 2008 Copyright 2008 Altera

More information

Legacy SDRAM Controller with Avalon Interface

Legacy SDRAM Controller with Avalon Interface Legacy SDRAM Controller with Avalon Interface January 2003, Version 1.0 Data Sheet Introduction PTF Assignments SDRAM is commonly used in cost-sensitive applications requiring large amounts of memory.

More information

Nios II Embedded Design Suite 7.1 Release Notes

Nios II Embedded Design Suite 7.1 Release Notes Nios II Embedded Design Suite 7.1 Release Notes May 2007, Version 7.1 Release Notes This document contains release notes for the Nios II Embedded Design Suite (EDS) version 7.1. Table of Contents: New

More information

Active Serial Memory Interface

Active Serial Memory Interface Active Serial Memory Interface October 2002, Version 1.0 Data Sheet Introduction Altera Cyclone TM devices can be configured in active serial configuration mode. This mode reads a configuration bitstream

More information

Introduction. Design Hierarchy. FPGA Compiler II BLIS & the Quartus II LogicLock Design Flow

Introduction. Design Hierarchy. FPGA Compiler II BLIS & the Quartus II LogicLock Design Flow FPGA Compiler II BLIS & the Quartus II LogicLock Design Flow February 2002, ver. 2.0 Application Note 171 Introduction To maximize the benefits of the LogicLock TM block-based design methodology in the

More information

DSP Builder. DSP Builder v6.1 Issues. Error When Directory Pathname is a Network UNC Path

DSP Builder. DSP Builder v6.1 Issues. Error When Directory Pathname is a Network UNC Path March 2007, Version 6.1 Errata Sheet This document addresses known errata and documentation changes for DSP Builder version 6.1. Errata are functional defects or errors which may cause DSP Builder to deviate

More information

DDR & DDR2 SDRAM Controller Compiler

DDR & DDR2 SDRAM Controller Compiler DDR & DDR2 SDRAM Controller Compiler march 2007, Compiler Version 7.0 Errata Sheet This document addresses known errata and documentation issues for the DDR and DDR2 SDRAM Controller Compiler version 7.0.

More information

White Paper AHB to Avalon & Avalon to AHB Bridges

White Paper AHB to Avalon & Avalon to AHB Bridges White Paper AHB to & to AHB s Introduction For years, system designers have been manually connecting IP peripheral functions to embedded processors, taking anywhere from weeks to months to accomplish.

More information

Nios Soft Core Embedded Processor

Nios Soft Core Embedded Processor Nios Soft Core Embedded Processor June 2000, ver. 1 Data Sheet Features... Preliminary Information Part of Altera s Excalibur TM embedded processor solutions, the Nios TM soft core embedded processor is

More information

DDR & DDR2 SDRAM Controller Compiler

DDR & DDR2 SDRAM Controller Compiler DDR & DDR2 SDRAM Controller Compiler May 2006, Compiler Version 3.3.1 Errata Sheet This document addresses known errata and documentation issues for the DDR and DDR2 SDRAM Controller Compiler version 3.3.1.

More information

Estimating Nios Resource Usage & Performance

Estimating Nios Resource Usage & Performance Estimating Nios Resource Usage & Performance in Altera Devices September 2001, ver. 1.0 Application Note 178 Introduction The Excalibur Development Kit, featuring the Nios embedded processor, includes

More information

Error Correction Code (ALTECC_ENCODER and ALTECC_DECODER) Megafunctions User Guide

Error Correction Code (ALTECC_ENCODER and ALTECC_DECODER) Megafunctions User Guide Error Correction Code (ALTECC_ENCODER and ALTECC_DECODER) Megafunctions User Guide 11 Innovation Drive San Jose, CA 95134 www.altera.com Software Version 8. Document Version: 2. Document Date: June 28

More information

DDR & DDR2 SDRAM Controller Compiler

DDR & DDR2 SDRAM Controller Compiler DDR & DDR2 SDRAM Controller Compiler August 2007, Compiler Version 7.1 Errata Sheet This document addresses known errata and documentation issues for the DDR and DDR2 SDRAM Controller Compiler version

More information

Introduction to the Altera SOPC Builder Using Verilog Design

Introduction to the Altera SOPC Builder Using Verilog Design Introduction to the Altera SOPC Builder Using Verilog Design This tutorial presents an introduction to Altera s SOPC Builder software, which is used to implement a system that uses the Nios II processor

More information

Simulating the PCI MegaCore Function Behavioral Models

Simulating the PCI MegaCore Function Behavioral Models Simulating the PCI MegaCore Function Behavioral Models August 2001, ver. 1.0 Application Note 169 Introduction Altera intellectual property (IP) MegaCore functions are developed and pre-tested by Altera,

More information

Nios PIO. General Description. Functional Description

Nios PIO. General Description. Functional Description Nios PIO January 2003, Version 3.1 Data Sheet General Description Functional Description The Nios parallel input/output (PIO) module is an Altera SOPC Builder library component included in the Nios development

More information

Using Verplex Conformal LEC for Formal Verification of Design Functionality

Using Verplex Conformal LEC for Formal Verification of Design Functionality Using Verplex Conformal LEC for Formal Verification of Design Functionality January 2003, ver. 1.0 Application Note 296 Introduction The Altera Quartus II software, version 2.2, easily interfaces with

More information

Toolflow for ARM-Based Embedded Processor PLDs

Toolflow for ARM-Based Embedded Processor PLDs Toolflow for ARM-Based Embedded Processor PLDs December 2000, ver. 1 Application Note Introduction The Excalibur embedded processor devices achieve a new level of system integration from the inclusion

More information

Using the Serial FlashLoader With the Quartus II Software

Using the Serial FlashLoader With the Quartus II Software Using the Serial FlashLoader With the Quartus II Software July 2006, ver. 3.0 Application Note 370 Introduction Using the Joint Test Action Group () interface, the Altera Serial FlashLoader (SFL) is the

More information

DSP Builder Release Notes

DSP Builder Release Notes April 2006, Version 6.0 SP1 Release Notes These release notes for DSP Builder version 6.0 SP1 contain the following information: System Requirements New Features & Enhancements Errata Fixed in This Release

More information

Simulating the PCI MegaCore Function Behavioral Models

Simulating the PCI MegaCore Function Behavioral Models Simulating the PCI MegaCore Function Behavioral Models February 2003, ver. 1.2 Application Note 169 Introduction Altera intellectual property (IP) MegaCore functions are developed and pre-tested by Altera,

More information

Introduction to the Altera SOPC Builder Using Verilog Designs. 1 Introduction

Introduction to the Altera SOPC Builder Using Verilog Designs. 1 Introduction Introduction to the Altera SOPC Builder Using Verilog Designs 1 Introduction This tutorial presents an introduction to Altera s SOPC Builder software, which is used to implement a system that uses the

More information

Cyclone II FPGA Family

Cyclone II FPGA Family ES-030405-1.3 Errata Sheet Introduction This errata sheet provides updated information on Cyclone II devices. This document addresses known device issues and includes methods to work around the issues.

More information

Nios II Embedded Design Suite 6.1 Release Notes

Nios II Embedded Design Suite 6.1 Release Notes December 2006, Version 6.1 Release Notes This document lists the release notes for the Nios II Embedded Design Suite (EDS) version 6.1. Table of Contents: New Features & Enhancements...2 Device & Host

More information

RLDRAM II Controller MegaCore Function

RLDRAM II Controller MegaCore Function RLDRAM II Controller MegaCore Function November 2006, MegaCore Version 1.0.0 Errata Sheet This document addresses known errata and documentation issues for the RLDRAM II Controller MegaCore function version

More information

Excalibur Solutions Using the Expansion Bus Interface. Introduction. EBI Characteristics

Excalibur Solutions Using the Expansion Bus Interface. Introduction. EBI Characteristics Excalibur Solutions Using the Expansion Bus Interface October 2002, ver. 1.0 Application Note 143 Introduction In the Excalibur family of devices, an ARM922T processor, memory and peripherals are embedded

More information

altshift_taps Megafunction User Guide

altshift_taps Megafunction User Guide altshift_taps Megafunction User Guide 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 www.altera.com Document Version: 1.0 Document Date: September 2004 Copyright 2004 Altera Corporation. All rights

More information

Simple Excalibur System

Simple Excalibur System Excalibur Solutions Simple Excalibur System August 2002, ver. 1.0 Application Note 242 Introduction This application note describes a simple Excalibur system design that consists of software running on

More information

2. System Interconnect Fabric for Memory-Mapped Interfaces

2. System Interconnect Fabric for Memory-Mapped Interfaces 2. System Interconnect Fabric for Memory-Mapped Interfaces QII54003-8.1.0 Introduction The system interconnect fabric for memory-mapped interfaces is a high-bandwidth interconnect structure for connecting

More information

Excalibur Solutions DPRAM Reference Design

Excalibur Solutions DPRAM Reference Design Excalibur Solutions DPRAM Reference Design August 22, ver. 2.3 Application Note 173 Introduction The Excalibur devices are excellent system development platforms, offering flexibility, performance, and

More information

Making Qsys Components. 1 Introduction. For Quartus II 13.0

Making Qsys Components. 1 Introduction. For Quartus II 13.0 Making Qsys Components For Quartus II 13.0 1 Introduction The Altera Qsys tool allows a digital system to be designed by interconnecting selected Qsys components, such as processors, memory controllers,

More information

Simulating the Reed-Solomon Model

Simulating the Reed-Solomon Model July 2000, ver. 1 Simulating the Reed-Solomon Model with the Visual IP Software User Guide Introduction Altera intellectual property (IP) MegaCore functions are developed and pre-tested by Altera, and

More information

Nios Timer. General Description. Functional Description

Nios Timer. General Description. Functional Description Nios Timer July 2003, Version 3.2 Data Sheet General Description Functional Description The Nios Timer module is an Altera SOPC Builder library component included in the Nios development kit. This SOPC

More information

Debugging Nios II Systems with the SignalTap II Logic Analyzer

Debugging Nios II Systems with the SignalTap II Logic Analyzer Debugging Nios II Systems with the SignalTap II Logic Analyzer May 2007, ver. 1.0 Application Note 446 Introduction As FPGA system designs become more sophisticated and system focused, with increasing

More information

Table 1 shows the issues that affect the FIR Compiler, v6.1. Table 1. FIR Compiler, v6.1 Issues.

Table 1 shows the issues that affect the FIR Compiler, v6.1. Table 1. FIR Compiler, v6.1 Issues. December 2006, Version 6.1 Errata Sheet This document addresses known errata and documentation issues for the Altera FIR Compiler, v6.1. Errata are functional defects or errors, which may cause an Altera

More information

Digital Systems Design

Digital Systems Design Digital Systems Design Custom Components for NIOS II Systems Dr. D. J. Jackson Lecture 15-1 Qsys Components A Qsys component includes the following elements: Information about the component type, such

More information

ZBT SRAM Controller Reference Design

ZBT SRAM Controller Reference Design ZBT SRAM Controller Reference Design for APEX II Devices December 2001, ver. 1.0 Application Note 183 Introduction As communication systems require more low-latency, high-bandwidth interfaces for peripheral

More information

Nios Embedded Processor UART Peripheral

Nios Embedded Processor UART Peripheral Nios Embedded Processor UART Peripheral March 2001, ver. 1.1 Data Sheet General Description The Nios universal asynchronous receiver/transmitter UART implements simple RS-232 asynchronous transmit and

More information

Matrices in MAX II & MAX 3000A Devices

Matrices in MAX II & MAX 3000A Devices Crosspoint Switch Matrices in MAX II & MAX 3000A Devices March 200, ver. 2.0 Application Note 29 Introduction With a high level of flexibility, performance, and programmability, you can use crosspoint

More information

FPGAs Provide Reconfigurable DSP Solutions

FPGAs Provide Reconfigurable DSP Solutions FPGAs Provide Reconfigurable DSP Solutions Razak Mohammedali Product Marketing Engineer Altera Corporation DSP processors are widely used for implementing many DSP applications. Although DSP processors

More information

9. Functional Description Example Designs

9. Functional Description Example Designs November 2012 EMI_RM_007-1.3 9. Functional Description Example Designs EMI_RM_007-1.3 This chapter describes the example designs and the traffic generator. Two independent example designs are created during

More information

Table 1 shows the issues that affect the FIR Compiler v7.1.

Table 1 shows the issues that affect the FIR Compiler v7.1. May 2007, Version 7.1 Errata Sheet This document addresses known errata and documentation issues for the Altera, v7.1. Errata are functional defects or errors, which may cause an Altera MegaCore function

More information

DKAN0011A Setting Up a Nios II System with SDRAM on the DE2

DKAN0011A Setting Up a Nios II System with SDRAM on the DE2 DKAN0011A Setting Up a Nios II System with SDRAM on the DE2 04 November 2009 Introduction This tutorial details how to set up and instantiate a Nios II system on Terasic Technologies, Inc. s DE2 Altera

More information

Simulating Excalibur Systems

Simulating Excalibur Systems Simulating Excalibur Systems September 2002, ver. 1.0 Application Note 240 Introduction Altera provides users of Excalibur systems with a powerful multilayered simulation environment that can be used to

More information

Introduction to the Altera Qsys System Integration Tool. 1 Introduction. For Quartus Prime 15.1

Introduction to the Altera Qsys System Integration Tool. 1 Introduction. For Quartus Prime 15.1 Introduction to the Altera Qsys System Integration Tool For Quartus Prime 15.1 1 Introduction This tutorial presents an introduction to Altera s Qsys system integration tool, which is used to design digital

More information

AIRbus Interface. Features Fixed width (8-, 16-, or 32-bit) data transfers (dependent on the width. Functional Description. General Arrangement

AIRbus Interface. Features Fixed width (8-, 16-, or 32-bit) data transfers (dependent on the width. Functional Description. General Arrangement AIRbus Interface December 22, 2000; ver. 1.00 Functional Specification 9 Features Fixed width (8-, 16-, or 32-bit) data transfers (dependent on the width of the data bus) Read and write access Four-way

More information

Video and Image Processing Suite

Video and Image Processing Suite Video and Image Processing Suite December 2006, Version 7.0 Errata Sheet This document addresses known errata and documentation issues for the MegaCore functions in the Video and Image Processing Suite,

More information

White Paper Using the MAX II altufm Megafunction I 2 C Interface

White Paper Using the MAX II altufm Megafunction I 2 C Interface White Paper Using the MAX II altufm Megafunction I 2 C Interface Introduction Inter-Integrated Circuit (I 2 C) is a bidirectional two-wire interface protocol, requiring only two bus lines; a serial data/address

More information

Supporting Custom Boards with DSP Builder

Supporting Custom Boards with DSP Builder Supporting Custom Boards with DSP Builder April 2003, ver. 1.0 Application Note 221 Introduction As designs become more complex, verification becomes a critical, time consuming process. To address the

More information

NIOS CPU Based Embedded Computer System on Programmable Chip

NIOS CPU Based Embedded Computer System on Programmable Chip NIOS CPU Based Embedded Computer System on Programmable Chip 1 Lab Objectives EE8205: Embedded Computer Systems NIOS-II SoPC: PART-I This lab has been constructed to introduce the development of dedicated

More information

SignalTap II with Verilog Designs. 1 Introduction. For Quartus II 13.1

SignalTap II with Verilog Designs. 1 Introduction. For Quartus II 13.1 SignalTap II with Verilog Designs For Quartus II 13.1 1 Introduction This tutorial explains how to use the SignalTap II feature within Altera s Quartus II software. The SignalTap II Embedded Logic Analyzer

More information

POS-PHY Level 4 MegaCore Function

POS-PHY Level 4 MegaCore Function POS-PHY Level 4 MegaCore Function November 2004, MegaCore Version 2.2.2 Errata Sheet Introduction This document addresses known errata and documentation changes for version v2.2.2 of the POS-PHY Level

More information

FFT MegaCore Function User Guide

FFT MegaCore Function User Guide FFT MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com MegaCore Version: 11.0 Document Date: May 2011 Copyright 2011 Altera Corporation. All rights reserved. Altera, The

More information

Design Guidelines for Using DSP Blocks

Design Guidelines for Using DSP Blocks Design Guidelines for Using DSP Blocks in the LeonardoSpectrum Software April 2002, ver. 1.0 Application Note 194 Introduction Altera R Stratix TM devices have dedicated digital signal processing (DSP)

More information

DDR & DDR2 SDRAM Controller

DDR & DDR2 SDRAM Controller DDR & DDR2 SDRAM Controller December 2005, Compiler Version 3.3.1 Release Notes These release notes for the DDR and DDR2 SDRAM Controller Compiler version 3.3.1 contain the following information: System

More information

Using SOPC Builder. with Excalibur Devices Tutorial. 101 Innovation Drive San Jose, CA (408)

Using SOPC Builder. with Excalibur Devices Tutorial. 101 Innovation Drive San Jose, CA (408) Using SOPC Builder with Excalibur Devices Tutorial 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com Document Version: 1.0 Document Date: July 2002 Copyright Excalibur Devices

More information

DDR & DDR2 SDRAM Controller

DDR & DDR2 SDRAM Controller DDR & DDR2 SDRAM Controller October 2005, Compiler Version 3.3.0 Release Notes These release notes for the DDR and DDR2 SDRAM Controller Compiler version 3.3.0 contain the following information: System

More information

White Paper Configuring the MicroBlaster Passive Serial Software Driver

White Paper Configuring the MicroBlaster Passive Serial Software Driver White Paper Configuring the MicroBlaster Passive Serial Software Driver Introduction The MicroBlaster TM software driver is designed to configure Altera programmable logic devices (PLDs) through the ByteBlasterMV

More information

Using ModelSim to Simulate Logic Circuits in VHDL Designs. 1 Introduction. For Quartus II 13.0

Using ModelSim to Simulate Logic Circuits in VHDL Designs. 1 Introduction. For Quartus II 13.0 Using ModelSim to Simulate Logic Circuits in VHDL Designs For Quartus II 13.0 1 Introduction This tutorial is a basic introduction to ModelSim, a Mentor Graphics simulation tool for logic circuits. We

More information

NIOS CPU Based Embedded Computer System on Programmable Chip

NIOS CPU Based Embedded Computer System on Programmable Chip 1 Objectives NIOS CPU Based Embedded Computer System on Programmable Chip EE8205: Embedded Computer Systems This lab has been constructed to introduce the development of dedicated embedded system based

More information

Nios II Custom Instruction User Guide Preliminary Information

Nios II Custom Instruction User Guide Preliminary Information Nios II Custom Instruction User Guide Preliminary Information 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com Copyright 2008 Altera Corporation. All rights reserved. Altera,

More information

Using the LogicLock Methodology in the

Using the LogicLock Methodology in the Using the LogicLock Methodology in the Quartus II Design Software December 2002, ver. 3.2 Application Note 161 Introduction TM Available exclusively in the Altera Quartus II software, the LogicLock TM

More information

Introduction to Simulation of VHDL Designs Using ModelSim Graphical Waveform Editor. 1 Introduction. For Quartus Prime 16.1

Introduction to Simulation of VHDL Designs Using ModelSim Graphical Waveform Editor. 1 Introduction. For Quartus Prime 16.1 Introduction to Simulation of VHDL Designs Using ModelSim Graphical Waveform Editor For Quartus Prime 16.1 1 Introduction This tutorial provides an introduction to simulation of logic circuits using the

More information

Nios Soft Core. Nios Timer Peripheral. Altera Corporation 101 Innovation Drive San Jose, CA (408)

Nios Soft Core. Nios Timer Peripheral. Altera Corporation 101 Innovation Drive San Jose, CA (408) Nios Soft Core Nios Timer Peripheral Altera Corporation 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com Nios Soft Core Nios Timer Peripheral Version 1.1 August 2000 Altera,

More information

CORDIC Reference Design. Introduction. Background

CORDIC Reference Design. Introduction. Background CORDIC Reference Design June 2005, ver. 1.4 Application Note 263 Introduction The co-ordinate rotation digital computer (CORDIC) reference design implements the CORDIC algorithm, which converts cartesian

More information

UTOPIA Level 2 Slave MegaCore Function

UTOPIA Level 2 Slave MegaCore Function UTOPIA Level 2 Slave MegaCore Function October 2005, Version 2.5.0 Release Notes These release notes for the UTOPIA Level 2 Slave MegaCore function contain the following information: System Requirements

More information

Avalon Streaming Interface Specification

Avalon Streaming Interface Specification Avalon Streaming Interface Specification 101 Innovation Drive San Jose, CA 95134 www.altera.com Document Version: 1.3 Document Date: June 2007 Copyright 2005 Altera Corporation. All rights reserved. Altera,

More information

Using MAX II & MAX 3000A Devices as a Microcontroller I/O Expander

Using MAX II & MAX 3000A Devices as a Microcontroller I/O Expander Using MAX II & MAX 3000A Devices as a Microcontroller I/O Expander March 2004, ver 2.0 Application Note 265 Introduction Advantages of Using MAX II & MAX 3000A Devices Many microcontroller and microprocessors

More information

December 2002, ver. 1.3 Application Note 191. Six individual interrupts Six-bit priority scheme Five-bit priority scheme plus one individual interrupt

December 2002, ver. 1.3 Application Note 191. Six individual interrupts Six-bit priority scheme Five-bit priority scheme plus one individual interrupt Excalibur Solutions Using the Interrupt Controller December 22, ver..3 Application Note 9 Introduction This document describes the operation of the interrupt controller for the Excalibur devices, particularly

More information

Floating Point Inverse (ALTFP_INV) Megafunction User Guide

Floating Point Inverse (ALTFP_INV) Megafunction User Guide Floating Point Inverse (ALTFP_INV) Megafunction User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com Document Version: 1.0 Document Date: October 2008 Copyright 2008 Altera Corporation. All

More information

Exercise 1 In this exercise you will review the DSSS modem design using the Quartus II software.

Exercise 1 In this exercise you will review the DSSS modem design using the Quartus II software. White Paper DSSS Modem Lab Background The direct sequence spread spectrum (DSSS) digital modem reference design is a hardware design that has been optimized for the Altera APEX DSP development board (starter

More information

Using MAX 3000A Devices as a Microcontroller I/O Expander

Using MAX 3000A Devices as a Microcontroller I/O Expander Using MAX 3000A Devices as a Microcontroller I/O Expander August 2003, Ver 1.0 Application Note 265 Introduction Advantages of Using MAX 3000A Devices Many microcontrollers and microprocessors limit I/O

More information

Quartus II Introduction Using Verilog Design

Quartus II Introduction Using Verilog Design Quartus II Introduction Using Verilog Design This tutorial presents an introduction to the Quartus R II CAD system. It gives a general overview of a typical CAD flow for designing circuits that are implemented

More information

Disassemble the machine code present in any memory region. Single step through each assembly language instruction in the Nios II application.

Disassemble the machine code present in any memory region. Single step through each assembly language instruction in the Nios II application. Nios II Debug Client This tutorial presents an introduction to the Nios II Debug Client, which is used to compile, assemble, download and debug programs for Altera s Nios II processor. This tutorial presents

More information

Simulating Visual IP Models with the NC-Verilog, Verilog-XL, VCS, or ModelSim (UNIX) Simulators

Simulating Visual IP Models with the NC-Verilog, Verilog-XL, VCS, or ModelSim (UNIX) Simulators White Paper Simulating Visual IP Models with the NC-Verilog, Verilog-XL, VCS, or ModelSim (UNIX) Simulators You can use the Visual IP software from Innoveda with Altera-provided models to simulate Altera

More information

PCI Express Multi-Channel DMA Interface

PCI Express Multi-Channel DMA Interface 2014.12.15 UG-01160 Subscribe The PCI Express DMA Multi-Channel Controller Example Design provides multi-channel support for the Stratix V Avalon Memory-Mapped (Avalon-MM) DMA for PCI Express IP Core.

More information

Avalon Bus Specification

Avalon Bus Specification Avalon Bus Specification Reference Manual 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com Document Version: 1.2 Document Date: July 2002 Copyright Avalon Bus Specification

More information

Nios Development Kit, Stratix Edition

Nios Development Kit, Stratix Edition Nios Development Kit, Stratix Edition User Guide 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com Document Version: 1.0 Document Date: January 2003 UG-NIOSSTX-1.0 P25-08785-00

More information

White Paper. Floating-Point FFT Processor (IEEE 754 Single Precision) Radix 2 Core. Introduction. Parameters & Ports

White Paper. Floating-Point FFT Processor (IEEE 754 Single Precision) Radix 2 Core. Introduction. Parameters & Ports White Paper Introduction Floating-Point FFT Processor (IEEE 754 Single Precision) Radix 2 Core The floating-point fast fourier transform (FFT) processor calculates FFTs with IEEE 754 single precision (1

More information

E3 Mapper MegaCore Function (E3MAP)

E3 Mapper MegaCore Function (E3MAP) MegaCore Function (E3MAP) March 9, 2001; ver. 1.0 Data Sheet Features Easy-to-use MegaWizard Plug-In generates MegaCore variants Quartus TM II software and OpenCore TM feature allow place-androute, and

More information

Using ModelSim to Simulate Logic Circuits for Altera FPGA Devices

Using ModelSim to Simulate Logic Circuits for Altera FPGA Devices Using ModelSim to Simulate Logic Circuits for Altera FPGA Devices This tutorial is a basic introduction to ModelSim, a Mentor Graphics simulation tool for logic circuits. We show how to perform functional

More information

Intel Stratix 10 H-Tile PCIe Link Hardware Validation

Intel Stratix 10 H-Tile PCIe Link Hardware Validation Intel Stratix 10 H-Tile PCIe Link Hardware Validation Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1. Intel Stratix 10 H-Tile PCIe* Link Hardware Validation... 3 1.1.

More information

System Debugging Tools Overview

System Debugging Tools Overview 9 QII53027 Subscribe About Altera System Debugging Tools The Altera system debugging tools help you verify your FPGA designs. As your product requirements continue to increase in complexity, the time you

More information

Introduction to the Qsys System Integration Tool

Introduction to the Qsys System Integration Tool Introduction to the Qsys System Integration Tool Course Description This course will teach you how to quickly build designs for Altera FPGAs using Altera s Qsys system-level integration tool. You will

More information

Using Library Modules in Verilog Designs

Using Library Modules in Verilog Designs Using Library Modules in Verilog Designs This tutorial explains how Altera s library modules can be included in Verilog-based designs, which are implemented by using the Quartus R II software. Contents:

More information

Applying the Benefits of Network on a Chip Architecture to FPGA System Design

Applying the Benefits of Network on a Chip Architecture to FPGA System Design white paper Intel FPGA Applying the Benefits of on a Chip Architecture to FPGA System Design Authors Kent Orthner Senior Manager, Software and IP Intel Corporation Table of Contents Abstract...1 Introduction...1

More information

Design Guidelines for Using DSP Blocks

Design Guidelines for Using DSP Blocks Design Guidelines for Using DSP Blocks in the Synplify Software April 2002, ver. 1.0 Application Note 193 Introduction Altera R Stratix TM devices have dedicated digital signal processing (DSP) blocks

More information

Using VCS with the Quartus II Software

Using VCS with the Quartus II Software Using VCS with the Quartus II Sotware December 2002, ver. 1.0 Application Note 239 Introduction As the design complexity o FPGAs continues to rise, veriication engineers are inding it increasingly diicult

More information

Designing with ESBs in APEX II Devices

Designing with ESBs in APEX II Devices Designing with ESBs in APEX II Devices March 2002, ver. 1.0 Application Note 179 Introduction In APEX TM II devices, enhanced embedded system blocks (ESBs) support memory structures, such as single-port

More information

Generic Serial Flash Interface Intel FPGA IP Core User Guide

Generic Serial Flash Interface Intel FPGA IP Core User Guide Generic Serial Flash Interface Intel FPGA IP Core User Guide Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1. Generic

More information

RapidIO Physical Layer MegaCore Function

RapidIO Physical Layer MegaCore Function RapidIO Physical Layer MegaCore Function April 2005, MegaCore version 2.2.1 Errata Sheet Introduction This document addresses known errata and documentation changes for version 2.2.1 of the RapidIO Physical

More information

RapidIO MegaCore Function

RapidIO MegaCore Function March 2007, MegaCore Function Version 3.1.1 Errata Sheet This document addresses known errata and documentation issues for the Altera RapidIO MegaCore function version 3.1.1. Errata are functional defects

More information

Simulating the ASMI Block in Your Design

Simulating the ASMI Block in Your Design 2015.08.03 AN-720 Subscribe Supported Devices Overview You can simulate the ASMI block in your design for the following devices: Arria V, Arria V GZ, Arria 10 Cyclone V Stratix V In the Quartus II software,

More information

Stratix FPGA Family. Table 1 shows these issues and which Stratix devices each issue affects. Table 1. Stratix Family Issues (Part 1 of 2)

Stratix FPGA Family. Table 1 shows these issues and which Stratix devices each issue affects. Table 1. Stratix Family Issues (Part 1 of 2) January 2007, ver. 3.1 Errata Sheet This errata sheet provides updated information on Stratix devices. This document addresses known issues and includes methods to work around the issues. Table 1 shows

More information

Using Library Modules in Verilog Designs. 1 Introduction. For Quartus II 13.0

Using Library Modules in Verilog Designs. 1 Introduction. For Quartus II 13.0 Using Library Modules in Verilog Designs For Quartus II 13.0 1 Introduction This tutorial explains how Altera s library modules can be included in Verilog-based designs, which are implemented by using

More information

SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide

SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: 8.1 Document Version: 4.0 Document Date: November 2008 UG-MF9504-4.0

More information