ECE232: Hardware Organization and Design. Computer Organization - Previously covered

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1 ECE232: Hardware Organization and Design Part 6: MIPS Instructions II Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Computer Organization - Previously covered Byte/Word addressing Registers Program counter 32 bits Processor (CPU) Control Datapath Computer Memory (where programs, & data live) Devices Input Output Keyboard, Mouse Disk (where programs, & data live when not running) Display, Printer ECE232: MIPS Instructions-II 2 Adapted from Computer Organization and Design, Patterson&Hennessy,,UCB, Kundu,UMass Koren

2 MIPS Registers Fast access to program data Register names: $0-$31 or R0-R31 Specialized names based on usage convention Register R0/$0/$zero: hardwired to constant zero $t0-$t7 ($8-$15) - temporary registers $s0-$s7 ($16-$23) - saved registers $sp - stack pointer Allow relative addressing Other special-purpose registers ECE232: MIPS Instructions-II 3 Adapted from Computer Organization and Design, Patterson&Hennessy,,UCB, Kundu,UMass Koren MIPS Instruction Types Arithmetic & Logical - manipulate data in registers add $s1, $s2, $s3 $s1 = $s2 + $s3 or $s3, $s4, $s5 $s3 = $s4 OR $s5 Instruction usage (assembly) add dest, src1, src2 dest = src1 + src2 Instruction characteristics Always 3 operands: 2 sources + destination Operand order is fixed Operands are always general-purpose registers ECE232: MIPS Instructions-II 4 Adapted from Computer Organization and Design, Patterson&Hennessy,,UCB, Kundu,UMass Koren

3 MIPS Instruction Types - 2 Data Transfer - move register data to/from memory lw $s1, 100($s2) $s1 = Memory[$s ] sw $s1, 100($s2) Memory[$s ] = $s1 Branch - alter program flow beq $s1, $s2, 25 if ($s1==$s2) skip 25 instructions ECE232: MIPS Instructions-II 5 Adapted from Computer Organization and Design, Patterson&Hennessy,,UCB, Kundu,UMass Koren Arithmetic/Logical Instructions: Binary Representation 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits op rs rt rd shamt funct Each instruction 32 bits Used for arithmetic, logical, shift instructions op: Basic operation of the instruction (opcode) rs: first register source operand rt: second register source operand rd: register destination operand shamt: shift amount (more about this later) funct: function - specific type of operation Also called R-Format or R-Type Instructions ECE232: MIPS Instructions-II 6 Adapted from Computer Organization and Design, Patterson&Hennessy,,UCB, Kundu,UMass Koren

4 MIPS Instructions All instructions exactly 32 bits wide Different formats for different purposes Similarities in formats ease implementation 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits op rs rt rd shamt funct 6 bits 5 bits 5 bits 16 bits op rs rt offset 6 bits 26 bits R-Format I-Format (e.g., Load/Store, Branch) op address J-Format (e.g., Jump) ECE232: MIPS Instructions-II 7 Adapted from Computer Organization and Design, Patterson&Hennessy,,UCB, Kundu,UMass Koren MIPS Arithmetic Instructions Instruction Example Meaning Comments add add $1,$2,$3 $1 = $2 + $3 3 operands; subtract sub $1,$2,$3 $1 = $2 $3 3 operands; add immediate addi $1,$2,100 $1 = $ constant; add unsigned addu $1,$2,$3 $1 = $2 + $3 3 operands; subtract unsigned subu $1,$2,$3 $1 = $2 $3 3 operands; add imm. unsign. addiu $1,$2,100 $1 = $ constant; multiply mult $2,$3 Hi, Lo = $2 x $3 64-bit signed product multiply unsigned multu$2,$3 Hi, Lo = $2 x $3 64-bit unsigned product divide div $2,$3 Lo = $2 $3, Lo = quotient, Hi = remainder Hi = $2 mod $3 divide unsigned divu $2,$3 Lo = $2 $3, Unsigned quotient & remainder Hi = $2 mod $3 Move from Hi mfhi $1 $1 = Hi Used to get copy of Hi Move from Lo mflo $1 $1 = Lo Used to get copy of Lo ECE232: MIPS Instructions-II 8 Adapted from Computer Organization and Design, Patterson&Hennessy,,UCB, Kundu,UMass Koren

5 MIPS Logical Instructions Instruction Example Meaning Comment and and $1,$2,$3 $1 = $2 & $3 3 reg. operands; Logical AND or or $1,$2,$3 $1 = $2 $3 3 reg. operands; Logical OR xor xor $1,$2,$3 $1 = $2 $3 3 operands; Logical XOR and immediate andi $1,$2,10 $1 = $2 & 10 Logical AND reg,constant or immediate ori $1,$2,10 $1 = $2 10 Logical OR reg, constant xor immediate xori $1, $2,10 $1 = $2 10 Logical XOR reg, constant shift left logical sll $1,$2,10 $1 = $2 << 10 Shift left by constant shift right logical srl $1,$2,10 $1 = $2 >> 10 Shift right by constant ECE232: MIPS Instructions-II 9 Adapted from Computer Organization and Design, Patterson&Hennessy,,UCB, Kundu,UMass Koren MIPS Data Transfer Instructions Transfer data between registers and memory Instruction format (assembly) lw $dest, offset($addr) load word sw $src, offset($addr) store word lw $s1, 100($s2) $s1 = Memory[$s ] sw $s1, 100($s2) Memory[$s ] = $s1 32-bit base address 16-bit offset Uses: Accessing a variable in main memory Accessing an array element ECE232: MIPS Instructions-II 10 Adapted from Computer Organization and Design, Patterson&Hennessy,,UCB, Kundu,UMass Koren

6 Example - Loading a Variable 8 R0=0 (constant) R1 R2=0x10 R3 R4 R5 = R30 R31 + 0x00 0x04 0x08 0x0c 0x10 0x14 0x18 0x1c Variable X Variable Y Variable Z = Registers lw R5,8(R2) Memory ECE232: MIPS Instructions-II 11 Adapted from Computer Organization and Design, Patterson&Hennessy,,UCB, Kundu,UMass Koren Data Transfer Instructions Binary Representation 6 bits 5 bits 5 bits 16 bits op rs rt offset Used for load, store instructions op: Basic operation of the instruction (opcode) rs: first register source operand rt: second register source operand offset: 16-bit signed address offset (-32,768 to +32,767) Also called I-Format or I-Type instructions Address source for sw destination for lw ECE232: MIPS Instructions-II 12 Adapted from Computer Organization and Design, Patterson&Hennessy,,UCB, Kundu,UMass Koren

7 I-Format vs. R-Format Instructions Compare with R-Format 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits op rs rt rd shamt funct 6 bits 5 bits 5 bits 16 bits op rs rt offset R-Format I-Format Note similarity! ECE232: MIPS Instructions-II 13 Adapted from Computer Organization and Design, Patterson&Hennessy,,UCB, Kundu,UMass Koren MIPS Conditional Branch Instructions Conditional branches allow decision making beq R1, R2, LABEL if R1==R2 goto LABEL bne R3, R4, LABEL if R3!=R4 goto LABEL beq $s1, $s2, 25 if ($s1==$s2) PC = PC *25 else PC = PC + 4 { Example C Code if (i==j) goto L1; f = g + h; L1: f = f - i; Address of next sequential instruction Offset in bytes Assembly beq $s3, $s4, L1 add $s0, $s1, $s2 L1: sub $s0, $s0, $s3 ECE232: MIPS Instructions-II 14 Adapted from Computer Organization and Design, Patterson&Hennessy,,UCB, Kundu,UMass Koren

8 Example: Compiling C if-then-else Example C Code if (i==j) f = g + h; else f = g - h; Assembly bne $s3, $s4, Else add $s0, $s1, $s2 j Exit; # new: unconditional jump Else: sub $s0, $s1, $s2 Exit: New Instruction: Unconditional jump j LABEL # goto Label ECE232: MIPS Instructions-II 15 Adapted from Computer Organization and Design, Patterson&Hennessy,,UCB, Kundu,UMass Koren Binary Representation - Branch 6 bits 5 bits 5 bits 16 bits op rs rt offset Branch instructions use I-Format offset is added to PC when branch is taken beq r0, r1, offset has the effect: Conversion to byte offset if (r0==r1) pc = pc (offset << 2) else pc = pc + 4; Offset is specified in instruction words (why?) What is the range of the branch target addresses? ECE232: MIPS Instructions-II 16 Adapted from Computer Organization and Design, Patterson&Hennessy,,UCB, Kundu,UMass Koren

9 Comparisons - What about <,, >,? bne, beq provide equality comparison slt (set on less than) provides magnitude comparison slt $t0,$s3,$s4 # if $s3<$s4 $t0=1; # else $t0=0; Combine with bne or beq to branch: slt $t0,$s3,$s4 # if (a<b) condition register bne $t0,$zero,less # goto Less; Why not include a blt instruction in hardware? Supporting in hardware would lower performance Assembler provides this function if desired (by generating the two instructions) ECE232: MIPS Instructions-II 17 Adapted from Computer Organization and Design, Patterson&Hennessy,,UCB, Kundu,UMass Koren Binary Representation - Jump 6 bits 26 bits op address Jump Instruction uses J-Format (op=2) What happens during execution? PC = PC[31:28] : (IR[25:0] << 2) Concatenate upper 4 bits of PC to form complete 32-bit address Conversion to byte offset ECE232: MIPS Instructions-II 18 Adapted from Computer Organization and Design, Patterson&Hennessy,,UCB, Kundu,UMass Koren

10 Constants / Immediate Instructions Small constants are used quite frequently (50% of operands) e.g., A = A + 5; B = B + 1; C = C - 18; MIPS Immediate Instructions (I-Format): addi $29, $29, 4 addi $29, $29,-8 Arithmetic instructions sign-extend immed. slti $8, $18, 10 andi $29, $29, 6 Logical instructions don t sign extend immed. ori $29, $29, 4 Allows up to 16-bit constants How do you load just a constant into a register? ori $5, $zero, 666 ECE232: MIPS Instructions-II 19 Adapted from Computer Organization and Design, Patterson&Hennessy,,UCB, Kundu,UMass Koren Larger Constants Immediate operations provide only for 16-bit constants Because 16 bits fit neatly in a 32-bit instruction Because most constants are small (i.e., < 16 bits) What about when we need larger constants? Use "load upper immediate - lui (I-Format) lui $t0, Then use ori to fill in lower 16 bits: ori $t0, $t0, $t0 (original contents) filled with zeros $t ECE232: MIPS Instructions-II 20 Adapted from Computer Organization and Design, Patterson&Hennessy,,UCB, Kundu,UMass Koren

11 MIPS Registers and Usage Name Register number Usage $zero 0 the constant value 0 $at 1 reserved for assembler $v0-$v1 2-3 values for results and expression evaluation $a0-$a3 4-7 arguments $t0-$t temporary registers $s0-$s saved registers $t8-$t more temporary registers $k0-$k reserved for Operating System kernel $gp 28 global pointer $sp 29 stack pointer $fp 30 frame pointer $ra 31 return address ECE232: MIPS Instructions-II 21 Adapted from Computer Organization and Design, Patterson&Hennessy,,UCB, Kundu,UMass Koren

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