Instruction Set Architecture of MIPS Processor

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1 CSE 3421/5421: Introduction to Computer Architecture Instruction Set Architecture of MIPS Processor Presentation B Study: , , 2.10 and Handout MIPS Instructions: 32-bit Core Subset Read: 2.17 (Intel x86) 01/11/2018 Gojko Babić MIPS Processor Memory Main Processor Registers $0 Coprocessor 1 (FPU) Registers $0 $31 $31 Control Arithmetic Logic unit Prog. Counter Lo Multiply divide Hi Arithmetic unit Figure A.10.1 Coprocessor 0 (traps and memory) Registers BadVAddr Status Cause EPC g. babic Presentation B 2 1

2 MIPS Registers Main Processor (integer manipulations): bit general purpose registers GPRs (r0 r31); r0 has fixed value of zero. Attempt to writing into r0 is not illegal, but its value will not change; two 32-bit registers Hi & Lo, hold results of integer multiply and divide 32-bit program counter PC; Floating Point Processor FPU (Coprocessor 1 CP1; real number manipulations): bit floating point registers FPRs (f0 f31); five control registers; g. babic Presentation B 3 MIPS Registers (continued) Coprocessor 0 CP0 is incorporated on the MIPS CPU chip and it provides functions necessary to support operating system: exception handling, memory management scheduling and control of critical resources. Coprocessor 0 (CP0) registers (partial list): Status register (CP0reg12) processor status and control; Cause register (CP0reg13) cause of the most recent interrupt; EPC register (CP0reg14) program counter at the last interrupt; BadVAddr register (CP0reg08) the address for the most recent address related exception; g. babic Presentation B 4 2

3 MIPS Data Types MIPS operates on: 32-bit (unsigned or 2 s complement) integers, 32-bit (single precision floating point) real numbers, 64-bit (double precision floating point) real numbers; 32-bit words, bytes and half words can be loaded into GPRs After loading into GPRs, bytes and half words are either zero or sign bit expanded to fill the 32 bits; Only 32-bit units can be loaded into FPRs and 32-bit real numbers are stored in even numbered FPRs. 64-bit real numbers are stored in two consecutive FPRs, starting with even-numbered register. g. babic Presentation B 5 MIPS Memory Organization MIPS supports byte addressability: it means that a byte is the smallest unit with its address; MIPS restricts memory accesses to be aligned as follows: 32-bit word has to start at byte address that is multiple of 4; Thus, 32-bit word at address 4n includes four bytes with addresses: 4n, 4n+1, 4n+2, and 4n bit half word has to start at byte address that is multiple of 2; Thus, 16-bit word at address 2n includes two bytes with addresses: 2n and 2n+1. MIPS supports 32-bit addresses: it means that an address is given as 32-bit unsigned integer; g. babic Presentation B 6 3

4 MIPS Instruction Classes Instructions that move data: load to register from memory, store from register to memory, move between registers in same and different coprocessors ALU integer instructions: register register and registerimmediate computational instructions, Floating point instructions: register register computational instructions and real number to/from integer conversion instructions, Control-related instructions, Special control-related instructions. g. babic Presentation B 7 MIPS Instruction Layout 32-bit fixed format instruction and 3 formats; /ft /offset /ft /fs /fd and fd fs funct ft jump_target g. babic Presentation B 8 4

5 Illustration of MIPS Addressing Modes 1. Immediate addressing op rs rt Immediate 2. Register addressing op rs rt rd... funct Registers Register 3. Base addressing op rs rt offset Address Memory Register + Byte Halfword Word 4. PC-relative addressing op rs rt offset Address Memory PC + Word 5. Pseudodirect addressing op jump_target Address PC Memory Word Figure 2.18 g. babic Presentation B 9 MIPS Addressing Modes register addressing; immediate addressing; register indexed is the only memory data addressing; (in MIPS terminology called base addressing): memory address = register content plus offset since r0 always contains value 0: r0 + offset absolute addressing; offset = 0 register indirect; branch instructions use PC relative addressing: branch address = [PC] offset jump instructions use: pseudo-direct addressing with 28-bit addresses (jumps inside 256MB regions), direct (absolute) addressing with 32-bit addresses. g. babic Presentation B 10 5

6 CPU Modes and Memory Address Space There are two modes MIPS CPU can operate in: kernel mode and user mode. The processor enters Kernel Mode at power-up, or as result of an interrupt, exception, or error. The processor leaves Kernel Mode and enters User Mode when ERET instruction is executed. Memory address space is divided in two ranges (simplified): User address space: address range [0 7FFFFFFF 16 ] Kernel address space: address range [ FFFFFFFF 16 ] g. babic Presentation B 11 Dual-Mode of CPU Operation CPU mode bit in Status register indicate the current CPU mode: 0 (=kernel) or 1 (=user). When an interrupt occurs, CPU hardware switches to the kernel mode. Switching to user mode (from kernel mode) done by setting CPU mode bit ERET instruction. Exception/Interrupt kernel user ERET instruction Privileged instructions can be executed only in kernel mode. g. babic Presentation B 12 6

7 MIPS Privilege Instructions With CPU in User Mode, the program in execution has access only to the CPU and FPU registers, while when CPU operates in Kernel Mode, the program has access to the full capabilities of processor including CP0 registers. Privileged instructions will not be executed when the processor is in User mode and they will be considered (by CPU) as instructions with illegal op code. Examples of MIPS privileged instructions: any instruction that accesses Kernel address space, instructions that access CP0 registers, e.g. MFC0 and MTC0, ERET instruction. g. babic Presentation B 13 Interrupts Classes There are three classes of causes for an interrupt. 1. Interrupts caused by hardware failure: Power failure Memory parity error 2. Interrupts caused by external signals: Reset: A signal asserted on the appropriate pin; Hardware Interrupts: Interrupt requests made via asserting signal on any of special external pins. Interrupt request lines IRQ s. Usually used by I/O controllers to signal normal I/O completion or a variety of error conditions. These interrupts also called I/O interrupts. Hardware interrupts can be masked by setting appropriate bits in some CP0 register; g. babic Presentation B 14 7

8 Interrupts by External Signals Reset IRQ 1 IRQ 0 Timer g. babic Presentation B 15 Interrupts Classes (continued) 3. Interrupts as result of instruction execution (these are also called exceptions); There are two types of those interrupts: Type A caused by problems during instruction execution: Address Error: a reference to a nonexistent or illegal memory address; Reserved Instruction: An instruction with undefined opcode field or a privileged instruction in User mode; Integer Overflow: An integer instruction results in a 2 s complement overflow; Floating Point Error: e.g. divide by zero, overflow, and underflow; Type B caused by special instructions: MIPS processors: Syscall or any trap instruction executed; Intel processors: INT n instruction executed; g. babic Presentation B 16 8

9 MIPS Interrupt Processing When any of the interrupts previously listed occurs, hardware should perform some predefined (by its ISA) tasks. Here we describe in some level of details how MIPS processor processes interrupts. MIPS does hardware interrupt processing in three steps. Step 1. (Saving content of PC) EPC register gets a value equal to either: the address of a faulty instruction if the instruction itself caused problems (e.g. address error, reserved instruction) or hardware malfunctioning detected (e.g. memory parity error), the address of the next instructions which would have been executed in all other cases, i.e. for interrupts caused by external causes or by those interrupt causing instructions. g. babic Presentation B 17 MIPS Interrupt Processing (continued) Step 2. (PC gets new value and interrupt cause code is saved) PC Thus, the next instruction is fetched from location Cause register a code of the interrupt Each interrupt has its code, e.g.: hardware interrupt = 0 address error exception (load/fatch or store) = 4 or 5 bus error exception (fetch or load/store)= 6 or 7 syscall execution = 8 illegal op-code or reserved instruction exception= 10 integer arithmetic overflow = 12 trap exception floating point exception = 15 Step 3. (Mode of CPU operation set to kernel mode) CPU mode bit 0; g. babic Presentation B 18 9

10 Hardware Interrupt Processing in General Hardware interrupt processing first saves the address of the interrupted instruction. Many architectures use a system stack (in memory) to save the address, while in MIPS architecture, EPC register is used. Hardware interrupt processing then loads PC with the new address. In many architectures, new content of PC comes from one of special memory locations (interrupt vectors). Each interrupt has its specific vector address, built in the hardware as a part of ISA. In MIPS architecture, PC always gets the value , while Cause register indicates a type of interrupt or exception. Hardware interrupt processing sets CPU into kernel mode. g. babic Presentation B 19 O.S. and Hardware Interrupt Processing During booting of operating system, interrupt handling routines are loaded starting at the some memory locations. It is responsibility of the operating system to also load interrupt vectors with addresses of the interrupt handling routines. In MIPS architecture, the operating system code must start at memory address , and then based on the content of Cause register appropriate processing is performed. Hardware interrupt processing saves the address of the interrupted instruction so the interrupted program (if needed) may be later restarted at the point of interruption. Note that new incoming interrupts may be disabled, i.e. masked, while another interrupt is being processed to prevent a loss of interrupt. g. babic Presentation B 20 10

11 Problem 1: OS loads the exception handling routine at the address What else should be done so this routine is activated each time an interrupt happens? Your solution should include instructions. g. babic Presentation B 21 Problem 2: OS loads the exception handling routine at the address What else should be done so this routine is activated each time an interrupt happens? Your solution should include only one instruction. g. babic Presentation B 22 11

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