ECE154A Introduction to Computer Architecture. Homework 4 solution

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1 ECE154A Introduction to Computer Architecture Homework 4 solution According to Figure 4.65 on the textbook, each register located between two pipeline stages keeps data shown below. Register IF/ID ID/EX EX/MEM MEM/WB PC + 4 Instruction word Data Control signals for EX, MEM, and WB stages Two values read from the register file Register number (Rs, Rt, and Rd field of the instruction word) Sign-extended immediate (the lowermost 16 bits of the instruction word) Control signals for MEM and WB stages ALU result and zero signal Value which will be stored in data memory in MEM stage Destination register number (Rd or Rt) Control signals for WB stages Value read from data memory ALU result Destination register number (Rd or Rt) The registers may store some random values for instructions that do not use all of the data above. For example, the register MEM/WB will store a random value if there was no memory read. For instruction add $5, $5, $5, the data in those registers are shown in the table below. Register IF/ID ID/EX EX/MEM Data PC Control signals for EX, MEM, and WB stages v 5 and v 5 (read from the register $5 and $5) 5, 5, and Control signals for MEM and WB stages v 5 + v 5 and zero signal XXXX XXXX hex (don't care or random ) 5 (Rd and Rt are both 5) 1

2 MEM/WB Control signals for WB stages XXXX XXXX hex (don't care or random ) v 5 + v According to the previous question, register $5 needs to be read and is actually read twice. 2 nd loop 3 rd loop In Ex stage, ALU does $5 + $5. In MEM stage, each unit does nothing. sw $0, 0($1) WB sw $0, 4($1) MEM WB add $2, $2, $4 EX MEM WB beq $2, $0, loop ID EX MEM WB add $1, $2, $3 IF ID EX MEM WB sw $0, 0($1) IF ID EX MEM sw $0, 4($1) IF ID EX add $2, $2, $4 IF ID beq $2, $0, loop IF For example, when instruction add $1, $2, $3 of the third loop is in the IF stage, instruction beq $2, $0, loop of the second loop is in the ID stage and instruction add $2, $2, $4 of the second loop is in the EX stage. Stages in which the particular instruction is not doing useful work are marked in red. For example, add does no useful work in MEM stage. So there are1 5 20%of cycles in which all stages do useful work. According to question , IF/ID register stores PC + 4 (indicates the instruction after beq, however, useless) and the instruction word of beq. 4.17a The probability of branch taken is60% 25% 15% add, beq, and sw (class 1, 85% probability) use two read ports. add and lw 2

3 (class 2, 65% probability) use the write port. If class 1 instructions are fetched 3 cycles later than class 2 instructions being fetched, i.e., the ID stage of class 1 instructions and the WB stage of class 2 instructions are executed simultaneously, all three register ports are used in the same cycle. The probability is85% 65% 55.25%. Only lw and sw instructions use data memory, so15% 10% 25%. Single-cycle datapath:, ns Pipelined datapath:, {100,120,90,130,60} ns Speedup is b In general, an instruction j is said data dependent on instruction i if either of the following holds 1. Instruction i produces a result that may be used by instruction j, or 2. Instruction j is data dependent on instruction k and instruction k is data dependent on instruction i Typically only type 1 data dependency is sufficient to satisfy for the correct execution of the program since type 2 dependency just implies that one instruction is dependent on another if there exist a chain of dependencies of the first type between the two instructions. A dependency between two instructions will only result in a data hazard if the instructions are close enough together for the considered simple datapath in class. In general, it may also become a hazard for advanced pipelined designs when the processor executes multiple and/or out-of-order instructions There are three particular data dependencies: 1. RAW (read after write) j reads a source after i writes it 2. WAW (write after write) j writes an operand after it is written by I 3. WAR (write after read) j writes a destination after it is read by i 3

4 Note that RAW is what is called true data dependency because there is a flow of data between the instructions. WAW and WAR are called name dependency, since two instructions use the same register of memory location (but there is no flow of data between the instructions) I1 add $1, $2, $3 I2 sw $2, 0($1) I3 lw $1, 4($2) I4 add $2, $2, $1 RAW (red line) WAR (green line) WAW (blue line) $1, I1 to I2 $1, I3 to I4 $2, I1 to I4 $2, I2 to I4 $2, I3 to I4 $1, I2 to I3 $1, I1 to I3 Only RAW data dependency can become hazards in a five-stage pipeline design. With forwarding Without forwarding $1, I3 to I4 $1, I1 to I2 $1, I3 to I4 $1, I1 to I2 is the first RAW hazard. -2 (the initial value) in $1 is overridden by 2563 ($2 + $3). add $1, $2, $3 $1 = $2 (63) + $3 (2500) = 2563 sw $2, 0($1) store $2 (63) to memory -2 (add not complete) lw $1, 4($2) load 0 from memory 67 to $1, override 2563 stall one cycle after lw add $2, $2, $1 $2 = $2 (63) + $1 (2563, lw not complete) = 2626 Finally, $0 = 0, $1 = 0, $2 = 2626, $3 = add $1, $2, $3 4

5 sw $2, 0($1) lw $1, 4($2) add $2, $2, $1 5

6 4.24a (from PH) Always-taken Always-not-taken 3 / 4 = 75% 1 / 4 = 25% According to the state diagram shown below, the state transition is S4 (predict not taken, wrong) S3 (predict not taken, wrong) S2 (predict taken, wrong) S3 (predict not taken, wrong) S2. The accuracy is 0%. Branch outcomes State transition & Correctness Accuracy 1 st T, T, NT, T S4( ) S3( ) S2( ) S3( ) S2 0% 2 nd T, T, NT, T 3 rd T, T, NT, T 4 th T, T, NT, T S2( ) S1( ) S1( ) S2( ) S1 75% S1( ) S1( ) S1( ) S2( ) S1 75% S1( ) S1( ) S1( ) S2( ) S1 75% The accuracy is 75% if this pattern is repeated forever. 6

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