TABLE 8-1. Control Signals for Binary Multiplier. Load. MUL0 Q 0 CAQ sr CAQ. Shift_dec. C out. Load LOADQ. CAQ sr CAQ. Shift_dec P P 1.

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1 T-192 Control Signals for Binary Multiplier TABLE 8-1 Control Signals for Binary Multiplier Block Diagram Module Microoperation Control Signal Name Control Expression Register A: A 0 Initialize IDLE G A A B Load MUL0 Q 0 CAQ sr CAQ Shift_dec MUL1 Register B: B IN Load_B LOADB Flip-Flop C: C 0 Clear_C IDLE G MUL1 C Load C out Register Q: Q IN CAQ sr CAQ Load_Q Shift_dec LOADQ Counter P: P n 1 Initialize P P 1 Shift_dec Mano & Kime Upper Saddle River, New Jersey 07458

2 T-193 State Table for Sequence Register and Decoder Part of Multiplier Control Unit TABLE 8-2 State Table for Sequence Register and Decoder Part of Multiplier Control Unit Present state Inputs Next state Decoder Outputs Name M 1 M 0 G Z M 1 M 0 IDLE MUL0 MUL1 IDLE MUL MUL Mano & Kime Upper Saddle River, New Jersey 07458

3 T-194 Control Signals for Microprogrammed Multiplier Control TABLE 8-3 Control Signals for Microprogrammed Multiplier Control Control Signal Register Transfers States in Which Signal is Active Microinstruction Bit Position Symbolic Notation Initialize A 0, P n 1 INIT 0 IT Load A A B, C C out ADD 1 LD Clear_C C 0 INIT, MUL1 2 CC Shift_dec C A Q sr C A Q, P P 1 MUL1 3 SD Mano & Kime Upper Saddle River, New Jersey 07458

4 T-195 SEL Field Definition for Binary Multiplier Control Sequencing TABLE 8-4 SEL Field Definition for Binary Multiplier Control Sequencing SEL Symbolic notation Binary Code Sequencing Microoperations NXT 00 DG 01 DQ 10 DZ 11 CAR NXTADD0 G: CAR NXTADD0 G: CAR NXTADD1 Q 0 : CAR NXTADD0 Q 0 : CAR NXTADD1 Z: CAR NXTADD0 Z: CAR NXTADD1

5 T-196 Register Transfer Description of Binary Multiplier Microprogram TABLE 8-5 Register Transfer Description of Binary Multiplier Microprogram Address IDLE INIT MUL0 ADD MUL1 Symbolic transfer statement G: CAR INIT, G: CAR IDLE C 0, A 0, P n 1, CAR MUL0 Q 0 : CAR ADD, Q 0 : CAR MUL1 A A B, C C out, CAR MUL1 C 0, C A Q sr C A Q, Z: CAR IDLE, Z: CAR MUL0, P P 1 Mano & Kime Upper Saddle River, New Jersey 07458

6 T-197 Symbolic Microprogram and Binary Microprogram for Multiplier TABLE 8-6 Symbolic Microprogram and Binary Microprogram for Multiplier Address NXTADD1 NXTADD0 SEL DATAPATH Address NXTADD1 NXTADD0 SEL DATAPATH IDLE INIT IDLE DS None INIT MUL0 NXT IT, CC MUL0 ADD MUL1 DQ None ADD MUL1 NXT LD MUL1 IDLE MUL0 DZ CC, SD Mano & Kime Upper Saddle River, New Jersey 07458

7 T-198 Truth Table for Instruction Decoder Logic TABLE 8-7 Truth Table for Instruction Decoder Logic Instruction Bits Control Word Bits Bit 15 Bit 14 Bit 13 MB MD RW MW Typical Operation Category ALU function using registers Shifter function using registers 0 Memory write using register data Memory read using register data ALU operation using a constant Shifter function using registers Memory write using constant data Memory read using constant data Mano & Kime Upper Saddle River, New Jersey 07458

8 T-199 Six Instructions for the Single-Cycle Computer Operation code Symbolic name Format Description Function MB MD RW MW ADI Immediate Add immediate R[ DR] R[ SA] zf I(2:0) 1 0 operand LD Register Load memory R[ DR] M[ R[ SA] ] 1 0 content into register ST Register Store register M[ R[ SA] ] R[ SB] content in memory INC Register Increment R[ DR] R[ SA] register NOT Register Complement R[ DR] R[ SA] 0 0 register ADD Register Add registers R[ DR] R[ SA] R[ SB] 0 0 Mano & Kime Upper Saddle River, New Jersey 07458

9 T-200 Control Word Information for Datapath TD TA TB MB FS MD RW MM MW Select Select Select Select Code Function Code Select Function Select Function Code R[DR] R[SA] R[SB] Register 0 F A FnUt No write(nw) Address No write(nw) 0 R8 R8 R8 Constant 1 F A Data In Write(WR) PC Write(WR) 1 F A B F A B 1 F A B F A B 1 F A 1 F A F A B F A B F A B F A F A F sl A F sr A F Mano & Kime Upper Saddle River, New Jersey 07458

10 T-201 Control Information for Sequence Control Fields MS MC IL PI Action Symbolic Notation Code Select Symbolic Notation Action Symbolic Notation Action Symbolic Notation Code Increment CAR CNT 000 NA NXA No load NLI No load NLP 0 Load CAR NXT 001 Opcode OPC Load instr. LDI Increment PC INP 1 If C 1, load CAR; BC 010 else increment CAR If V 1, load CAR; BV 011 else increment CAR If Z 1, load CAR; BZ 100 else increment CAR If N 1, load CAR; BN 101 else increment CAR If C 0, load CAR; BNC 110 else increment CAR If Z 0, load CAR, else increment CAR BNZ 111 Mano & Kime Upper Saddle River, New Jersey 07458

11 T-202 Symbolic Microprogram for Fetch and Execution of Six Instructions Address NXT ADD MS MC IL PI TD TA TB MB FS MD RW MM MW IF EX0 CNT LDI INP NW PC NW EXO NXT OPC NLI NLP NW NW ADI IF NXT NXA NLI NLP DR SA Constant F A B FnUt WR NW LD IF NXT NXA NLI NLP DR SA Data WR MA NW ST IF NXT NXA NLI NLP SA SB Register NW MA WR INC IF NXT NXA NLI NLP DR SA F A 1 FnUt WR NW NOT IF NXT NXA NLI NLP DR SA F A FnUt WR NW ADD IF NXT NXA NLI NLP DR SA SB Register F A B FnUt WR NW Mano & Kime Upper Saddle River, New Jersey 07458

12 T-203 Binary Microprogram for Fetch and Execution of Six Instructions Address NXT ADD MS MC IL PI TD TA TB MB FS MD RW MM MW Mano & Kime Upper Saddle River, New Jersey 07458

13 T-204 ASM Chart Elements Name Binary code IDLE 000 Register operation or output R 0 RUN Condition (a) State box (b) Example of state box (c) Decision box IDLE R 0 From decision box START Register operation or output PC 0 (d) Conditional output box (e) Example of decision and condition output box

14 T-205 ASM Block IDLE AVAIL Entry ASM BLOCK Exit START A 0 Q 0 Exit Exit MUL0 MUL1

15 T-206 ASM Timing Behavior Clock cycle 1 Clock cycle 2 Clock cycle 3 Clock START Q 0 State IDLE MUL1 AVAIL A Mano & Kime Upper Saddle River, New Jersey 07458

16 T-207 Hand Multiplication Example Multiplicand Multiplier Product

17 T-208 Hardware Multiplication Example Multiplicand Multiplier Initial partial product Add multiplicand, since multiplier bit is Partial product after add and before shift Partial product after shift Add multiplicand, since multiplier bit is Partial product after add and before shift a Partial product after shift Partial product after shift Partial product after shift Add multiplicand, since multiplier bit is Partial product after add and before shift Product after final shift a. Note that overflow temporarily occurred.

18 T-209 Block Diagram for Binary Multiplier log 2 n n 1 Counter P IN n Multiplicand Register B n Zero detect G (Go) C out Parallel adder Control unit 5 Z Q o n Multiplier 0 C Shift register A Shift register Q n n Control signals Product OUT Mano & Kime Upper Saddle River, New Jersey 07458

19 T-210 ASM Chart for Binary Multiplier IDLE G C 0, A 0 P n 1 MUL0 Q 0 A A + B, C C out MUL1 C 0, C A Q sr C A Q, P P 1 Z

20 T-211 Sequencing Part of ASM Chart for the Binary Multiplier IDLE 00 G MUL0 01 MUL1 10 Z

21 T-212 Control Unit for Binary Multiplier Using a Sequence Register and a Decoder G Z D M 0 C DECODER IDLE A0 0 MUL0 1 2 MUL1 A1 3 Initialize Clear_C Shift_dec D M 1 C Load Q 0 Clock Mano & Kime Upper Saddle River, New Jersey 07458

22 T-213 Transformation Rules for Control Unit with One Flip-Flop per State State Entry Entry State D C Exit Entry X (a) State box Entry Exit X Exit 0 Exit 1 (b) Decision box Exit 0 Exit 1 Entry 1 Entry 2 Entry 1 Entry 2 Exit (c) Junction Exit Entry X 1 Entry X Exit 1 Control Exit 1 (d) Conditional output box

23 T-214 Control Unit with One Flip-Flop per State for the Binary Multiplier 3 IDLE D 1 C G 2 4 Initialize 3 MUL0 D 1 Q 0 4 Clear _C Load C MUL1 D 1 4 Shift_dec C Clock Z 2

24 T-215 Microprogrammed Control Unit Organization Control inputs Status signals from datapath Next-address generator Control address register Sequencer Control address Address Control memory (ROM) Data Control data register (optional) Microinstruction Next-address information Control outputs Control signals to datapath

25 T-216 ASM Chart for Microprogrammed Binary Multiplier Control Unit IDLE 000 G INIT 001 A 0, C 0 P n 1 MUL0 010 Q 0 ADD 011 A A + B, C C out MUL1 100 C 0, C A Q sr C A Q, P P 1 Z

26 T-217 Microinstruction Control Unit Word Format NXTADD1 NXTADD0 SEL DATAPATH

27 T-218 Microprogrammed Control Unit for Multiplier IN n 2 Datapath 4 n OUT MUX1 2 to 1 MUX DATAPATH 0 G Z Q 0 MUX2 4 to 1 MUX S 3 CAR x 12 Control Memory (ROM) SEL NXTADD0 NXTADD1 S 1 S 0 2 Mano & Kime Upper Saddle River, New Jersey 07458

28 T-219 Two Instruction Formats Opcode Destination register (DR) Source register A (SA) Source register B (SB) (a) Register Opcode Destination register (DR) Source register A (SA) Operand (OP) (b) Immediate Mano & Kime Upper Saddle River, New Jersey 07458

29 T-220 Memory Representation of Instructions and Data Decimal address Memory contents Decimal opcode Other specified fields Operation (Subtract) DR:1, SA:2 SB:3 R1 R2 R (Store) SA:4 SB:5 M [R4] R (Add Immediate) DR:2 SA:7 OP:3 R2 R Data = 192. After execution of instruction in 35, Data = 80. Mano & Kime Upper Saddle River, New Jersey 07458

30 T-221 Storage Resource Diagram for a Simple Computer Program counter (PC) Instruction memory 2 15 x 16 Register file 8 x 16 Data memory 2 15 x 16

31 T-222 Block Diagram of a Single-Cycle Computer PC Address Instruction memory Instruction RW DA AA D Register file A B BA Instruction decoder Zero fill Constant in 1 0 MUX B MB D A B A A A M B F S M D R W M W CONTROL FS V C N Z Bus A A Bus B Function unit F B Address out Data out Data in MW Data memory Data out Address Data in DATAPATH Bus D MD MUX D

32 T-223 Diagram of Instruction Decoder Instruction Opcode DR SA SB Bit DA AA BA MB FS MD RW 0 MW Control word

33 T-224 Worst Case Delay Path in Single-Cycle Computer PC 1 ns Instruction memory 4 ns Register file (Read) 3 ns MUX B 1 ns Function unit or Data memory 4 ns MUX D 1 ns Register file (Write) 3 ns

34 T-225 Multiple-Cycle Microprogrammed Computer PI PC Z C N C V C MUX S 3 MS 16 TD DR RW 4 DA D 9 x 16 Register file 8 IL Opcode IR DR SA SB TD SA 4 Zero fill AA A B BA 4 TB SB MC MUX C 1 0 MUX B MB CAR 8 Bus A Bus B MM MUX M Control memory 256 x 28 FS V C N A Function unit B Data MW Address out out Data in Address Memory M N M M I P A S C L I Sequence control T D T A T B M B F S M D R W M M M W 4 Datapath control Z MD Bus D F MUX D Data in Data out MICROPROGRAMMED CONTROL DATAPATH

35 T-226 Format for Microinstruction NA MS M C I L P I T D T A T B MB FS M D R W M M M W Mano & Kime Upper Saddle River, New Jersey 07458

36 T-227 ASM Chart for Multiple-Cycle Microprogrammed Computer EX IF IR M [PC] PC PC + 1 IR = ? ADl R [DR] R [SA] + zf IR [2:0] IR = ? LD R [DR] M [R [SA] ] IR = ? ST M [R [SA] ] R [SB] IR = ? INC R [DR] R [SA] + 1 IR = ? NOT R [DR] R [SA] IR = ? ADD R [DR] R [SA] + R [SB] IR = ? IR = ?

37 T-228 ASM Chart for Register Indirect Instruction IR = ? LRI0 R8 M [R [ SA] ] LRI R [DR] M [R8] To IF

38 T-229 ASM Chart for Right-Shift Multiple Instruction IR = ? SRM R8 zf IR [2:0] zf IR [2:0] = 0? 1 T0 IF 0 SRM R [DR] sr R [SA], NOTE: SA = DR SRM R8 R8 1 R8 = 0? 1 T0 IF 0

39 T-230 ASM Chart for Multiple-Cycle, Decoder-Based Computer EX0 01 IF 00 IR M [PC], PC PC + 1 IR = ? (ADl) R [DR] R [SA] + zf IR [2:0] IR = ? (LD) R [DR] M [R [SA] ] IR = ? (ST) M [R [SA] ] R [SB] IR = ? (INC) R [DR] R [SA] + 1 IR = ? (NOT) R [DR] R [SA] IR = ? (ADD) R [DR] R [SA] + R [SB] IR = ? (LRI) R8 M [R [SA] ] EX1 10 R [DR] M [R8]

40 T-231 Block Diagram of Hardwired Counter and Decoder-Based, Multiple-Cycle Control Unit CR Syn. reset Counter IL Decoder I R Decoder ADI LD ST INC NOT ADD LRI 2 I F E X E X Control logic C R I L P I T D T A T B M B F S M D R W M M M W

41 T-232 Assembly Line Analogy to Computer Pipeline WAREHOUSE Mano & Kime Upper Saddle River, New Jersey 07458

42 T-233 Block Diagram of Pipelined Computer IF PC Stage 1 Address Instruction memory Instruction IF DOF IR AA Register file A data B data BA Stage 2 Instruction decoder Zero fill MUX B MB DOF AA BA MB Data A Data B EX FS MW Address out Stage 3 FS C V N Z 5 A B Function unit F Data in Data memory Data out Address EX WB Stage 4 WB DA MD RW CONTROL RW D DATAPATH Data F MD MUX D D data register file (same as above) Data I Data out Data in MW Address Data memory (same as above)

43 T-234 Pipeline Execution Pattern of Register Number Program Clock cycle IF DOF EX WB 2 IF DOF EX WB 3 IF DOF EX WB 4 IF DOF EX WB 5 IF DOF EX WB 6 IF DOF EX WB 7 Instruction IF DOF EX WB Mano & Kime Upper Saddle River, New Jersey 07458

44 T-235 Pipeline Execution Pattern of Register Sum Program Clock cycle IF DOF EX WB R1 2 IF DOF EX WB R3 3 IF DOF EX WB R5 4 IF DOF EX WB R7 5 R1, R3 IF DOF EX WB R3 6 IF DOF EX WB 7 R5, R7 IF DOF EX WB R7 8 IF DOF EX WB 9 IF DOF EX WB 10 R3, R7 IF DOF EX WB Instruction Mano & Kime Upper Saddle River, New Jersey 07458

8-1. Fig. 8-1 ASM Chart Elements 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

8-1. Fig. 8-1 ASM Chart Elements 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated. 8-1 Name Binary code IDLE 000 Register operation or output R 0 RUN Condition (a) State box (b) Example of state box (c) Decision box IDLE R 0 From decision box START Register operation or output PC 0 (d)