Intel Stratix 10 Variable Precision DSP Blocks User Guide

Size: px
Start display at page:

Download "Intel Stratix 10 Variable Precision DSP Blocks User Guide"

Transcription

1 Intel Stratix 10 Variable Precision DSP Blocks User Guide Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML

2 Contents Contents 1 Intel Stratix 10 Variable Precision DSP Blocks Overview Features Supported Operational Modes in Intel Stratix 10 Devices Resources Block Architecture Overview Input for Fixed-Point and Floating-Point Arithmetic Pipeline s for Fixed-Point and Floating-Point Arithmetic Pre-adder for Fixed-Point Arithmetic Internal Coefficient for Fixed-Point Arithmetic s for Fixed-Point and Floating-Point Arithmetic Adder or Subtractor for Fixed-Point and Floating-Point Arithmetic Accumulator, Chainout Adder, and Preload Constant for Fixed-Point Arithmetic Systolic for Fixed-Point Arithmetic Double Accumulation for Fixed-Point Arithmetic Output for Fixed-Point and Floating-Point Arithmetic Exception Handling for Floating-Point Arithmetic Operational Mode Descriptions Operational Modes for Fixed-Point Arithmetic Independent Mode Adder Sum Mode Independent Complex Multiplication Summed with 36-Bit Input Mode Systolic FIR Mode Operational Modes for Floating-Point Arithmetic Single Floating-Point Arithmetic Functions Multiple Floating-Point Arithmetic Functions Design Considerations Internal Coefficient and Pre-Adder for Fixed-Point Arithmetic Accumulator for Fixed-Point Arithmetic Chainout Adder Input Cascade for Fixed-Point Arithmetic Intel Stratix 10 Variable Precision DSP Blocks Implementation Guide Stratix 10 Native Fixed Point DSP IP Core References Supported Operational Modes Maximum Input Data Width for Fixed-Point Arithmetic Using Less Than 36-Bit Operand In x Plus 36 Mode Example Parameterizing Stratix 10 Native Fixed Point DSP IP Core Intel Stratix 10 Native Fixed Point DSP Intel FPGA IP Parameters Signals Intel FPGA Multiply Adder IP Core References Features Pre-adder Systolic Delay

3 Contents Pre-load Constant Double Accumulator Parameters General Tab Extra Modes s Tab Preadder Tab Accumulator Tab Systolic/Chainout Tab Pipelining Tab Signals ALTMULT_COMPLEX IP Core Reference Features Complex Multiplication Parameters Signals LPM_MULT () IP Core References Features Parameters General Tab General 2 Tab Pipelining Tab Signals Intel Stratix 10 Native Floating Point DSP IP References Intel Stratix 10 Native Floating Point DSP IP Core Supported Operational Modes Parameterizing the Intel Stratix 10 Native Floating-Point DSP Intel FPGA IP Intel Stratix 10 Native Floating-Point DSP Intel FPGA IP Parameters Stratix 10 Native Floating Point DSP IP Core Signals Document Revision History for Intel Stratix 10 Variable Precision DSP Blocks User Guide

4 1 Intel Stratix 10 Variable Precision DSP Blocks Overview 1.1 Features The variable-precision digital signal processing (DSP) blocks in Intel Stratix 10 devices can support fixed-point arithmetic and single-precision floating-point arithmetic. The Intel Stratix 10 DSP blocks provide high design flexibility and are optimized to support high-performance DSP applications. Related Links HyperFlex Core Architecture, Intel Stratix 10 Device Overview Provides more information about Hyper-s and the HyperFlex core architecture. Hyper-s are additional registers available in every interconnect routing segment throughout the core fabric, including the routing segments connected to the DSP inputs and outputs. The Intel Stratix 10 fixed-point arithmetic features include: High-performance, power-optimized, and fully registered multiplication operations -bit and 27-bit word lengths Two x 19 multipliers or one 27 x 27 multiplier per DSP block Built-in addition, subtraction, and 64-bit double accumulation register to combine multiplication results Cascading 19-bit or 27-bit and cascading -bit when pre-adder is used to form the tap-delay line for filtering applications Cascading 64-bit output bus to propagate output results from one block to the next block without external logic support Hard pre-adder supported in -bit and 27-bit DSP operation modes for symmetric filters Internal coefficient register bank in both -bit and 27-bit modes for filter implementation -bit and 27-bit systolic finite impulse response (FIR) filters with distributed output adder Biased rounding support The Intel Stratix 10 floating-point arithmetic is a completely hardened architecture. Features for floating-point arithmetic include : Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 ed

5 1 Intel Stratix 10 Variable Precision DSP Blocks Overview Multiplication, addition, subtraction, multiply-add, and multiply-subtract Multiplication with accumulation capability and a dynamic accumulator reset control Multiplication with cascade summation and subtraction capability Complex multiplication Direct vector dot product Systolic vector dot product Sequential vector dot product Exception handling support using exception flags 1.2 Supported Operational Modes in Intel Stratix 10 Devices Table 1. Supported Combinations of Operational Modes and Features for Variable Precision DSP Block in Intel Stratix 10 Devices Variable- Precision DSP Block Resource Operation Mode Supported Operation Instance Pre-Adder Support Coefficient Support Input Cascade Support Chainin Support Chainout Support 1 variable precision DSP block 1 variable precision DSP block Fixed-point independent x 19 multiplication Fixed-point independent 27 x 27 multiplication Fixed-point two x 19 multiplier adder mode Fixed-point x multiplier adder summed with 36-bit input Fixed-point x 19 systolic mode Floating-point multiplication mode Floating-point adder or subtract mode Floating-point multiplier adder or subtract mode 2 Yes Yes Yes (1) No No 1 Yes Yes Yes (2) Yes Yes 1 Yes Yes Yes (1) Yes Yes 1 No No No Yes Yes 1 Yes Yes Yes (1) Yes Yes 1 No No No No Yes 1 No No No No Yes 1 No No No Yes Yes continued... (1) Each of the two inputs to a pre-adder has a maximum width of -bit. When the input cascade is used to feed one of the pre-adder inputs, the maximum width for the input cascade is -bit. (2) When you enable the pre-adder feature, the input cascade support is not available. 5

6 1 Intel Stratix 10 Variable Precision DSP Blocks Overview Variable- Precision DSP Block Resource Operation Mode Supported Operation Instance Pre-Adder Support Coefficient Support Input Cascade Support Chainin Support Chainout Support 2 Variable precision DSP blocks 4 Variable precision DSP blocks Floating-point multiplier accumulate mode Floating-point vector one mode Floating-point vector two mode Fixed-point complex x19 multiplication Floating-point complex multiplication 1 No No No No Yes 1 No No No Yes Yes 1 No No No Yes Yes 1 No No No No No 1 No No No No No Table 2. Supported Combinations of Operational Modes and Dynamic Control Features for Variable Precision DSP Blocks in Intel Stratix 10 Devices Variable- Precision DSP Block Resource Operation Mode Dynamic ACCUMULATE Dynamic LOADCONST Dynamic SUB Dynamic NEGATE 1 variable precision DSP block Fixed-point independent x 19 multiplication Fixed-point independent 27 x 27 multiplication Fixed-point two x 19 multiplier adder mode Fixed-point x multiplier adder summed with 36-bit input Fixed-point x 19 systolic mode Floating-point multiplication mode Floating-point adder or subtract mode Floating-point multiplier adder or subtract mode Floating-point multiplier accumulate mode Floating-point vector one mode No No No No Yes Yes No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No No No Yes No No No No No No No continued... 6

7 1 Intel Stratix 10 Variable Precision DSP Blocks Overview Variable- Precision DSP Block Resource Operation Mode Dynamic ACCUMULATE Dynamic LOADCONST Dynamic SUB Dynamic NEGATE 2 variable precision DSP blocks 4 Variable precision DSP blocks Floating-point vector two mode Fixed-point complex x 19 multiplication Floating-point complex multiplication No No No No No No No No No No No No Related Links Design Considerations on page 39 Internal Coefficient and Pre-Adder for Fixed-Point Arithmetic on page 39 Accumulator for Fixed-Point Arithmetic on page 39 Chainout Adder on page 40 Input Cascade for Fixed-Point Arithmetic on page Resources Table 3. Number of s in Intel Stratix 10 Devices Product Line DSP Block Independent Input and Output Number of Multiplications Operator x x 27 Number of Variableprecision Single- Precision Floating-Point Single- Precision Floating- Point Adders x 19 Adder Sum Mode x Adder Summed with 36 bit Input GX 400/ SX 400 GX 650/ SX 650 GX 850/ SX 850 GX 1100/ SX 1100 GX 1650/ SX 1650 GX 2100/ SX 2100 GX 2500/ SX 2500 GX 2800/ SX 2800 GX 4500/ SX 4500 GX 5500/ SX , ,152 2,304 1,152 1,152 1,152 1,152 1,152 2,016 4,032 2,016 2,016 2,016 2,016 2,016 2,520 5,040 2,520 2,520 2,520 2,520 2,520 3,145 6,290 3,145 3,145 3,145 3,145 3,145 3,744 7,488 3,744 3,744 3,744 3,744 3,744 5,011 10,022 5,011 5,011 5,011 5,011 5,011 5,760 11,520 5,760 5,760 5,760 5,760 5,760 1,980 3,960 1,980 1,980 1,980 1,980 1,980 1,980 3,960 1,980 1,980 1,980 1,980 1,980 continued... 7

8 1 Intel Stratix 10 Variable Precision DSP Blocks Overview Product Line DSP Block Independent Input and Output Number of Multiplications Operator x x 27 Number of Variableprecision Single- Precision Floating-Point Single- Precision Floating- Point Adders x 19 Adder Sum Mode x Adder Summed with 36 bit Input TX ,326 6,652 3,326 3,326 3,326 3,326 3,326 TX ,960 7,920 3,960 3,960 3,960 3,960 3,960 TX ,011 10,022 5,011 5,011 5,011 5,011 5,011 TX ,760 11,520 5,760 5,760 5,760 5,760 5,760 MX ,520 5,040 2,520 2,520 2,520 2,520 2,520 MX ,326 6,652 3,326 3,326 3,326 3,326 3,326 MX ,960 7,920 3,960 3,960 3,960 3,960 3,960 8

9 2 Block Architecture Overview The Intel Stratix 10 variable precision DSP consists of the following blocks: Table 4. Block Architecture DSP Implementations Block Architecture Fixed-Point Arithmetic Input register bank Pipeline register Pre-adder Internal coefficient s Adder and Subtractor Accumulator, chainout adder, and Preload Constant Systolic registers Double accumulation register Output register bank Floating-Point Arithmetic Input register bank Pipeline register s Adder Accumulator Output register bank Exception Handling Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 ed

10 2 Block Architecture Overview Figure 1. Variable Precision DSP Block Architecture in x 19 Mode for Fixed-Point Arithmetic in Intel Stratix 10 Devices scanin[..0] CLK[2..0] ENA[2..0] CLR[1..0] chainin[63..0] LOADCONST ACCUMULATE NEGATE SUB Pre-Adder **Systolic s **Systolic Constant ay[..0] +/- az[17..0] ax[17..0] COEFSELA[2..0] Pipleine Input *1st Pipleine *2nd Pipleine Internal Coefficient **Systolic s x +/- +/- Adder and Subtractor + Chainout adder/ accumulator Double Accumulation Pre-Adder by[..0] bz[17..0] bx[17..0] COEFSELB[2..0] +/- x Output resulta[36:0] resultb[36:0] Internal Coefficient scanout[..0] chainout[63..0] *This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block. **Systolic registers are enabled in systolic mode only. Figure 2. Variable Precision DSP Block Architecture in 27 x 27 Mode for Fixed-Point Arithmetic in Intel Stratix 10 Devices clk [2:0] ena[2:0] clr [1:0] scanin[26:0] chainin[63:0] LOADCONST ACCUMULATE NEGATE Constant ay[26:0] az[25:0] ax[26:0] Input *1st Pipeline *2nd Pipeline Pre-Adder +/- x +/- Chainout Adder/ Accumulator + Double Accumulation COEFSELA[2:0] Internal Coefficients Output 64 resulta[63:0] scanout[26:0] chainout[63:0] *This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block. 10

11 2 Block Architecture Overview Figure 3. Variable Precision DSP Block Architecture for Floating-Point Arithmetic in Intel Stratix 10 Devices chainin[31:0] accumulate ax[31:0] ay[31:0] az[31:0] Input Adder Output resulta[31:0] mult_invalid mult_inexact mult_overflow mult_underflow adder_invalid adder_inexact adder_overflow adder_underflow chainout[31:0] *This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block. Related Links Intel Stratix 10 Native Floating Point DSP IP References on page 88 Stratix 10 Native Fixed Point DSP IP Core References on page 44 11

12 2 Block Architecture Overview 2.1 Input for Fixed-Point and Floating-Point Arithmetic The input register banks in Intel Stratix 10 DSP blocks are available for the following input signals: Table 5. Input Fixed-Point Arithmetic Data Dynamic control signals NEGATE LOADCONST ACCUMULATE SUB Data Floating-Point Arithmetic Dynamic ACCUMULATE control signal All the registers in the DSP blocks are positive-edge triggered and cleared on power up. Each multiplier operand can feed an input register or a multiplier directly, bypassing the input registers. The following variable precision DSP block signals control the input registers within the variable precision DSP block: CLK[2..0] ENA[2..0] CLR[0] 12

13 2 Block Architecture Overview Figure 4. Data Input s in Fixed-Point Arithmetic x 19 Mode CLK[2..0] ENA[2..0] scanin[..0] CLR[0] ay[..0] az[17..0] ax[17..0] Top delay registers by[..0] bz[17..0] bx[17..0] Bottom delay registers scanout[..0] 13

14 2 Block Architecture Overview Figure 5. Data Input s in Fixed-Point Arithmetic 27 x 27 Mode scanin[26..0] CLK[2..0] ENA[2..0] CLR[0] ay[26..0] az[25..0] ax[26..0] scanout[26..0] 2.2 Pipeline s for Fixed-Point and Floating-Point Arithmetic In addition to the input and output registers, there are 2 columns of pipeline registers for fixed-point arithmetic. Pipeline registers are used to get the maximum Fmax performance. The pipeline registers can be bypassed if high Fmax is not needed. The following variable precision DSP block signals control the pipeline registers within the variable precision DSP block: CLK[2..0] ENA[2..0] CLR[1] Floating-point arithmetic has 3 latency layers of pipeline registers. You can bypass all latency layers of the pipeline registers or use any one, two or three layers of pipeline registers. 14

15 2 Block Architecture Overview 2.3 Pre-adder for Fixed-Point Arithmetic Each variable precision DSP block has two 19-bit pre-adders. You can configure these pre-adders in the following configurations: -bit (signed or unsigned) addition or -bit subtraction for x 19 mode 26-bit addition or subtraction for 27 x 27 mode For x 19 mode, when both pre-adders within the same DSP block are used, they must share the same operation type (either addition or subtraction). 2.4 Internal Coefficient for Fixed-Point Arithmetic The Intel Stratix 10 variable precision DSP block has the flexibility of selecting the multiplicand from either the dynamic input or the internal coefficient. The internal coefficient can support up to eight constant coefficients for the multiplicands in -bit and 27-bit modes. When you enable the internal coefficient feature, COEFSELA/COEFSELB are used to control the selection of the coefficient multiplexer. 2.5 s for Fixed-Point and Floating-Point Arithmetic A single variable precision DSP block can perform many multiplications in parallel, depending on the data width of the multiplier and implementation. There are two multipliers per variable precision DSP block. You can configure these two multipliers in several operational modes: Table 6. Operational Modes Fixed-Point Arithmetic Two (signed or unsigned) x 19 multipliers One 27 x 27 multiplier Floating-Point Arithmetic One floating-point arithmetic single precision multiplier 15

16 2 Block Architecture Overview 2.6 Adder or Subtractor for Fixed-Point and Floating-Point Arithmetic Depending on the operational mode, you can use the adder or subtractor as follows: One 38-bit adder Performs fixed-point arithmetic addition or subtraction between two multipliers within a DSP block One floating-point arithmetic single precision adder Use the dynamic SUB port to select the adder to perform addition or subtraction operation for fixed-point arithmetic. Table 7. Adder Operations with SUB Dynamic Control Signal Operation Description SUB Signal Addition Adds the results of the two multipliers within one DP block. 0 Subtraction Subtracts the results between two multipliers within the same DSP block. 1 The dynamic SUB port is not supported in floating-point arithmetic. 2.7 Accumulator, Chainout Adder, and Preload Constant for Fixed- Point Arithmetic The Intel Stratix 10 variable precision DSP block supports accumulator and adder up to 64 bits for fixed-point arithmetic. The following signals can dynamically control the function of the accumulator and the chainout adder: NEGATE LOADCONST ACCUMULATE The accumulator and chainout adder features are not supported in two fixed-point arithmetic independent x 19 modes. Table 8. Accumulator Functions and Dynamic Control Signals Function Description NEGATE LOADCONST ACCUMULATE Zeroing Disables the accumulator Preload The result is always added to the preload value. Only one bit of the 64-bit preload value can be 1. It can be used as rounding the DSP result to any position of the 64-bit result continued... 16

17 2 Block Architecture Overview Function Description NEGATE LOADCONST ACCUMULATE Accumulation Decimation + Accumulation Decimation + Chainout Adder Adds the current result to the previous accumulate result. This function takes the current result, converts it into two s complement, and adds it to the previous result. This function takes the current result, converts it into two s complement, and adds it to the output of previous DSP block. 0 X 1 1 X Systolic for Fixed-Point Arithmetic There are two sets of systolic registers per variable precision DSP block and each set supports up to 44 bits chain in and chain out adder. If the variable precision DSP block is not configured in fixed-point arithmetic systolic FIR mode, both sets of systolic registers are bypassed. The first set of systolic registers consists of -bit and 19-bit registers that are used to register the -bit and 19-bit inputs of the upper multiplier, respectively. The second set of systolic registers are used to delay the chainin input from the previous variable precision DSP block. Below are the guidelines when implementing systolic registers in your design: The input and output register must be enabled when using systolic registers. First and second pipeline registers are optional when using systolic registers. If second pipeline is enabled, use the same clock as the input systolic register. The chainin systolic register always has the same clock source as the output register. All registers are recommended to use the same clock source to ensure correct systolic operation. 2.9 Double Accumulation for Fixed-Point Arithmetic The accumulator supports double accumulation by enabling the 64-bit double accumulation registers located between the output register bank and the accumulator feedback path. If the double accumulation register is enabled, an extra clock cycle delay is added into the feedback path of the accumulator. This register has the same CLK, ENA, and CLR settings as the output register bank. By enabling this register, you can have two accumulator channels using the same number of variable precision DSP block. This is useful when processing interleaved complex data (I, Q). 17

18 2 Block Architecture Overview 2.10 Output for Fixed-Point and Floating-Point Arithmetic The positive edge of the clock signal triggers the 74-bit bypassable output register bank and is cleared after power up. The following variable precision DSP block signals control the output register per variable precision DSP block: CLK[2..0] ENA[2..0] CLR[1]

19 2 Block Architecture Overview 2.11 Exception Handling for Floating-Point Arithmetic The Intel Stratix 10 floating-point arithmetic supports exception handling for the multiplier and adder blocks. Table 9. Supported Exception Flags Exception Flags Width Description Multiplication mult_overflow 1 This signal indicates if the multiplier result is a larger value compared to the maximum presentable value. 1: If the multiplier result is a larger value compared to the maximum representable value and the result is cast to infinity. 0: If the multiplier result is not larger than the maximum presentable value. This signal is not available in Adder or Subtract Mode. mult_underflow 1 This signal indicates if the multiplier result is a smaller value compared to the minimum presentable value. 1: If the multiplier result is a smaller value compared to the minimum representable value and the result is flushed to zero. 0: If the multiplier result is a larger than the minimum representable value. This signal is not available in Adder or Subtract Mode. mult_inexact 1 This signal indicates if the multiplier result is an exact representation. 1: If the multiplier result is: a rounded value a smaller value compared to the minimum representable value or a larger value compared to the maximum representable value. 0: If the multiplier result does not meet any of the criteria above. This signal is not available in Adder or Subtract Mode. mult_invalid 1 This signal indicates if the multiplier operation is ill-defined and produces an invalid result. 1: If the multiplier result is invalid and cast to qnan. 0: If the multiplier result is not an invalid number. This signal is not available in Adder or Subtract Mode. Addition adder_overflow 1 This signal indicates if the adder result is a larger value compared to the maximum representable value. 1: If the adder result is a larger value compared to the maximum presentable value and the result is cast to infinity. 0: If the multiplier result is not larger than the maximum presentable value. This signal is not available in Multiplication Mode. adder_underflow 1 This signal indicates if the adder result is a smaller value compared to the minimum presentable value. 1: If the multiplier result is a smaller value compared to the minimum representable value and the result is flushed to zero. 0: If the multiplier result is a larger than the minimum representable value. This signal is not available in Multiplication Mode. adder_inexact 1 This signal indicates if the adder result is an exact representation. 1: If the adder result is: a rounded value a smaller value compared to the minimum representable value or a larger value compared to the maximum representable value. 0: If the multiplier result does not meet any of the criteria above. continued... 19

20 2 Block Architecture Overview Exception Flags Width Description This signal is not available in Multiplication Mode. adder_invalid 1 This signal indicates if the adder operation is ill-defined and produces an invalid result. 1: If the multiplier result is invalid and cast to qnan. 0: If the multiplier result is not an invalid number. This signal is not available in Multiplication Mode. Table 10. Exception Handling Possible Results Input A Input B Result (3) Flags Overflow/Underflow/ Inexact/Invalid Normalized Normalized Normalized value 0/0/0/0 Normalized (rounded) value 0/0/1/0 Positive/negative infinity value 1/0/1/0 Subnormal (denormal) value 0/1/1/0 0 or Subnormal (denormal) Normalized 0 value 0/0/0/0 Positive/negative infinity Normalized Positive/negative infinity value 0/0/0/0 Quiet Not A Number (qnan) Normalized qnan value 0/0/0/0 0 or Subnormal (denormal) 0 or Subnormal (denormal) 0 value 0/0/0/0 Positive/negative infinity 0 or Subnormal (denormal) qnan value 0/0/0/1 Quiet Not A Number (qnan) 0 or Subnormal (denormal) qnan value 0/0/0/0 Positive/negative infinity Positive/negative Infinity Positive/negative infinity value 0/0/0/0 Quiet Not A Number (qnan) Positive/negative Infinity qnan value 0/0/0/0 Quiet Not A Number (qnan) Quiet Not A Number (qnan) qnan value 0/0/0/0 Table 11. Adder Exception Handling Possible Results Input A Input B Result : (3) Flags Overflow/Underflow/ Inexact/Invalid Normalized Normalized Normalized value 0/0/0/0 Normalized (rounded) value 0/0/1/0 Positive/negative infinity value 0 value Sign bit = 0 1/0/1/0 0/0/0/0 Subnormal (denormal) value 0/1/1/0 continued... (3) Output exception flags. These flags do not change if exceptions are at input value. 20

21 2 Block Architecture Overview Input A Input B Result : (3) The sign is preserved Flags Overflow/Underflow/ Inexact/Invalid 0 or Subnormal (denormal) Normalized Input b 0/0/0/0 Positive/negative infinity Normalized Positive/negative infinity value 0/0/0/0 Quiet Not A Number (qnan) Normalized qnan value 0/0/0/0 0 or Subnormal (denormal) 0 or Subnormal (denormal) 0 value For (-0 + (-0)) equation, sign bit = 1. For any other equation, sign bit = 0. Positive/negative infinity 0 or Subnormal (denormal) Positive/negative infinity value 0/0/0/0 0/0/0/0 Quiet Not A Number (qnan) 0 or Subnormal (denormal) qnan value 0/0/0/0 Positive/negative infinity Positive/negative infinity qnan value for invalid cases Positive/negative infinity value for valid cases 0/0/0/1 for invalid cases 0/0/0/0 for valid cases Valid cases are: Positive infinity value + positive infinity value Negative infinity value + negative infinity value Negative infinity value - positive infinity value Positive infinity value - negative infinity value Quiet Not A Number (qnan) Positive/negative infinity qnan value 0/0/0/0 Quiet Not A Number (qnan) Quiet Not A Number (qnan) qnan value 0/0/0/0 Related Links Stratix 10 Native Floating Point DSP IP Core Signals on page 92 21

22 3 Operational Mode Descriptions This section describes how you can configure the Intel Stratix 10 variable precision DSP block to efficiently support the fixed-point arithmetic and floating-point arithmetic operational modes. Table 12. Operational Modes Fixed-Point Arithmetic Independent multiplier mode adder sum mode Independent complex multiplier multiplication summed with 36-Bit input mode systolic FIR mode Floating-Point Arithmetic Multiplication mode Adder or subtract mode Multiply-add or multiply-subtract mode Multiply accumulate mode Vector one mode Vector two mode Direct vector dot product Complex multiplication 3.1 Operational Modes for Fixed-Point Arithmetic Independent Mode In independent input and output multiplier mode, the variable precision DSP blocks perform individual multiplication operations for general purpose multipliers. Table 13. Supported Independent Modes in Intel Stratix 10 Variable Precision DSP Blocks Configuration s per Block x 2 x (signed or unsigned) x 27 (signed or unsigned) 1 Related Links Stratix 10 Native Fixed Point DSP IP Core References on page 44 Supported Operational Modes on page or 19 Independent The or 19 independent multiplier mode uses the following equations: resulta = ax * ay resultb = bx * by Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 ed

23 3 Operational Mode Descriptions Figure 6. Two or 19 Independent per Variable Precision DSP Block for Intel Stratix 10 Devices In this figure, the variables are defined as follows: n = 19 and m = 37 for 19 signed operands n = and m = 36 for unsigned operands ay [(n-1)..0] ax [17..0] by [(n-1)..0] bx [17..0] Variable-Precision DSP Block n n Input *1st Pipeline *2nd Pipeline x x Output m m resulta[(m-1)..0] resultb[(m-1)..0] *This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block Independent The 27 x 27 independent multiplier mode uses the equation of resulta = ay * ax. Figure 7. One Independent Mode per Variable Precision DSP Block for Intel Stratix 10 Devices In this mode, the resulta can be up to 64 bits when combined with a chainout adder or accumulator. Variable-Precision DSP Block ay[26..0] ax[26..0] Input *1st Pipeline *2nd Pipeline x Output 54 resulta[53..0] *This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block. 23

24 3 Operational Mode Descriptions Adder Sum Mode The multiplier adder sum mode uses the equations: resulta = (bx * by) + (ax * ay) to calculate the sum of the two x 19 multiplications. resulta = (bx * by) - (ax * ay) to calculate the difference of the two x 19 multiplications. Figure 8. One Sum of Two 19 s with One Variable Precision DSP Block for Intel Stratix 10 Devices In this figure, the variable is defined as follows: n = 19 for 19 signed operands n = for unsigned operands SUB ay[(n-1)..0] Variable-Precision DSP Block n ax17..0] by[(n-1)..0] n Input *1st Pipeline *2nd Pipeline x +/- Adder Output 38 resulta[37..0] x bx[17..0] *This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block. Set the SUB dynamic control signal to high to calculate the difference of the two 19 multiplications. Related Links Stratix 10 Native Fixed Point DSP IP Core References on page 44 Supported Operational Modes on page Independent Complex The Intel Stratix 10 devices support the 19 complex multiplier mode using two fixed-point arithmetic multiplier adder sum mode. Figure 9. Sample of Complex Multiplication Equation The imaginary part [(a d) + (b c)] is implemented in the first variable-precision DSP block, while the real part [(a c) - (b d)] is implemented in the second variable-precision DSP block. 24

25 3 Operational Mode Descriptions Figure 10. One 19 Complex with Two Variable Precision DSP Blocks for Intel Stratix 10 Devices Variable-Precision DSP Block 1 c[..0] b[17..0] d[..0] Input *1st Pipeline * 2nd Pipeline x Adder + Output 38 Imaginary Part (ad+bc) a[17..0] x Variable-Precision DSP Block 2 d[..0] b[17..0] c[..0] a[17..0] Input *1st Pipeline * 2nd Pipeline x x Adder - Output 38 Real Part (ac-bd) *This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block. Related Links Stratix 10 Native Fixed Point DSP IP Core References on page 44 Supported Operational Modes on page Multiplication Summed with 36-Bit Input Mode Intel Stratix 10 variable precision DSP blocks support one 19 multiplication summed to a 36-bit input. The 19 multiplication summed with 36-bit input mode uses the equations: resulta = (ax * ay) + by to sum the x 19 multiplication with 36-bit input. resulta = (ax * ay) - by to subtract the x 19 multiplication with 36-bit input. 25

26 3 Operational Mode Descriptions Use the upper multiplier to provide the input for an 19 multiplication, while the bottom multiplier is bypassed. The by[17..0] and by[35..] signals are concatenated to produce a 36-bit input. Use the SUB dynamic control signal to control the adder to perform addition or subtraction operation. Figure 11. One x 19 Multiplication Summed with 36-Bit Input Mode for Intel Stratix 10 Devices In this figure, the variable is defined as follows: n = 19 for 19 signed operands n = for unsigned operands Variable-Precision DSP Block SUB ay [(n-1)..0] n ax [17..0] bx [35..] Input *1st Pipeline *2nd Pipeline x +/- Output 38 resulta[37..0] by [17..0] Adder *This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block. Related Links Stratix 10 Native Fixed Point DSP IP Core References on page 44 Supported Operational Modes on page Systolic FIR Mode The basic structure of a FIR filter consists of a series of multiplications followed by an addition. Figure 12. Basic FIR Filter Equation Depending on the number of taps and the input sizes, the delay through chaining a high number of adders can become quite large. To overcome the delay performance issue, the systolic form is used with additional delay elements placed per tap to increase the performance at the cost of increased latency. 26

27 3 Operational Mode Descriptions Figure 13. Systolic FIR Filter Equivalent Circuit y [ n ] w 1[ n ] w 2 [ n ] w k 1 [ n ] [ n w k ] c c 1 2 c k 1 c k x [ n ] Intel Stratix 10 variable precision DSP blocks support the following systolic FIR structures: -bit 27-bit In systolic FIR mode, the input of the multiplier can come from four different sets of sources: Two dynamic inputs One dynamic input and one coefficient input One coefficient input and one pre-adder output One dynamic input and one pre-adder output Related Links Stratix 10 Native Fixed Point DSP IP Core References on page 44 Supported Operational Modes on page Mapping Systolic Mode User View to Variable Precision Block Architecture View The following figure shows that the user view of the systolic FIR filter (a) can be implemented using the Intel Stratix 10 variable precision DSP blocks (d) by retiming the register and restructuring the adder. B can be retimed into systolic registers at the chainin, ay and ax input paths as shown in (b). The end result of the register retiming is shown in (c). The location of the adder is then restructured to sum both the multipliers output. The adder result is send to chainout adder to sum with the chainin value from the previous DSP block as shown in (d). 27

28 3 Operational Mode Descriptions Figure 14. Mapping Systolic Mode User View to Variable Precision Block Architecture View x[n] c1 x[n-2] c2 x[n-4] c3 x[n-6] c4 (a) Systolic FIR Filter User View w1[n] w2[n] A w3[n] B w4[n] A y[n] (b) Variable Precision Block Architecture View (Before Retiming) dataa_y0 x[n] dataa_x0 c1 datab_y1 x[n-2] datab_x1 c2 First DSP Block dataa_y0 x[n-4] dataa_x0 c3 datab_y1 x[n-6] datab_x1 c4 Second DSP Block w1[n] w2[n] w3[n] w4[n] A Chainin from Previous DSP Block B y[n] Adder Output Result Chainout Adder Retiming (c) Variable Precision Block Architecture View (After Retiming) dataa_y0 x[n] dataa_x0 c1 datab_y1 x[n-2] datab_x1 c2 First DSP Block dataa_y0 x[n-4] dataa_x0 c3 datab_y1 x[n-6] Output C datab_x1 c4 Result Second DSP Block w1[n] w2[n] Systolic s w4[n] A Chainin from Previous DSP Block B w3[n] y[n] Adder Output Result Systolic Chainout Adder Output C Result dataa_y0 x[n-4] Second DSP Block (d) Variable Precision Block Architecture View (Adder Restructured) dataa_y0 x[n] dataa_x0 c1 datab_y1 x[n-2] First DSP Block dataa_x0 c3 datab_y1 x[n-6] datab_x1 c4 datab_x1 c2 Systolic s w1[n] w2[n] w4[n] w3[n] A Chainin from Previous DSP Block Adder B y[n] Adder Output Result Systolic Chainout Adder Output C Result bit Systolic FIR Mode In -bit systolic FIR mode, the adders are configured as dual 44-bit adders, thereby giving 7 bits of overhead when using an x 19 operation mode, resulting 37-bit result. This allows a total sixteen x 19 multipliers or eight Intel Stratix 10 variable precision DSP blocks to be cascaded as systolic FIR structure. Figure 15. -Bit Systolic FIR Mode for Intel Stratix 10 Devices chainin[43..0] 44 ay[..0] az[17..0] ax[17..0] COEFSELA[2..0] by[..0] bz[17..0] bx[17..0] Input *1st Pipeline *2nd Pipeline Pre-Adder Pre-Adder +/- +/- +/- Internal Coefficient Systolic s Systolic s x x Adder Systolic + Chainout adder or accumulator Output 44 resulta[43..0] COEFSELB[2..0] 3 Internal Coefficient -bit Systolic FIR 44 chainout[43..0] *This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block. 28

29 3 Operational Mode Descriptions Bit Systolic FIR Mode In 27-bit systolic FIR mode, the chainout adder or accumulator is configured for a 64-bit operation, providing 10 bits of overhead when using a 27-bit data (54-bit products). This allows a total of eleven 27 x 27 multipliers or eleven Intel Stratix 10 variable precision DSP blocks to be cascaded as systolic FIR structure. The 27-bit systolic FIR mode allows the implementation of one stage systolic filter per DSP block. Systolic registers are not required in this mode. Figure Bit Systolic FIR Mode for Intel Stratix 10 Devices chainin[63..0] 64 ay[25..0] az[25..0] ax[26..0] COEFSELA[2..0] Input *1st Pipeline *2nd Pipeline Pre-Adder +/- Internal Coefficient 27 x 27-bit Systolic FIR + Chainout adder or accumulator Output resulta[63..0] chainout[63..0] *This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block. 3.2 Operational Modes for Floating-Point Arithmetic Single Floating-Point Arithmetic Functions One floating-point arithmetic DSP can perform the following: Multiplication mode Adder or subtract mode Multiply accumulate mode Related Links Intel Stratix 10 Native Floating Point DSP IP Core Supported Operational Modes on page Multiplication Mode This mode allows you to apply basic floating-point multiplication equation: result = ay*az The floating-point multiplication mode supports the following exception flags: 29

30 3 Operational Mode Descriptions mult_invalid mult_inexact mult_overflow mult_underflow Figure 17. Multiplication Mode for Intel Stratix 10 Devices chainin[31:0] accumulate ax[31:0] ay[31:0] az[31:0] Input Adder Output resulta[31:0] mult_invalid mult_inexact mult_overflow mult_underflow chainout[31:0] *This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block Adder or Subtract Mode This mode allows you to apply following equations: result = ax+ay result = ay-ax The floating-point adder or subtract mode supports the following exception flags: adder_invalid adder_inexact adder_overflow adder_underflow 30

31 3 Operational Mode Descriptions Figure. Adder or Subtract Mode for Intel Stratix 10 chainin[31:0] accumulate ax[31:0] ay[31:0] az[31:0] Input Pipeline Pipeline Adder Output resulta[31:0] adder_invalid adder_inexact adder_overflow adder_underflow chainout[31:0] *This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block Multiply Accumulate Mode This mode performs floating-point multiplication followed by floating-point addition or subtraction with the previous multiplication result. When ACCUMULATE signal is high, this mode uses the equation of result = (ay*az) +/- previous value. When ACCUMULATE signal is low, this mode uses the equation of result = (ay*az). The floating-point multiply accumulate mode supports the following exception flags: mult_invalid mult_inexact mult_overflow mult_underflow adder_invalid adder_inexact adder_overflow adder_underflow 31

32 3 Operational Mode Descriptions Figure 19. Multiply Accumulate Mode for Intel Stratix 10 Devices chainin[31:0] accumulate ax[31:0] ay[31:0] az[31:0] Input Adder Output resulta[31:0] mult_invalid mult_inexact mult_overflow mult_underflow adder_invalid adder_inexact adder_overflow adder_underflow chainout[31:0] *This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block Multiple Floating-Point Arithmetic Functions Two or more floating-point arithmetic DSP can perform the following: Multiply-add or multiply-subtract mode which uses single floating-point arithmetic DSP if the chainin parameter is turn off Vector one mode Vector two mode Direct vector dot product Complex multiplication Related Links Intel Stratix 10 Native Floating Point DSP IP Core Supported Operational Modes on page Multiply-Add or Multiply-Subtract Mode This mode performs floating-point multiplication followed by floating-point addition or floating-point subtraction. The chainin parameter allows you to enable a multiple-chain mode. Table 14. Equations Applied to Multiply-Add or Multiply-Subtract Mode Chainin Parameter Multiply-Add Mode Multiply-Subtract Mode Disable result = (ay*az) + ax result = (ay*az) - ax Enable result = (ay*az) + chainin result = (ay*az) - chainin The floating-point multiply-adder or multiply-subtract mode supports the following exception flags: 32

33 3 Operational Mode Descriptions mult_invalid mult_inexact mult_overflow mult_underflow adder_invalid adder_inexact adder_overflow adder_underflow Figure 20. Multiply-Add or Multiply-Subtract Mode for Intel Stratix 10 Devices chainin[31:0] accumulate ax[31:0] ay[31:0] az[31:0] Input Adder Output resulta[31:0] mult_invalid mult_inexact mult_overflow mult_underflow adder_invalid adder_inexact adder_overflow adder_underflow chainout[31:0] *This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block Vector One Mode This mode performs floating-point multiplication followed by floating-point addition or subtraction with the chainin input from the previous variable DSP Block. Input ax is directly fed into chainout. Table 15. Equations Applied to Vector One Mode Chainin Parameter Disable Enable Vector One with Floating-Point Addition result = ay * az Chainout = ax result = (ay * az) + chainin Chainout = ax Vector One with Floating-Point Subtraction result = ay * az Chainout = ax result = (ay * az) - chainin Chainout = ax The floating-point vector one mode supports the following exception flags: mult_invalid mult_inexact mult_overflow mult_underflow 33

34 3 Operational Mode Descriptions adder_invalid adder_inexact adder_overflow adder_underflow Figure 21. Vector One Mode for Intel Stratix 10 Devices chainin[31:0] accumulate ax[31:0] ay[31:0] az[31:0] Input Adder Output resulta[31:0] mult_invalid mult_inexact mult_overflow mult_underflow adder_invalid adder_inexact adder_overflow adder_underflow chainout[31:0] *This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block Vector Two Mode This mode performs floating-point multiplication where the multiplication result is directly fed to chainout. The chainin input from the previous variable DSP Block is then added or subtracted from input ax as the output result. Table 16. Equations Applied to Vector Two Mode Chainin Parameter Disable Enable Vector Two with Floating-Point Addition result = ax Chainout = ay * az result = ax + chainin Chainout = ay * az Vector Two with Floating-Point Subtraction result = ax Chainout = ay * az result = ax - chainin Chainout = ay * az The floating-point vector two mode supports the following exception flags: mult_invalid mult_inexact mult_overflow mult_underflow adder_invalid adder_inexact adder_overflow adder_underflow 34

35 3 Operational Mode Descriptions Figure 22. Vector Two Mode for Intel Stratix 10 Devices chainin[31:0] accumulate ax[31:0] ay[31:0] az[31:0] Input Adder Output resulta[31:0] mult_invalid mult_inexact mult_overflow mult_underflow adder_invalid adder_inexact adder_overflow adder_underflow chainout[31:0] *This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block Direct Vector Dot Product In the following figure, the direct vector dot product is implemented by several DSP blocks by setting the following DSP modes: Multiply-add and subtract mode with chainin parameter turned on Vector one Vector two 35

36 3 Operational Mode Descriptions Figure 23. Direct Vector Dot Product KL chainin[31:0] accumulate ax[31:0] J ay[31:0] I az[31:0] Input Vector One chainout[31:0] Adder Output resulta[31:0] IJ +KL mult_invalid mult_inexact mult_overflow mult_underflow adder_invalid adder_inexact adder_overflow adder_underflow accumulate AB + CD + EF + GH ax[31:0] H ay[31:0] G az[31:0] Input Vector Two chainin[31:0] chainout[31:0] Adder Output resulta[31:0] AB + CD +EF + GH + IJ +KL mult_invalid mult_inexact mult_overflow mult_underflow adder_invalid adder_inexact adder_overflow adder_underflow accumulate EF + GH ax[31:0] F ay[31:0] E az[31:0] Input Vector One chainout[31:0] Adder Output resulta[31:0] EF + GH mult_invalid mult_inexact mult_overflow mult_underflow adder_invalid adder_inexact adder_overflow adder_underflow accumulate AB + CD ax[31:0] D ay[31:0] C az[31:0] Input Vector Two chainin[31:0] chainout[31:0] Adder Output resulta[31:0] AB + CD + EF + GH mult_invalid mult_inexact mult_overflow mult_underflow adder_invalid adder_inexact adder_overflow adder_underflow accumulate ax[31:0] B ay31:0] A az[31:0] Input Multiplication chainin[31:0] chainout[31:0] Adder Output resulta[31:0] AB + CD mult_invalid mult_inexact mult_overflow mult_underflow adder_invalid adder_inexact adder_overflow adder_underflow *This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block Complex Multiplication The Intel Stratix 10 devices support the floating-point arithmetic single precision complex multiplier using four Intel Stratix 10 variable-precision DSP blocks. Figure 24. Sample of Complex Multiplication Equation 36

37 3 Operational Mode Descriptions The imaginary part [(a d) + (b c)] is implemented in the first two variableprecision DSP blocks, while the real part [(a c) - (b d)] is implemented in the next two variable-precision DSP blocks. Figure 25. Complex Multiplication with Imaginary Result chainin[31:0] accumulate ax[31:0] a ay[31:0] d az[31:0] Input Adder Output resulta[31:0] mult_invalid mult_inexact mult_overflow mult_underflow Multiplication Mode chainout[31:0] chainin[31:0] accumulate ax[31:0] b ay[31:0] c az[31:0] Input Multiply-Add Mode Adder Output resulta[31:0] Result Imaginary mult_invalid mult_inexact mult_overflow mult_underflow adder_invalid adder_inexact adder_overflow adder_underflow chainout[31:0] *This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block. 37

38 3 Operational Mode Descriptions Figure 26. Complex Multiplication with Result Real chainin[31:0] accumulate ax[31:0] b ay[31:0] d az[31:0] Input Adder Output resulta[31:0] mult_invalid mult_inexact mult_overflow mult_underflow Multiplication Mode chainout[31:0] chainin[31:0] accumulate ax[31:0] a ay[31:0] c az[31:0] Input Multiply-Subtract Mode Subtract Output resulta[31:0] Result Real mult_invalid mult_inexact mult_overflow mult_underflow adder_invalid adder_inexact adder_overflow adder_underflow chainout[31:0] *This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block. 38

39 4 Design Considerations You should consider the following elements in your design: Table 17. Design Considerations DSP Functions Design Elements Fixed-point arithmetic Operational modes Internal coefficient and pre-adder Accumulator Chainout adder Input cascade Floating-point arithmetic Operational modes Chainout adder Related Links Supported Operational Modes in Intel Stratix 10 Devices on page 5 For a summary of features supported per operational modes. 4.1 Internal Coefficient and Pre-Adder for Fixed-Point Arithmetic In both -bit and 27-bit modes, you can use the coefficient feature and pre-adder feature independently. When pre-adder feature is enabled in -bit modes, you must enable both top and bottom pre-adder. When internal coefficient feature is enabled in -bit modes, you must enable both top and bottom coefficient. Related Links Supported Operational Modes in Intel Stratix 10 Devices on page 5 For a summary of features supported per operational modes. 4.2 Accumulator for Fixed-Point Arithmetic The accumulator in the Intel Stratix 10 devices supports double accumulation by enabling the 64-bit double accumulation registers located between the output register bank and the accumulator. Related Links Supported Operational Modes in Intel Stratix 10 Devices on page 5 For a summary of features supported per operational modes. Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 ed

40 4 Design Considerations 4.3 Chainout Adder Table. Chainout Adder Fixed-Point Arithmetic You can use the output chaining path to add results from another DSP block. Support for all operational modes except for x or x 19 independant multiplier and 27 x 27 independant multiplier modes. Floating-Point Arithmetic You can use the output chaining path to add results from another DSP block. Support for certain operation modes: Multiply-add or multiply-subtract mode Vector one mode Vector two mode Related Links Supported Operational Modes in Intel Stratix 10 Devices on page 5 For a summary of features supported per operational modes. 4.4 Input Cascade for Fixed-Point Arithmetic The input register bank in Intel Stratix 10 variable precision DSP block supports input cascade feature. This feature provides the capability of cascading the input bus within a DSP block and to another DSP block. When you enable the input cascade feature in x 19 mode: The top multiplier Y input drives the bottom multiplier Y input within a DSP block The bottom multiplier Y input of the first DSP block drives the top multiplier Y input of the subsequent DSP block For mode, the multiplier Y input of the first DSP block drives the multiplier Y input of the subsequent DSP block. This feature is not supported with pre-adder enabled. There are two delay registers that you can use to balance the latency requirements when you use both the input cascade and chainout features in fixed-point arithmetic x 19 mode. These are the top delay registers and bottom delay registers. The ay input register must be enabled when top delay register is enabled. The clock source for both registers must be the same. Similarly, the by input register must be enabled when bottom delay register is enabled. The clock source for both registers must be the same. The delay registers are only in supported in x or x 19 independant multiplier, multiplier adder sum mode and -bit systolic FIR mode. 40

41 4 Design Considerations Figure 27. Input Cascade in Fixed-Point Arithmetic x 19 Mode CLK[2..0] ENA[2..0] scanin[..0] CLR[0] ay[..0] az[17..0] ax[17..0] Top delay registers by[..0] bz[17..0] bx[17..0] Bottom delay registers scanout[..0] 41

42 4 Design Considerations Figure 28. Input Cascade in Fixed-Point Arithmetic 27 x 27 Mode scanin[26..0] CLK[2..0] ENA[2..0] CLR[0] ay[26..0] az[25..0] ax[26..0] scanout[26..0] Related Links Supported Operational Modes in Intel Stratix 10 Devices on page 5 For a summary of features supported per operational modes. 42

43 5 Intel Stratix 10 Variable Precision DSP Blocks Implementation Guide The Intel Quartus Prime software contains tools for you to create and compile your design, and configure your device. You can prepare for device migration, set pin assignments, define placement restrictions, setup timing constraints, and customize IP cores using the Intel Quartus Prime software. The supported IP cores for Intel Stratix 10 variable precision DSP includes: Intel Stratix 10 Native Fixed Point DSP (4) Intel FPGA Multiply Adder (4) ALTMULT_COMPLEX (4) LPM_MULT (4) Intel Stratix 10 Native Floating Point DSP (4) Related Links Introduction to Intel FPGA IP Cores Provides general information about all Intel FPGA IP cores, including parameterizing, generating, upgrading, and simulating IP cores. Creating Version-Independent IP and Qsys Simulation Scripts Create simulation scripts that do not require manual updates for software or IP version upgrades. Project Management Best Practices Guidelines for efficient management and portability of your project and IP files. (4) Intel Stratix 10 variable precision DSP IP cores only available in Intel Quartus Prime Pro Edition. Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 ed

44 6 Stratix 10 Native Fixed Point DSP IP Core References The Stratix 10 Native Fixed Point DSP IP core instantiates and controls a single Intel Stratix 10 Variable Precision DSP block. Operational modes supported in the Stratix 10 Native Fixed Point DSP IP core include: full mode full top mode sum-of-2 mode plus 36 mode systolic mode mode Figure 29. Stratix 10 Native Fixed Point DSP IP Core Functional Block Diagram scanin chainin loadconst accumulate negate sub ay az ax coefsela Top Delay by bz bx coefselb clk ena clr Input s Input s Bottom Delay *1st Pipeline s *1st Pipeline s *2nd Pipeline s *2nd Pipeline s Top pre-adder +/ - Internal Coefficient +/- - Internal Coefficient Input Systolic Bottom pre-adder x Top x Bottom +/- +/- Adder Chainin Systolic + Chainadder Double Accumulator Output resulta resultb scanout chainout *This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block. Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 ed

45 6 Stratix 10 Native Fixed Point DSP IP Core References Related Links Block Architecture Overview on page 9 Independent Mode on page 22 Adder Sum Mode on page 24 Independent Complex on page Multiplication Summed with 36-Bit Input Mode on page 25 Systolic FIR Mode on page Supported Operational Modes Table 19. Operational Modes Supported by Intel Stratix 10 Native Fixed Point IP Core Operational Modes Description Full Mode This mode operates as two independent 19 or multipliers with 37-bit output. This mode applies the following equations: resulta = ax * ay resultb = bx * by Full Top Mode This mode operates as a single x 19 or x multiplier with 37-bit output. This mode applies the following equation: resulta = ax * ay Sum of Two Mode This mode operates as sum of two 19 multiplication. This mode applies the equations of: resulta = [(bx * by) + (ax * ay)] when sub signal is driven low. resulta = [(bx * by) - (ax * ay)] when sub signal is driven high. The resulta output bus can support up to 64 bits when you enable accumulator or chainout adder. Plus 36 Mode This mode operates as one 19 multiplication summed to a 36-bit input. This mode applies the equation of resulta = (ax * ay) + (bx, by). When the input bus is less than 36-bit in this mode, you are required to provide the necessary signed extension to fill up the 36-bit input. When you enable the accumulator, the resulta output bus can support up to 64 bits. Systolic Mode This mode operates as -bit systolic FIR. Enable the input systolic register and the output register when using this operational mode. When you enable the chainoout adder, the chainout and chainin width can support up to 44 bits. When you enable the accumulator, the resulta output bus can support up to 64 bits Mode This mode operates as one independent 27(signed/ unsigned) 27(signed/unsigned) multiplier. This mode applies the equation of resulta = ax * ay. The resulta output bus can support up to 64 bits when you enable accumulator or chainout adder. 45

46 6 Stratix 10 Native Fixed Point DSP IP Core References Related Links Independent Mode on page 22 Adder Sum Mode on page 24 Independent Complex on page Multiplication Summed with 36-Bit Input Mode on page 25 Systolic FIR Mode on page Maximum Input Data Width for Fixed-Point Arithmetic Table 20. Operation Mode Maximum Input Data Width for Fixed-Point Arithmetic Operational Modes Maximum Input Data Width ax ay az bx by bz COEFSELA COEFSELB Without Pre-adder or Internal Coefficient m _full 19 Not used 19 Not used Not used Not used mx_full _top 19 Not used Not used Not used Not used Not used Not used m _su mof2 (5) 19 Not used (5) 19 Not used Not used Not used m _sy stolic (5) 19 Not used (5) 19 Not used Not used Not used m _plu s36 19 Not used (6) Not used Not used Not used m (7) Not used Not used Not used Not used Not used Not used With Pre-adder Feature Only continued... (5) Maximum width is 17 when negate is used. (6) When the input bus is less than 36-bit, it is necessary to fill up the 36-bit input with signed extension. (7) Maximum width is 26 when negate is used. 46

47 6 Stratix 10 Native Fixed Point DSP IP Core References Operation Mode Maximum Input Data Width ax ay az bx by bz COEFSELA COEFSELB m _full Not used Not used mx_full _top Not used Not used Not used Not used Not used m _su mof2 (5) (5) Not used Not used m _sy stolic (5) (5) Not used Not used m (7) Not used Not used Not used Not used Not used With Internal Coefficient Feature Only m _full Not used 19 Not used Not used 19 Not used 3 3 mx_full _top Not used 19 Not used Not used Not used Not used 3 Not used m _su mof2 Not used 19 Not used Not used 19 Not used 3 3 m _sy stolic Not used 19 Not used Not used 19 Not used 3 3 m27 27 Not used Not used Not used Not used Not used 3 Not used With Pre-adder and Internal Coefficient Features m _full Not used Not used mx_full _top Not used Not used Not used Not used 3 Not used continued... 47

48 6 Stratix 10 Native Fixed Point DSP IP Core References Operation Mode Maximum Input Data Width ax ay az bx by bz COEFSELA COEFSELB m _su mof2 Not used Not used m _sy stolic Not used Not used m27 27 Not used Not used Not used Not used 3 Not used 48

49 6 Stratix 10 Native Fixed Point DSP IP Core References Using Less Than 36-Bit Operand In x Plus 36 Mode Example This example shows how to configure the Intel Stratix 10 Native Fixed Point DSP IP core to use Plus 36 operational mode with a signed 12-bit input data of (binary) instead of a 36-bit operand. 1. Set Representation format for bottom multiplier x operand to signed. 2. Set Representation format for bottom multiplier y operand to unsigned. 3. Set 'bx' input bus width to. 4. Set 'by' input bus width to. 5. Provide -bit signed representation data, example,' ', to bx input bus. This step is to perform sign extension. The initial 12 bits input is extended to 36 bits with bx representing the most significant bits. 6. Provide data -bit signed representation data, example, ' ', to by input bus. 6.3 Parameterizing Stratix 10 Native Fixed Point DSP IP Core 1. In Intel Quartus Prime Pro Edition, create a new project that targets a Intel Stratix 10 device. 2. In IP Catalog, click on Library DSP Primitive DSP Stratix 10 Native Fixed Point DSP. The Stratix 10 Native Fixed Point DSP IP Core IP parameter editor opens. 3. In the New IP Variation dialog box, enter an Entity Name and click OK. 4. Under Parameters, select the operation mode, multiplier configuration, clear signal, port width, and internal coefficient configurations according to the variant of your IP core 5. In the DSP Block View, switch the clock of each valid register. 6. Click the input and output ports in the GUI to select your desired inputs and outputs. 7. Click the Preadder symbols in the GUI to select addition or subtraction. 8. Click the Top delay register Bottom delay register and symbols in the GUI to enable the delay registers. 9. Click the multiplexer symbols in the GUI to enable the preadder modules and the internal coefficient modules. 10. Click the clken port symbols to create clock enable signal for each valid register. 11. Click the clr port symbols to create clear signal for each valid register. 12. Click Generate HDL. 13. Click Finish. 49

50 6 Stratix 10 Native Fixed Point DSP IP Core References Intel Stratix 10 Native Fixed Point DSP Intel FPGA IP Parameters Table 21. General Parameters Parameter IP Generated Parameter Value Default Value Description Operation Mode Select the Operation Mode operation_ mode m _full m _full_top m _f ull Select the desired operational mode. m _sumof2 m _plus36 m _systolic m27 27 Configuration Representation format for AX input bus signed_max signed unsigned unsigned Specify the representation format for the top multiplier x operand. Representation format foray/az input buses signed_may signed unsigned unsigned Specify the representation format for the top multiplier y operand. Representation format for BX input bus signed_mbx signed unsigned unsigned Specify the representation format for the bottom multiplier x operand. Representation format for BY/BZ input buses signed_mby signed unsigned unsigned Specify the representation format for the bottom multiplier y operand. Always select unsigned for m _plus36. Clear Signal Setting Type of clear signal clear_type none aclr sclr Port Width Setting none Select aclr to use asynchronous clear signal type for all registers. Select sclr to use synchronous clear signal type for all registers. How wide should AX input bus be? How wide should BX input bus be? ax_width 1 27 Specify the width of ax input bus. Refer to Maximum Input Data Width for Fixed-Point Arithmetic on page 46. bx_width 1 Specify the width of bx input bus. Set this parameter to 0 when using mx_full_top mode. Refer to Maximum Input Data Width for Fixed-Point Arithmetic on page 46. How wide should AY input bus be? ay_scan_in _width 1 27 Specify the width of ay or scanin input bus. Refer to Maximum Input Data Width for Fixed-Point Arithmetic on page 46. How wide should BY input bus be? How wide should AZ input bus be? by_width 1 19 Specify the width of by input bus. Set this parameter to 0 when using mx_full_top mode. Refer to Maximum Input Data Width for Fixed-Point Arithmetic on page 46. az_width 0-0 Specify the width of az input bus. Refer to Maximum Input Data Width for Fixed-Point Arithmetic on page 46. continued... 50

51 6 Stratix 10 Native Fixed Point DSP IP Core References Parameter IP Generated Parameter Value Default Value Description How wide should BZ input bus be? bz_width 0 0 Specify the width of bz input bus. Set this parameter to 0 when using mx_full_top mode. Refer to Maximum Input Data Width for Fixed-Point Arithmetic on page 46. How wide should result A width? How wide should result B width? How wide should result scanout width? result_a_wi dth result_b_wi dth scan_out_w idth Specify the width of resulta output bus Specify the width of resultb output bus. This parameter is supported only in mx_full mode Specify the width of scanout output bus. Figure 30. DSP Block View Each block is described in the DSP Block View Parameters table. Table 22. DSP Block View Parameters Parameter Value Default Value Description loadconst port (1) Disable Enable Disable Click the port symbol to enable loadconst port and its input register. accumulate port (2) Disable Enable Disable Click the port symbol to enable accumlate port and its input register. continued... 51

52 6 Stratix 10 Native Fixed Point DSP IP Core References Parameter Value Default Value Description negate port (3) Disable Enable Disable Click the port symbol to enable negate port and its input register. sub port (4) Disable Enable Disable Click the port symbol to enable sub port and its input register. Top delay register (5) Disable Enable Disable Click to enable the top delay register for ay input bus. This feature is not supported in m _plus36 and m27x27 operational mode. Bottom delay register (6) Disable Enable Disable Click to enable bottom delay register for by input bus. This feature is not supported in m _plus36, mx_top_full, and m27x27 operational mode. Scanout output bus (7) Disable Enable Disable Click to enable scanout output bus. Input cascade for ay input (8) Disable Enable Disble Click to enable input cascade module for ay input. When you enable input cascade module, the Stratix 10 Native Fixed Point DSP IP core uses the scanin input signals as input instead of ay input signal. Input cascade for by input (9) Disable Enable Disable Click to enable input cascade module for by input. When you enable input cascade module, the Stratix 10 Native Fixed Point DSP IP core uses the ay input signals as input instead of by input signal. clock (10) None Clock 0 Clock 1 Clock 2 Clock 0 To bypass any register, switch the register clock to None. Switch the register clock to: Clock 0 to use clk[0] signal as the clock source Clock 1 to use clk[1] signal as the clock source Clock 2 to use clk[2] signal as the clock source Top pre-adder (11) Disable Enable Disable Click to enable top pre-adder module. This uses az input bus as one of the operand source. To use pre-adder feature, both top and bottom preadder modules must be enabled. Top Pre-adder operation (12) Click to switch the operation of top preadder between addition and subtraction. continued... 52

53 6 Stratix 10 Native Fixed Point DSP IP Core References Parameter Value Default Value Description Top coefficient module (13) Disable Enable Disable Click to enable top internal coefficient module. To use internal coefficient feature, both top and bottom internal coefficient modules must be enabled. Bottom pre-adder (14) Disable Enable Disable Click to enable bottom preadder module. This uses bz input bus as one of the operand source. To use pre-adder feature, both top and bottom preadder modules must be enabled. Bottom coefficient module (15) Disable Enable Disable Click to enable bottom internal coefficient module. To use internal coefficient feature, both top and bottom internal coefficient modules must be enabled. Bottom Pre-adder operation (16) Click to switch the operation of bottom preadder between addition and subtraction. Chainin input bus (17) Disable Enable Disable Click to enable Chainin input bus. Clock enable for clock 0 () Disable Enable Disable Click to create clock enable signal for clock 0. Clock enable for clock 1 (19) Disable Enable Disable Click to create clock enable signal for clock 1. Clock enable for clock 2 (20) Disable Enable Disable Click to create clock enable signal for clock 2. Clear signal for input registers (21) Disable Enable Disable Click to create Clr[0] signal for all input registers. Use the Type of clear signal parameter to select asynchronous clear or synchronous clear for the input registers. Clear signal for output and pipeline registers (22) Disable Enable Disable Click to create Clr[1] signal for all output and pipeline registers. Use the Type of clear signal parameter to select asynchronous clear or synchronous clear for the output and pipeline registers. Double accumulator module (23) Disable Enable Disable Click to enable double accumulator feature. Chainout output bus (24) Disable Enable Disable Click to enable Chainout output bus. 53

54 6 Stratix 10 Native Fixed Point DSP IP Core References Table 23. Coefficient Configuration Parameter IP Generated Parameter Value Default Value Description Coefficient A Storage Configuration Coef_a_0 coef_a_0 Integer 0 Specify the coefficient values for ax input Coef_a_1 coef_a_1 bus. Coef_a_2 Coef_a_3 Coef_a_4 Coef_a_5 coef_a_2 coef_a_3 coef_a_4 coef_a_5 For -bit operation mode, the maximum input value is 2-1. For 27-bit operation, the maximum value is Coef_a_6 Coef_a_7 coef_a_6 coef_a_7 Coefficient B Storage Configuration Coef_b_0 coef_a_0 Integer 0 Specify the coefficient values for ax input Coef_b_1 coef_a_1 bus. Coef_b_2 Coef_b_3 Coef_b_4 Coef_b_5 coef_a_2 coef_a_3 coef_a_4 coef_a_5 Set coefficient values to more than when operand is set to unsigned and negate is enabled. Coef_b_6 Coef_b_7 coef_a_6 coef_a_7 54

55 6 Stratix 10 Native Fixed Point DSP IP Core References 6.4 Signals The following figure shows the input and output signals of the Stratix 10 Native Fixed Point DSP IP core. Figure 31. Stratix 10 Native Fixed Point DSP IP Core Signals Dynamic Control Signals Data Input Signals sub negate accumulate loadconst ax[17:0], [26:0] ay[:0], [26:0] az[17:0], [25:0] bx[17:0] by[:0] bz[17:0] Stratix 10 Native Fixed Point DSP resulta[63:0] resultb[36:0] chainout[63:0] scanout[26:0] chainin[63:0] scanin[26:0] Data Output Signals Output Cascade Signals Input Cascade Signals Internal Coefficient Signals Clock, Enable and Clear Signals coefsela[2:0] coefselb[2:0] clk[2:0] ena[2:0] clr[1:0] Table 24. Data Input Signals Signal Name Type Width Description ax[26:0] Input 27 Input data bus to top multiplier. This signal is not available when internal coefficient feature is enabled. ay[26:0] Input 27 Input data bus to top multiplier. When pre-adder is enabled, these signals are served as input to the top pre-adder. az[25:0] Input 26 These signal are input to the top pre-adder. These signals are only available when pre-adder is enabled and not available in mx_plus36 operational mode. bx[17:0] Input Input data bus to bottom multiplier. These signals are not available in m27 27operational mode and when internal coefficient feature is enabled. by[:0] Input 19 Input data bus to bottom multiplier. continued... 55

56 6 Stratix 10 Native Fixed Point DSP IP Core References Signal Name Type Width Description When pre-adder is enabled, these signals serve as input signals to the bottom pre-adder. These signals are not available in m27 27 operational mode. bz[17:0] Input These signals are input signals to the bottom pre-adder. These signals are only available when pre-adder is enabled. These signals are not available in mx_plus36 and m27 27 operational modes. Table 25. Data Output Signals Signal Name Type Width Decsription resulta[63:0] Output 64 Output data bus from top multiplier. Only in m _full mode, these signals support up to 37 bits. resultb[36:0] Output 37 Output data bus from bottom multiplier. These signals are only available in m _full operational mode. Table 26. Clock, Enable and Clear Signals Signal Name Type Width Description clk[2:0] Input 3 Input clock for all registers. These clock are only available if any of the input registers, pipeline registers or output register is set to Clock0 or Clock1 or Clock2. clk[0] = Clock0 clk[1] = Clock1 clk[2] = Clock2 ena[2:0] Input 3 Clock enable for clk[2:0]. These signals are active-high. ena[0] is for Clock0 ena[1] is for Clock1 ena[2] is for Clock2 clr[1:0] Input 2 These signals can be asynchronous or synchronous clear input signals for all registers. You may select the type of clear input signal using Type of CLEAR signal parameter. These signals are active-high. Use clr[0] for all input registers and use clr[1] for all pipeline and output registers. By default, this signal is de-asserted. Table 27. Dynamic Control Signals For summary of supported dynamic control features for each operational modes, please refer to Table 2 on page 6 Signal Name Type Width Description sub Input 1 Dynamic input signal to control the operation of the adder module. De-assert this signal to add the output of the top multiplier with the output of the bottom multiplier. Assert this signal to subtract the output of the top multiplier from the output of the bottom multiplier. continued... 56

57 6 Stratix 10 Native Fixed Point DSP IP Core References Signal Name Type Width Description By default, this signal is de-asserted. You can assert or de-assert this signal during run-time. This signal is not available in mx_full, mx_full_top, and m27x27 operational modes. negate Input 1 Dynamic input signal to control the operation of the chainout adder module. Deassert this signal to add the sum of the top and bottom multipliers with the chainin data input bus and accumulate loopback data. Assert this signal to subtract the sum of the top and bottom multipliers from the chainin data input bus and accumulate loopback data. By default, this signal is de-asserted. You can assert or de-assert this signal during run-time. This signal is not available in mx_full and mx_full_topoperational modes. accumulate Input 1 Input signal to enable or disable the accumulator feature. De-assert this signal to generate the current result without accumulating the previous result. Assert this signal to add the current result to the previous result. By default, this signal is de-asserted. You can assert or de-assert this signal during run-time. This signal is not available in mx_full and mx_full_topoperational modes. loadconst Input 1 Input signal to enable or disable the load constant feature. De-assert this signal to disable the load constant feature. Assert this signal to add a preload constant to the result to perform a biased rounding. By default, this signal is de-asserted. You can assert or de-assert this signal during run-time. This signal is not available in mx_full and mx_full_top operational modes. Table 28. Internal Coefficient Ports For summary of supported features for each operational modes, please refer to Table 1 on page 5 Signal Name Type Width Description coefsela[2:0] Input 3 Input selection signals for 8 coefficient values defined by user for the top multiplier. The coefficient values are stored in the internal memory and specified by parameters coef_a_0 to coef_a_7. coefsela[2:0] = 000 refers to coef_a_0 coefsela[2:0] = 001 refers to coef_a_1 coelsela[2:0] = 010 refers to coef_a_2... and so forth. These signals are only available when the internal coefficient feature is enabled. These signals are not available in mx_plus36 operational mode. coefselb[2:0] Input 3 Input selection signals for 8 coefficient values defined by user for the bottom multiplier. The coefficient values are stored in the internal memory and specified by parameters coef_b_0 to coef_b_7. continued... 57

58 6 Stratix 10 Native Fixed Point DSP IP Core References Signal Name Type Width Description coefselb[2:0] = 000 refers to coef_b_0 coefselb[2:0] = 001 refers to coef_b_1 coelselb[2:0] = 010 refers to coef_b_2... and so forth. These signals are only available when the internal coefficient feature is enabled. These signals are not available in mx_full, mx_plus36 and m27x27 operational modes. Table 29. Input Cascade Signals Signal Name Type Width Description scanin[26:0] Input 27 Input data bus for input cascade module. Connect these signals to the scanout signals from the preceding DSP core. scanout[26:0] Ouput 27 Output data bus of the input cascade module. Connect these signals to the scanin signals of the next DSP core. Table 30. Output Cascade Signals Signal Name Type Width Description chainin[63:0] Input 64 Input data bus for output cascade module. Connect these signals to the chainout signals from the preceding DSP core. In x systolic mode, only 44 bits of output cascade is supported. chainout[63:0] Output 64 Output data bus of the output cascade module. Connect these signals to the chainin signals of the next DSP core. In x systolic mode, only 44 bits of output cascade is supported. 58

59 Data s 7 Intel FPGA Multiply Adder IP Core References The Intel FPGA Multiply Adder IP core allows you to implement a multiplier-adder. (8) The following figure shows the ports for the Intel FPGA Multiply Adder IP core. Figure 32. Intel FPGA Multiply Adder Ports accum_sload/sload_accum negate addnsub1 signa signb Control Signal s chainin scanina dataa_0 datab_0 datab_0/datac_0 coefsel0 Mult 1 Systolic dataa_1 datab_1 datab_1/datac_1 Mult 2 coefsel2 Pipeline s N Layers of Pipeline Systolic Output dataa_2 datab_2 datab_2/datac_2 Mult 3 coefsel2 Systolic dataa_3 datab_3 datab_3/datac_3 Mult 4 coefsel3 addnsub3 Control Signal scanout chainout scanouta A multiplier-adder accepts pairs of inputs, multiplies the values together and then adds to or subtracts from the products of all other pairs. (8) Intel Stratix 10 variable precision DSP IP cores only available in Intel Quartus Prime Pro Edition. Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 ed

60 7 Intel FPGA Multiply Adder IP Core References 7.1 Features Pre-adder The DSP block uses 19-bit input multipliers to process data with widths up to bits and bit input multipliers to process data with widths between to 27 bits. For data with widths more than 27 bits, the DSP block uses partial products algorithm to process the data and bit input multiplier to process data with widths between to 27 bits. The registers and extra pipeline registers for the following signals are also placed inside the DSP block: Data input Signed or unsigned select Add or subtract select Products of multipliers In the case of the output result, the first register is placed in the DSP block. However the extra latency registers are placed in logic elements outside the block. Peripheral to the DSP block, including data inputs to the multiplier, control signal inputs, and outputs of the adder, use regular routing to communicate with the rest of the device. All connections in the function use dedicated routing inside the DSP block. This dedicated routing includes the shift register chains when you select the option to shift a multiplier's registered input data from one multiplier to an adjacent multiplier. The Intel FPGA Multiply Adder IP core offers the following features: Generates a multiplier to perform multiplication operations of two numbers Note: When building multipliers larger than the natively supported size there may/ will be a performance impact resulting from the partial production implementation. Supports data widths of bits Supports signed and unsigned data representation format Supports pipelining with configurable input latency Provides an option to dynamically switch between signed and unsigned data support Provides an option to dynamically switch between add and subtract operation Supports optional asynchronous and synchronous clear and clock enable input ports Supports systolic delay register mode Supports pre-adder with 8 pre-load coefficients per multiplier Supports pre-load constant to complement accumulator feedback With pre-adder, additions or subtractions are done prior to feeding the multiplier. 60

61 7 Intel FPGA Multiply Adder IP Core References There are five pre-adder modes: Simple mode Coefficient mode Input mode Square mode Constant mode Note: When pre-adder is used (pre-adder coefficient/input/square mode), all data inputs to the multiplier must have the same clock setting Pre-adder Simple Mode In this mode, both operands derive from the input ports and pre-adder is not used or bypassed. This is the default mode. Figure 33. Pre-adder Simple Mode a0 b0 Mult0 result Pre-adder Coefficient Mode In this mode, one multiplier operand derives from the pre-adder, and the other operand derives from the internal coefficient storage. The coefficient storage allows up to 8 preset constants. The coefficient selection signals are coefsel[0..3]. This mode is expressed in the following equation. The following shows the pre-adder coefficient mode of a multiplier. Figure 34. Pre-adder Coefficient Mode Preadder a0 b0 +/- Mult0 result coefsel0 coef 61

62 7 Intel FPGA Multiply Adder IP Core References Pre-adder Input Mode In this mode, one multiplier operand derives from the pre-adder, and the other operand derives from the datac[] input port. This mode is expressed in the following equation. The following shows the pre-adder input mode of a multiplier. Figure 35. Pre-adder Input Mode a0 b0 +/- Mult0 result c Pre-adder Square Mode This mode is expressed in the following equation. The following shows the pre-adder square mode of two multipliers. Figure 36. Pre-adder Square Mode a0 b0 +/- Mult0 result Pre-adder Constant Mode In this mode, one multiplier operand derives from the input port, and the other operand derives from the internal coefficient storage. The coefficient storage allows up to 8 preset constants. The coefficient selection signals are coefsel[0..3]. This mode is expressed in the following equation. 62

63 7 Intel FPGA Multiply Adder IP Core References The following figure shows the pre-adder constant mode of a multiplier. Figure 37. Pre-adder Constant Mode a0 Mult0 result coefsel0 coef Systolic Delay In a systolic architecture, the input data is fed into a cascade of registers acting as a data buffer. Each register delivers an input sample to a multiplier where it is multiplied by the respective coefficient. The chain adder stores the gradually combined results from the multiplier and the previously registered result from the chainin[] input port to form the final result. Each multiply-add element must be delayed by a single cycle so that the results synchronize appropriately when added together. Each successive delay is used to address both the coefficient memory and the data buffer of their respective multiply-add elements. For example, a single delay for the second multiply add element, two delays for the third multiply-add element, and so on. Figure 38. Systolic s Systolic registers x(t) S -1 S -1 S -1 S S S c(0) c(1) c(2) c(n-1) S -1 S -1 S -1 S -1 y(t) x(t) represents the results from a continuous stream of input samples and y(t) represents the summation of a set of input samples, and in time, multiplied by their respective coefficients. Both the input and output results flow from left to right. The c(0) to c(n-1) denotes the coefficients. The systolic delay registers are denoted by S -1, whereas the 1 represents a single clock delay. Systolic delay registers are added at the inputs and outputs for pipelining in a way that ensures the results from the multiplier operand and the accumulated sums stay in synch. This processing element is replicated to form a circuit that computes the filtering function. This function is expressed in the following equation. 63

64 7 Intel FPGA Multiply Adder IP Core References N represents the number of cycles of data that has entered into the accumulator, y(t) represents the output at time t, A(t) represents the input at time t, and B(i) are the coefficients. The t and i in the equation correspond to a particular instant in time, so to compute the output sample y(t) at time t, a group of input samples at N different points in time, or A(n), A(n-1), A(n-2), A(n-N+1) is required. The group of N input samples are multiplied by N coefficients and summed together to form the final result y. The systolic register architecture is available only for sum-of-2 and sum-of-4 modes. The following figure shows the systolic delay register implementation of 2 multipliers. Figure 39. Systolic Delay Implementation of 2 s chainin a0 b0 Mult0 a1 b1 +/- +/- Mult1 result The sum of two multipliers is expressed in the following equation. The following figure shows the systolic delay register implementation of 4 multipliers. 64

65 7 Intel FPGA Multiply Adder IP Core References Figure 40. Systolic Delay Implementation of 4 s chainin a0 b0 Mult0 a1 b1 Mult1 a2 b2 Mult2 a3 b3 +/- +/- +/- +/- Mult3 result The sum of four multipliers is expressed in the following equation. The following lists the advantages of systolic register implementation: Reduces DSP resource usage Enables efficient mapping in the DSP block using the chain adder structure 65

66 7 Intel FPGA Multiply Adder IP Core References Pre-load Constant The pre-load constant controls the accumulator operand and complements the accumulator feedback. The valid LOADCONST_VALUE ranges from The constant value is equal to 2 N, where N = LOADCONST_VALUE. When the LOADCONST_VALUE is set to 64, the constant value is equal to 0. This function can be used as biased rounding. The following figure shows the pre-load constant implementation. Figure 41. Pre-load Constant Accumulator feedback constant a0 b0 a1 b1 +/- +/- Mult0 Mult1 result accum_sload sload_accum Double Accumulator The double accumulator feature adds an additional register in the accumulator feedback path that process the interleaved complex data (I, Q). The double accumulator register follows the output register, which includes the clock, clock enable, and aclr. The additional accumulator register returns result with a one-cycle delay. This feature enables you to have two accumulator channels with the same resource count. The following figure shows the double accumulator implementation. 66

67 7 Intel FPGA Multiply Adder IP Core References Figure 42. Double Accumulator Double Accu mulator Accumulator feedba ck a0 b0 a1 b1 +/- +/- Mult0 Mult1 Output Output result 7.2 Parameters You can customize the Intel FPGA Multiply Adder IP core by specifying the parameters using the parameter editor in the Intel Quartus Prime software General Tab Table 31. General Tab Parameter Value Default Value Description What is the number of multipliers? How wide should the A input buses be? How wide should the B input buses be? How wide should the 'result' output bus be? Number of multipliers to be added together. Values are 1 up to Specify the width of the dataa[] port Specify the width of the datab[] port Specify the width of the result[] port. Create an associated clock enable for each clock On Off Off Select this option to create clock enable for each clock Extra Modes Table 32. Extra Modes Tab Parameter Value Default Value Description Outputs Configuration output of the adder unit On Off Off Turn on this option to enable output register of the adder module. What is the source for clock input? Clock0 Clock1 Clock2 Clock0 Select Clock0, Clock1 or Clock2 to enable and specify the clock source for output registers. continued... 67

68 7 Intel FPGA Multiply Adder IP Core References Parameter Value Default Value Description You must select output of the adder unit to enable this parameter. What is the source for asynchronous clear input? ACLR0 ACLR1 Specifies the asynchronous clear source for the adder output register. You must select output of the adder unit to enable this parameter. The IP core supports either asynchronous or synchronous clear but not both. What is the source for synchronous clear input? SCLR0 SCLR1 Specifies the synchronous clear source for the adder output register. You must select output of the adder unit to enable this parameter. The IP core supports either asynchronous or synchronous clear but not both. Adder Operation What operation should be performed on outputs of the first pair of multipliers? ADD, SUB, VARIABLE ADD Select addition or subtraction operation to perform for the outputs between the first and second multipliers. Select ADD to perform addition operation. Select SUB to perform subtraction operation. Select VARIABLE to use addnsub1 port for dynamic addition/subtraction control. When VARIABLE value is selected: Drive addnsub1 signal to high for addition operation. Drive addnsub1 signal to low for subtraction operation. You must select more than two multipliers to enable this parameter. 'addnsub1' input On Off Off Turn on this option to enable input register for addnsub1 port. You must select VARIABLE for What operation should be performed on outputs of the first pair of multipliers to enable this parameter. What is the source for clock input? Clock0 Clock1 Clock2 Clock0 Select Clock0, Clock1 or Clock2 to specify the input clock signal for addnsub1 register. You must select 'addnsub1' input to enable this parameter. What is the source for asynchronous clear input? ACLR0 ACLR1 Specifies the asynchronous clear source for the addnsub1 register. You must select 'addnsub1' input to enable this parameter. The IP core supports either asynchronous or synchronous clear but not both. What is the source for synchronous clear input? SCLR0 SCLR1 Specifies the synchronous clear source for the addnsub1 register. You must select 'addnsub1' input to enable this parameter. The IP core supports either asynchronous or synchronous clear but not both. continued... 68

69 7 Intel FPGA Multiply Adder IP Core References Parameter Value Default Value Description What operation should be performed on outputs of the second pair of multipliers? ADD, SUB, VARIABLE ADD Select addition or subtraction operation to perform for the outputs between the third and fourth multipliers. Select ADD to perform addition operation. Select SUB to perform subtraction operation. Select VARIABLE to use addnsub1 port for dynamic addition/subtraction control. When VARIABLE value is selected: Drive addnsub1 signal to high for addition operation. Drive addnsub1 signal to low for subtraction operation. You must select the value 4 for What is the number of multipliers? to enable this parameter. 'addnsub3' input On Off Off Turn on this option to enable input register for addnsub3 signal. You must select VARIABLE for What operation should be performed on outputs of the second pair of multipliers to enable this parameter. What is the source for clock input? Clock0 Clock1 Clock2 Clock0 Select Clock0, Clock1 or Clock2 to specify the input clock signal for addnsub3 register. You must select 'addnsub3' input to enable this parameter. What is the source for asynchronous clear input? ACLR0 ACLR1 Specifies the asynchronous clear source for the addnsub3 register. You must select 'addnsub3' input to enable this parameter. The IP core supports either asynchronous or synchronous clear but not both. What is the source for synchronous clear input? SCLR0 SCLR1 Specifies the synchronous clear source for the addnsub3 register. You must select 'addnsub3' input to enable this parameter. The IP core supports either asynchronous or synchronous clear but not both. Polarity Enable use_subadd On Off Off Turn on this option to reverse the function of addnsub input port. When this option is turned on, do the following: drive addnsub to high for subtraction operation drive addnsub to low for addition operation s Tab Table 33. s Tab Parameter Value Default Value Description What is the representation format for s A inputs? SIGNED, UNSIGNED, UNSIGNED Specify the representation format for the multiplier A input. continued... 69

70 7 Intel FPGA Multiply Adder IP Core References Parameter Value Default Value Description VARIABLE signa input On Off Off Select this option to enable signa register. You must select VARIABLE value for What is the representation format for s A inputs? parameter to enable this option. What is the source for clock input? Clock0 Clock1 Clock2 Clock0 Select Clock0, Clock1 or Clock2 to enable and specify the input clock signal for signa register. You must select signa input to enable this parameter. What is the source for asynchronous clear input? ACLR0 ACLR1 Specifies the asynchronous clear source for the signa register. You must select signa input to enable this parameter. The IP core supports either asynchronous or synchronous clear but not both. What is the source for synchronous clear input? SCLR0 SCLR1 Specifies the synchronous clear source for the signa register. You must select signa input to enable this parameter. The IP core supports either asynchronous or synchronous clear but not both. What is the representation format for s B inputs? SIGNED, UNSIGNED, VARIABLE UNSIGNED Specify the representation format for the multiplier B input. signb input On Off Off Turn on this option to enable signb register. You must select VARIABLE value for What is the representation format for s B inputs? parameter to enable this option. What is the source for clock input? Clock0 Clock1 Clock2 Clock0 Select Clock0, Clock1 or Clock2 to enable and specify the input clock signal for signb register. You must select signb input to enable this parameter. What is the source for asynchronous clear input? ACLR0 ACLR1 Specifies the asynchronous clear source for the signb register. You must select signb input to enable this parameter. The IP core supports either asynchronous or synchronous clear but not both. What is the source for synchronous clear input? SCLR0 SCLR1 Specifies the synchronous clear source for the signb register. You must select signb input to enable this parameter. The IP core supports either asynchronous or synchronous clear but not both. Input Configuration input A of the multiplier On Off Off Turn on this option to enable input register for dataa input bus. What is the source for clock input? Clock0 Clock1 Clock2 Clock0 Select Clock0, Clock1 or Clock2 to enable and specify the register input clock signal for dataa input bus. continued... 70

71 7 Intel FPGA Multiply Adder IP Core References Parameter Value Default Value Description You must select input A of the multiplier to enable this parameter. What is the source for asynchronous clear input? ACLR0 ACLR1 Specifies the register asynchronous clear source for the dataa input bus. You must select input A of the multiplier to enable this parameter. The IP core supports either asynchronous or synchronous clear but not both. What is the source for synchronous clear input? SCLR0 SCLR1 Specifies the register synchronous clear source for the dataa input bus. You must select input A of the multiplier to enable this parameter. The IP core supports either asynchronous or synchronous clear but not both. input B of the multiplier On Off Off Turn on this option to enable input register for datab input bus. What is the source for clock input? Clock0 Clock1 Clock2 Clock0 Select Clock0, Clock1 or Clock2 to enable and specify the register input clock signal for datab input bus. You must select input B of the multiplier to enable this parameter. What is the source for asynchronous clear input? ACLR0 ACLR1 Specifies the register asynchronous clear source for the datab input bus. You must select input B of the multiplier to enable this parameter. The IP core supports either asynchronous or synchronous clear but not both. What is the source for synchronous clear input? SCLR0 SCLR1 Specifies the register synchronous clear source for the datab input bus. You must select input B of the multiplier to enable this parameter. The IP core supports either asynchronous or synchronous clear but not both. What is the input A of the multiplier connected to? input Scan chain input input Select the input source for input A of the multiplier. Select input to use dataa input bus as the source to the multiplier. Select Scan chain input to use scanin input bus as the source to the multiplier and enable the scanout output bus. This parameter is available when you select 2, 3 or 4 for What is the number of multipliers? parameter. Scanout A Configuration output of the scan chain On Off Off Turn on this option to enable output register for scanouta output bus. You must select Scan chain input for What is the input A of the multiplier connected to? parameter to enable this option. What is the source for clock input? Clock0 Clock1 Clock2 Clock0 Select Clock0, Clock1 or Clock2 to enable and specify the register input clock signal for scanouta output bus. continued... 71

72 7 Intel FPGA Multiply Adder IP Core References Parameter Value Default Value Description You must turn on output of the scan chain parameter to enable this option. What is the source for asynchronous clear input? ACLR0 ACLR1 Specifies the register asynchronous clear source for the scanouta output bus. You must turn on output of the scan chain parameter to enable this option. The IP core supports either asynchronous or synchronous clear but not both. What is the source for synchronous clear input? SCLR0 SCLR1 Specifies the register synchronous clear source for the scanouta output bus. You must select output of the scan chain parameter to enable this option. The IP core supports either asynchronous or synchronous clear but not both Preadder Tab Table 34. Preadder Tab Parameter Value Default Value Description Select preadder mode SIMPLE, COEF, INPUT, SQUARE, CONSTANT SIMPLE Specifies the operation mode for preadder module. SIMPLE: This mode bypass the preadder. This is the default mode. COEF: This mode uses the output of the preadder and coefsel input bus as the inputs to the multiplier. INPUT: This mode uses the output of the preadder and datac input bus as the inputs to the multiplier. SQUARE: This mode uses the output of the preadder as both the inputs to the multiplier. CONSTANT: This mode uses dataa input bus with preadder bypassed and coefsel input bus as the inputs to the multiplier. Select preadder direction ADD, SUB ADD Specifies the operation of the preadder. To enable this parameter, select the following for Select preadder mode: COEF INPUT SQUARE or CONSTANT continued... 72

73 7 Intel FPGA Multiply Adder IP Core References Parameter Value Default Value Description How wide should the C input buses be? Specifies the number of bits for C input bus. You must select INPUT for Select preadder mode to enable this parameter. Data C Input Configuration datac input On Off On Turn on this option to enable input register for datac input bus. You must set INPUT to Select preadder mode parameter to enable this option. What is the source for clock input? Clock0 Clock1 Clock2 Clock0 Select Clock0, Clock1 or Clock2 to specify the input clock signal for datac input register. You must select datac input to enable this parameter. What is the source for asynchronous clear input? ACLR0 ACLR1 Specifies the asynchronous clear source for the datac input register. You must select datac input to enable this parameter. The IP core supports either asynchronous or synchronous clear but not both. What is the source for synchronous clear input? SCLR0 SCLR1 Specifies the synchronous clear source for the datac input register. You must select datac input to enable this parameter. The IP core supports either asynchronous or synchronous clear but not both. Coefficients How wide should the coef width be? 1-27 Specifies the number of bits for coefsel input bus. You must select COEF or CONSTANT for preadder mode to enable this parameter. Coef Configuration continued... 73

74 7 Intel FPGA Multiply Adder IP Core References Parameter Value Default Value Description the coefsel input On Off Checked Select this option to enable input register for coefsel input bus. You must select COEF or CONSTANT for preadder mode to enable this parameter. What is the source for clock input? Clock0 Clock1 Clock2 Clock0 Select Clock0, Clock1 or Clock2 to specify the input clock signal for coefsel input register. You must select the coefsel input to enable this parameter. What is the source for asynchronous clear input? ACLR0 ACLR1 Specifies the asynchronous clear source for the coefsel input register. You must select the coefsel input to enable this parameter. The IP core supports either asynchronous or synchronous clear but not both. What is the source for synchronous clear input SCLR0 SCLR1 Specifies the synchronous clear source for the coefsel input register. You must select the coefsel input to enable this parameter. The IP core supports either asynchronous or synchronous clear but not both. Coefficient_0 Configuration 0x xFFFFFFF 0x Specifies the coefficient values for this first multiplier. The number of bits must be the same as specified in How wide should the coef width be? parameter. You must select COEF or CONSTANT for preadder mode to enable this parameter. Coefficient_1 Configuration 0x xFFFFFFF 0x Specifies the coefficient values for this second multiplier. The number of bits must be the same as specified in How wide should the coef width be? parameter. continued... 74

75 7 Intel FPGA Multiply Adder IP Core References Parameter Value Default Value Description You must select COEF or CONSTANT for preadder mode to enable this parameter. Coefficient_2 Configuration 0x xFFFFFFF 0x Specifies the coefficient values for this third multiplier. The number of bits must be the same as specified in How wide should the coef width be? parameter. You must select COEF or CONSTANT for preadder mode to enable this parameter. Coefficient_3 Configuration 0x xFFFFFFF 0x Specifies the coefficient values for this fourth multiplier. The number of bits must be the same as specified in How wide should the coef width be? parameter. You must select COEF or CONSTANT for preadder mode to enable this parameter Accumulator Tab Table 35. Accumulator Tab Parameter Value Default Value Description Enable accumulator? YES, NO NO Select YES to enable the accumulator. You must select output of adder unit when using accumulator feature. What is the accumulator operation type? ADD, SUB ADD Specifies the operation of the accumulator: ADD for addition operation SUB for subtraction operation. You must select YES for Enable accumulator? parameter to enable this option. Preload Constant Enable preload constant On Off Off Enable the accum_sload or sload_accum signals and the registers input to dynamically select the input to the accumulator. When accum_sload is low or sload_accum is high, the multiplier output is feed into the accumulator. When accum_sload is high or sload_accum is low, a user specified preload constant is feed into the accumulator. You must select YES for Enable accumulator parameter to enable this option. continued... 75

76 7 Intel FPGA Multiply Adder IP Core References Parameter Value Default Value Description What is the input of accumulate port connected to? ACCUM_SLOAD, SLOAD_ACCUM ACCUM_SLO AD Specifies the behavior of accum_sload/ sload_accum signal. ACCUM_SLOAD: Drive accum_sload low to load the multiplier output to the accumulator. SLOAD_ACCUM: Drive sload_accum high to load the multiplier output to the accumulator. You must select Enable preload constant option to enable this parameter. Select value for preload constant Specify the preset constant value. This value can be 2 N where N is the preset constant value. When N=64, it represents a constant zero. You must select Enable preload constant option to enable this parameter. What is the source for clock input? Clock0 Clock1 Clock2 Clock0 Select Clock0, Clock1 or Clock2 to specify the input clock signal for accum_sload/ sload_accum register. You must select Enable preload constant option to enable this parameter. What is the source for asynchronous clear input? ACLR0 ACLR1 Specifies the asynchronous clear source for the accum_sload/sload_accum register. You must select Enable preload constant option to enable this parameter. What is the source for synchronous clear input? SCLR0 SCLR1 Specifies the synchronous clear source for the accum_sload/sload_accum register. You must select Enable preload constant option to enable this parameter Systolic/Chainout Tab Table 36. Systolic/Chainout Adder Tab Parameter Value Default Value Description Enable chainout adder YES, NO Select YES to enable chainout adder module. NO What is the chainout adder operation type? ADD, SUB ADD Specifies the chainout adder operation. For subtraction operation, SIGNED must be selected for What is the representation format for s A inputs? and What is the representation format for s B inputs? in the s Tab. Enable negate input for chainout adder? PORT_USED, PORT_UNUSED PORT_UNUS ED Select PORT_USED to enable negate input signal. This parameter is invalid when chainout adder is disabled. negate input? UNREGISTERED, CLOCK0, CLOCK1, CLOCK2, CLOCK3 UNREGISTE RED To enable the input register for negate input signal and specifies the input clock signal for negate register. Select UNREGISTERED if the negate input register to is not needed This parameter is invalid when you select: NO for Enable chainout adder or PORT_UNUSED for Enable 'negate' input for chainout adder? parameter continued... 76

77 7 Intel FPGA Multiply Adder IP Core References Parameter Value Default Value Description What is the source for asynchronous clear input? ACLR0 ACLR1 Specifies the asynchronous clear source for the negate register. This parameter is invalid when you select: NO for Enable chainout adder or PORT_UNUSED for Enable 'negate' input for chainout adder? parameter What is the source for synchronous clear input? SCLR0 SCLR1 Specifies the synchronous clear source for the negate register. This parameter is invalid when you select: NO for Enable chainout adder or PORT_UNUSED for Enable 'negate' input for chainout adder? parameter Systolic Delay Enable systolic delay registers On Off Off Select this option to enable systolic mode. This parameter is available when you select 2, or 4 for What is the number of multipliers? parameter. You must enable the output of the adder unit to use the systolic delay registers. What is the source for clock input? CLOCK0, CLOCK1, CLOCK2, CLOCK0 Specifies the input clock signal for systolic delay register. You must select enable systolic delay registers to enable this option. What is the source for asynchronous clear input? ACLR0 ACLR1 Specifies the asynchronous clear source for the systolic delay register. You must select enable systolic delay registers to enable this option. What is the source for synchronous clear input? SCLR0 SCLR1 Specifies the synchronous clear source for the systolic delay register. You must select enable systolic delay registers to enable this option Pipelining Tab Table 37. Pipelining Tab Parameter IP Generated Parameter Value Default Value Description Pipelining Configuration Do you want to add pipeline register to the input? gui_pipelining No, Yes No Select Yes to enable an additional level of pipeline register to the input signals. You must specify a value greater than 0 for Please specify the number of latency clock cycles parameter. Please specify the number of latency clock cycles latency Any value greater than 0 0 Specifies the desired latency in clock cycles. One level of pipeline register = 1 latency in clock cycle. You must select YES for Do you want to add pipeline register to the input? to enable this option. continued... 77

78 7 Intel FPGA Multiply Adder IP Core References Parameter IP Generated Parameter Value Default Value Description What is the source for clock input? gui_input_late ncy_clock CLOCK0, CLOCK1, CLOCK2 CLOCK0 Select Clock0, Clock1 or Clock2 to enable and specify the pipeline register input clock signal. You must select YES for Do you want to add pipeline register to the input? to enable this option. What is the source for asynchronous clear input? gui_input_late ncy_aclr ACLR0 ACLR1 Specifies the register asynchronous clear source for the additional pipeline register. You must select YES for Do you want to add pipeline register to the input? to enable this option. What is the source for synchronous clear input? gui_input_late ncy_sclr SCLR0 SCLR1 Specifies the register synchronous clear source for the additional pipeline register. You must select YES for Do you want to add pipeline register to the input? to enable this option. 7.3 Signals The following tables list the input and output signals of the Intel FPGA Multiply Adder IP core. Table 38. Intel FPGA Multiply Adder Input Signals Signal Required Description dataa_0[]/dataa_1[]/ dataa_2[]/dataa_3[] datab_0[]/datab_1[]/ datab_2[]/datab_3[] datac_0[] /datac_1[]/ datac_2[]/datac_3[] Yes Data input to the multiplier. Input port [NUMBER_OF_MULTIPLIERS * WIDTH_A - 1 0] wide Yes Data input to the multiplier. Input signal [NUMBER_OF_MULTIPLIERS * WIDTH_B - 1 0] wide No Data input to the multiplier. Input signal [NUMBER_OF_MULTIPLIERS * WIDTH_C - 1 0] wide Select INPUT for Select preadder mode parameter to enable these signals. clock[1:0] No Clock input port to the corresponding register. This signal can be used by any register in the IP core. aclr[1:0] No Asynchronous clear input to the corresponding register. sclr[1:0] No Synchronous clear input to the corresponding register. ena[1:0] No Enable signal input to the corresponding register. signa No Specifies the numerical representation of the multiplier input A. If the signa signal is high, the multiplier treats the multiplier input A signal as a signed number. If the signa signal is low, the multiplier treats the multiplier input A signal as an unsigned number. Select VARIABLE for What is the representation format for s A inputs parameter to enable this signal. signb No Specifies the numerical representation of the multiplier input B signal. If the signb signal is high, the multiplier treats the multiplier input B signal as a signed two's complement number. If the signb signal is low, the multiplier treats the multiplier input B signal as an unsigned number. continued... 78

79 7 Intel FPGA Multiply Adder IP Core References Signal Required Description scanina[] No Input for scan chain A. Input signal [WIDTH_A ] wide. When the INPUT_SOURCE_A parameter has a value of SCANA, the scanina[] signal is required. accum_sload No Dynamically specifies whether the accumulator value is constant. If the accum_sload signal is low, then the multiplier output is loaded into the accumulator. Do not use accum_sload and sload_accum simultaneously. sload_accum No Dynamically specifies whether the accumulator value is constant. If the sload_accum signal is high, then the multiplier output is loaded into the accumulator. Do not use accum_sload and sload_accum simultaneously. chainin[] No Adder result input bus from the preceding stage. Input signal [WIDTH_CHAININ - 1 0] wide. addnsub1 No Perform addition or subtraction to the outputs from the first pair of multipliers. Input 1 to addnsub1 signal to add the outputs from the first pair of multipliers. Input 0 to addnsub1 signal to subtract the outputs from the first pair of multipliers. addnsub3 No Perform addition or subtraction to the outputs from the first pair of multipliers. Input 1 to addnsub3 signal to add the outputs from the second pair of multipliers. Input 0 to addnsub3 signal to subtract the outputs from the first pair of multipliers. coefsel0[] No Coefficient input signal[0..3] to the first multiplier. coefsel1[] No Coefficient input signal[0..3]to the second multiplier. coefsel2[] No Coefficient input signal[0..3]to the third multiplier. coefsel3[] No Coefficient input signal [0..3] to the fourth multiplier. Table 39. Intel FPGA Multiply Adder Output Signals Signal Required Description result [] Yes output signal. Output signal [WIDTH_RESULT - 1 0] wide scanouta [] No Output of scan chain A. Output signal [WIDTH_A ] wide. Select more than 2 for numbers of multipliers and choose Scan chain input for What is the input A of the multiplier connected to parameter to enable this signal. 79

80 8 ALTMULT_COMPLEX IP Core Reference You can use the ALTMULT_COMPLEX IP core to implement the complex multiplier by instantiating two multipliers. Figure 43. ALTMULT_COMPLEX Block Diagram dataa_real datab_real result_real dataa_imaginary datab_imaginary dataa_real datab_imaginary datab_real result_imaginary dataa_imaginary Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 ed

81 8 ALTMULT_COMPLEX IP Core Reference 8.1 Features The ALTMULT_COMPLEX IP core offers the following features: Generates a multiplier to perform multiplication operations of two complex numbers Note: When building multipliers larger than the natively supported size there may/ will be a performance impact resulting from the partial products calculations.. Supports data width of bits Supports signed and unsigned data representation format Supports pipelining with configurable output latency Supports optional asynchronous and synchronous clear and clock enable input ports 8.2 Complex Multiplication Complex numbers are numbers in the form of the following equation: a + ib Where: a and b are real numbers i is an imaginary unit that equals the square root of -1. Two complex numbers, x = a + ib and y = c + id are multiplied, as shown in the following equations. Figure 44. Equation for Two Complex Numbers Multiplication 8.3 Parameters Table 40. ALTMULT_COMPLEX Parameters Parameter Value Default Value Description General How wide should the A input buses be? How wide should the B input buses be? How wide should the result output bus be? Input Representation Specifies the number of bits for dataa_imag and dataa_real input buses Specifies the number of bits for datab_imag and datab_real input buses Specifies the number of bits for result output bus. continued... 81

82 8 ALTMULT_COMPLEX IP Core Reference Parameter Value Default Value Description What is the representation format for A inputs? Signed, Unsigned Signed Specifies the representation format for A inputs. Only Signed representation format is supported in Intel Stratix 10 devices. What is the representation format for B inputs? Signed, Unsigned Signed Specifies the representation format for B inputs. Only Signed representation format is supported in Intel Stratix 10 devices. Implementation Style Which implementation style should be used? Automatically select a style for best trade-off for the current settings Canonical. (Minimize the number of simple multipliers) Conventional. (Minimize the use of logic cells) Automaticall y select a style for best tradeoff for the current settings Intel Stratix 10 device supports only Automatically select a style for best tradeoff for the current settings style. Intel Quartus Prime software will determine the best implementation based on the selected device family and input width. Pipelining Output latency Specifies the number of clock cycles for output latency. Create a Clear input? ACLR Select this option to create aclr or sclr signal for the complex multiplier. SCLR Create a Clock Enable input? On Off Off Select this option to create ena signal for the complex multiplier clock. 8.4 Signals Table 41. ALTMULT_COMPLEX Input Signals Signal Required Description aclr No Asynchronous clear for the complex multiplier. When the aclr signal is asserted high, the function is asynchronously cleared. sclr No Synchronous clear for the complex multiplier. When the sclr signal is asserted high, the function is asynchronously cleared. clock Yes Clock input to the ALTMULT_COMPLEX function. dataa_imag[] Yes Imaginary input value for the data A signal of the complex multiplier. The size of the input signal depends on the WIDTH_A parameter value. dataa_real[] Yes Real input value for the data A signal of the complex multiplier. The size of the input signal depends on the WIDTH_A parameter value. datab_imag[] Yes Imaginary input value for the data B signal of the complex multiplier. The size of the input signal depends on the WIDTH_B parameter value. continued... 82

83 8 ALTMULT_COMPLEX IP Core Reference Signal Required Description datab_real[] Yes Real input value for the data B signal of the complex multiplier. The size of the input signal depends on the WIDTH_B parameter value. ena No Active high clock enable for the clock signal of the complex multiplier. complex No Optional input to enable dynamic switching between normal model and complex mode. This input is only available in Stratix V devices. In the GUI, this parameter is referred as Dynamic Complex Mode. Table 42. ALTMULT_COMPLEX Output Signals Signal Required Description result_imag Yes Imaginary output value of the multiplier. The size of the output signal depends on the WIDTH_RESULT parameter value. result_real Yes Real output value of the multiplier. The size of the output signal depends on the WIDTH_RESULT parameter value. 83

84 9 LPM_MULT () IP Core References The LPM_MULT IP core implements a multiplier to multiply two input data values to produce a product as an output. Figure 45. LPM_MULT IP Core Architecture dataa[] datab[] aclr/sclr clken clock result[] 9.1 Features 9.2 Parameters The LPM_MULT IP core offers the following features: Generates a multiplier that multiplies two input data values Supports data width of bits Supports signed and unsigned data representation format Supports area or speed optimization Supports pipelining with configurable output latency Provides an option for implementation in dedicated digital signal processing (DSP) block circuitry or logic elements (LEs) Note: When building multipliers larger than the natively supported size there may/ will be a performance impact resulting from the cascading of the DSP blocks. Supports optional asynchronous and synchronous clear and clock enable input ports You can customize the Intel Stratix 10 LPM_MULT IP core by specifying the parameters using the IP Parameter Editor in the Intel Quartus Prime software. Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 ed

85 9 LPM_MULT () IP Core References General Tab Table 43. General Tab Parameter Value Default Value Description Configuration Type Multiply 'dataa' input by 'datab' input Multiply 'dataa' input by itself (squaring operation) Multiply 'dataa' input by 'datab' input Select the desired configuration for the multiplier. Data Port Widths Dataa width bits 8 bits Specify the width of the dataa[] port. Datab width bits 8 bits Specify the width of the datab[] port. How should the width of the 'result' output be determined? Type Automatically calculate the width Restrict the width Automaticall y calculate the width Select the desired method to determine the width of the result[] port. Value bits 16 bits Specify the width of the result[] port. This value will only be effective if you select Restrict the width in the Type parameter. Result width bits Displays the effective width of the result[] port General 2 Tab Table 44. General 2 Tab Datab Input Parameter Value Default Value Description Does the 'datab' input bus have a constant value? No Yes No Select Yes to specify the constant value of the datab input bus, if any. Value Multiplication Type Any value greater than 0 0 Specify the constant value of datab[] port. Which type of multiplication do you want? Unsigned Signed Unsigned Specify the representation format for both dataa[] and datab[] inputs. Implementation Style Which multiplier implementation should be used? Use the default implementation Use the dedicated multiplier circuitry (Not available for all families) Use logic elements Use the default implementat ion Select the desired method to determine the width of the result[] port. When SCLR is selected for Clear Signal Type parameter, only Use the dedicated multiplier circuitry (Not available for all families) option is available. 85

86 9 LPM_MULT () IP Core References Pipelining Tab Table 45. Pipelining Tab Parameter Value Default Value Description Do you want to pipeline the function? Pipeline No Yes No Select Yes to enable pipeline register to the multiplier's output. Enabling the pipeline register adds extra latency to the output. Latency Any value greater than 0. 1 Specify the desired output latency in clock cycle. Clear Signal Type ACLR SCLR Specify the type of reset for the pipeline register. Select if you do not use any pipeline register. Select ACLR to use asynchronous clear for the pipeline register. This generates ACLR port. Select SCLR to use synchronous clear for the pipeline register. This generates SCLR port. Create a 'clken' clock enable clock Off On Off Specifies active high clock enable for the clock port of the pipeline register What type of optimization do you want? Type Default Speed Area Default Specify the desired optimization for the IP core. Select Default to let Intel Quartus Prime software to determine the best optiomization for the IP core. 9.3 Signals Table 46. LPM_MULT Input Signals Signal Name Required Description dataa[] Yes Data input. The size of the input signal depends on the Dataa width parameter value. datab[] Yes Data input. The size of the input signal depends on the Datab width parameter value. clock No Clock input for pipelined usage. For Latency values other than 1 (default), the clock signal must be enabled. clken No Clock enable for pipelined usage. When the clken signal is asserted high, the adder/subtractor operation takes place. When the signal is low, no operation occurs. If omitted, the default value is 1. aclr No Asynchronous clear signal used at any time to reset the pipeline to all 0s, asynchronously to the clock signal. The pipeline initializes to an undefined (X) logic level. The outputs are a consistent, but non-zero value. sclr No Synchronous clear signal used at any time to reset the pipeline to all 0s, synchronously to the clock signal. The pipeline initializes to an undefined (X) logic level. The outputs are a consistent, but non-zero value. Table 47. LPM_MULT Output signals signal Name Required Description result[] Yes Data output. 86

87 9 LPM_MULT () IP Core References signal Name Required Description The size of the output signals depends on the Result width parameter. 87

88 10 Intel Stratix 10 Native Floating Point DSP IP References The Intel Stratix 10 Native Floating Point DSP Intel FPGA IP instantiates and controls a single Intel Stratix 10 Variable Precision DSP block. Related Links Block Architecture Overview on page 9 More information related to functional blocks in Intel Stratix 10 Floating-Point DSP IP core Intel Stratix 10 Native Floating Point DSP IP Core Supported Operational Modes Table 48. Operational Modes Supported by Intel Stratix 10 Native Floating Point DSP IP Core Operational Modes Description Supported Exception Flags Multiply mode Add mode Multiply Add mode Multiply Accumulate mode This mode performs single precision multiplication operation. This mode applies the following equation: Out = Ay * Az This mode performs single precision addition or subtraction operation. This mode applies the following equations: Out = Ay + Ax Out = Ay - Ax This mode performs single precision multiplication, followed by addition or subtraction operations. This mode applies the following equations: Out = (Ay * Az) - chainin Out = (Ay * Az) + chainin Out = (Ay * Az) - Ax Out = (Ay * Az) + Ax This mode performs floating-point multiplication followed by floating-point addition or subtraction with the previous multiplication result. This mode applies the following equations: mult_overflow mult_underflow mult_inexact mult_invalid adder_overflow adder_underflow adder_inexact adder_invalid mult_overflow mult_underflow mult_inexact mult_invalid adder_overflow adder_underflow adder_inexact adder_invalid continued... Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 ed

89 10 Intel Stratix 10 Native Floating Point DSP IP References Operational Modes Description Supported Exception Flags Out(t) = [Ay(t) * Az(t)] - Out (t-1) when accumulate signal is driven high. Out(t) = [Ay(t) * Az(t)] + Out (t-1) when accumulate port is driven high. Out(t) = Ay(t) * Az(t) when accumulate port is driven low. Vector Mode 1 Vector Mode 2 This mode performs floating-point multiplication followed by floating-point addition or subtraction with the chainin input from the previous variable DSP Block. This mode applies the following equations: Out = (Ay * Az) - chainin, chainout = Ax Out = (Ay * Az) + chainin, chainout = Ax Out = (Ay * Az), chainout = Ax This mode performs floating-point multiplication where the multiplication result is directly fed to chainout. The chainin input from the previous variable DSP Block is then added or subtracted from input Ax as the output result. This mode applies the following equations: Out = Ax - chainin, chainout = Ay * Az Out = Ax + chainin, chainout = Ay * Az Out = Ax, chainout = Ay * Az Related Links Single Floating-Point Arithmetic Functions on page 29 Multiple Floating-Point Arithmetic Functions on page Parameterizing the Intel Stratix 10 Native Floating-Point DSP Intel FPGA IP Select different parameters to create an IP core suitable for your design. 1. In Intel Quartus Prime Pro Edition,create a new project that targets a Intel Stratix 10 device. 2. In IP Catalog, click Library DSP Primitive DSP Intel Stratix 10 Native Floating Point DSP. The Intel Stratix 10 Native Floating-Point DSP IP Core IP parameter editor opens. 3. In the New IP Variation dialog box, enter an Entity Name and click OK. 4. Under Parameters, select the DSP Template and the View you want for your IP core 5. In the DSP Block View, switch the clock or reset of each valid register. 6. For Multiply Add or Vector Mode 1, click the Chain In multiplexer in the GUI to select input from chainin port or Ax port. 7. Click the Adder symbol in the GUI to select addition or subtraction. 8. Click the Chain Out multiplexer in the GUI to enable chainout port. 9. Click Generate HDL. 10. Click Finish. 89

90 10 Intel Stratix 10 Native Floating Point DSP IP References Intel Stratix 10 Native Floating-Point DSP Intel FPGA IP Parameters Table 49. Parameters Parameter Value Default Value Description DSP Template Multiply Add Multiply Add Multiply Accumulate Multiply Select the desired operational mode for the DSP block. The selected operation is reflected in the DSP Block View. Vector Mode 1 Vector Mode 2 View Enables Clears Enables Options to select clocking scheme or reset scheme for registers view. The selected operation is reflected in the DSP Block View. Select Enables for DSP Block View to show registers clocking scheme. You can change the clocks for each of the registers in this view. Select Clears for DSP Block View to show registers reset scheme. Turn on Use Single Clear to change the registers reset scheme. Clear Type None Synchronous Options to select reset type for all registers. Synchronous Asynchronous Select None to not reset the registers. Select Synchronous use synchronous clear signal type for all registers. Select Asynchronous to use asynchronous clear signal type for all registers. Single Clear On or off Off Turn on this parameter if you want a single reset to reset all the registers in the DSP block. Turn off this parameter to use different reset ports to reset the registers. This parameter is disable when you select None for Clear Type. Connect Exception Flags On Off Off Click this parameter to use and generate exception flags output ports for the DSP block. When you turn off this parameter, the IP core does not generate exception flags output ports. DSP View Block. Chain In Multiplexer (1) Enable Disable Disable Click the multiplexer to enable chainin port. Chain Out Multiplexer (2) Disable Enable Disable Click the multiplexer to enable chainout port. Adder (3) Click the Adder symbol to select addition or subtraction mode. Clock (4) None Clock 0 Clock 1 Clock 2 Clock 0 To bypass any register, switch the register clock to None. Switch the register clock to: Clock 0 to use clk[0] signal as the clock source Clock 1 to use clk[1] signal as the clock source Clock 2 to use clk[2] signal as the clock source continued... 90

91 10 Intel Stratix 10 Native Floating Point DSP IP References Parameter Value Default Value Description You can only change these settings when you select Enables in View parameter. Clear (4) Clear 0 Clear 1 Clear 0 for input registers Clear 1 for output and pipeline registers This view shows the IP core reset scheme. Clear 0 uses clr[0] signal. Clear 1 uses clr[1] signal. All input registers use clr[0] reset signal. All output and pipeline registers use clr[1] reset signal. Figure 46. DSP View Block 91

Intel Arria 10 Native Fixed Point DSP IP Core User Guide

Intel Arria 10 Native Fixed Point DSP IP Core User Guide Intel Arria 0 Native Fixed Point DSP IP Core User Guide UG-06 207.0. Subscribe Send Feedback Contents Contents Intel Arria Native Fixed Point DSP IP Core User Guide.... Arria 0 Native Fixed Point DSP IP

More information

Intel Arria 10 Native Floating- Point DSP Intel FPGA IP User Guide

Intel Arria 10 Native Floating- Point DSP Intel FPGA IP User Guide Intel Arria 10 Native Floating- Point DSP Intel FPGA IP User Guide Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1...3 1.1 Parameterizing the Intel Arria 10 Native Floating-Point

More information

Intel Stratix 10 Logic Array Blocks and Adaptive Logic Modules User Guide

Intel Stratix 10 Logic Array Blocks and Adaptive Logic Modules User Guide Intel Stratix 10 Logic Array Blocks and Adaptive Logic Modules User Guide Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Intel Stratix 10 LAB and Overview... 3 2 HyperFlex

More information

4. DSP Blocks in Stratix IV Devices

4. DSP Blocks in Stratix IV Devices 4. DSP Blocks in Stratix IV Devices February 2011 SIV51004-3.1 SIV51004-3.1 This chapter describes how the Stratix IV device digital signal processing (DSP) blocks are optimized to support DSP applications

More information

Intel Stratix 10 Analog to Digital Converter User Guide

Intel Stratix 10 Analog to Digital Converter User Guide Intel Stratix 10 Analog to Digital Converter User Guide Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Intel Stratix

More information

Altera ASMI Parallel II IP Core User Guide

Altera ASMI Parallel II IP Core User Guide Altera ASMI Parallel II IP Core User Guide UG-20068 2017.05.08 Last updated for Intel Quartus Prime Design Suite: 17.0 Subscribe Send Feedback Contents Contents 1... 3 1.1 Ports...4 1.2 Parameters... 5

More information

ASMI Parallel II Intel FPGA IP Core User Guide

ASMI Parallel II Intel FPGA IP Core User Guide ASMI Parallel II Intel FPGA IP Core User Guide Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1.... 3 1.1. Ports...4 1.2.

More information

High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example User Guide

High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example User Guide High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Updated for Intel Quartus Prime Design Suite: 18.1.1 Subscribe Latest document on the web: PDF HTML Contents Contents 1. High Bandwidth

More information

Intel Acceleration Stack for Intel Xeon CPU with FPGAs 1.0 Errata

Intel Acceleration Stack for Intel Xeon CPU with FPGAs 1.0 Errata Intel Acceleration Stack for Intel Xeon CPU with FPGAs 1.0 Errata Updated for Intel Acceleration Stack for Intel Xeon CPU with FPGAs: 1.0 Production Subscribe Send Feedback Latest document on the web:

More information

Nios II Custom Instruction User Guide

Nios II Custom Instruction User Guide Nios II Custom Instruction User Guide Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Nios II Custom Instruction Overview...4 1.1 Custom Instruction Implementation... 4

More information

AN 464: DFT/IDFT Reference Design

AN 464: DFT/IDFT Reference Design Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents About the DFT/IDFT Reference Design... 3 Functional Description for the DFT/IDFT Reference Design... 4 Parameters for the

More information

Interlaken IP Core (2nd Generation) Design Example User Guide

Interlaken IP Core (2nd Generation) Design Example User Guide Interlaken IP Core (2nd Generation) Design Example User Guide UG-20051 2017.09.19 Subscribe Send Feedback Contents Contents 1 Quick Start Guide... 3 1.1 Directory Structure... 4 1.2 Design Components...

More information

Timing Analyzer Quick-Start Tutorial

Timing Analyzer Quick-Start Tutorial Timing Analyzer Quick-Start Tutorial Intel Quartus Prime Pro Edition Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents Timing

More information

Intel Quartus Prime Software Download and Installation Quick Start Guide

Intel Quartus Prime Software Download and Installation Quick Start Guide Intel Quartus Prime Software Download and Installation Quick Start Guide Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus, and Stratix

More information

Intel Xeon with FPGA IP Asynchronous Core Cache Interface (CCI-P) Shim

Intel Xeon with FPGA IP Asynchronous Core Cache Interface (CCI-P) Shim Intel Xeon with FPGA IP Asynchronous Core Cache Interface (CCI-P) Shim AN-828 2017.10.02 Subscribe Send Feedback Contents Contents 1... 3 1.1 Conventions...3 1.2 Glossary...3 1.3 Introduction...3 1.4 Design...

More information

Using the DSP Blocks in Stratix & Stratix GX Devices

Using the DSP Blocks in Stratix & Stratix GX Devices Using the SP Blocks in Stratix & Stratix GX evices November 2002, ver. 3.0 Application Note 214 Introduction Traditionally, designers had to make a trade-off between the flexibility of off-the-shelf digital

More information

Intel FPGA Integer Arithmetic IP Cores User Guide

Intel FPGA Integer Arithmetic IP Cores User Guide Intel FPGA Integer Arithmetic IP Cores User Guide Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Intel FPGA Integer

More information

Stratix 10 Serial Flash Mailbox Client Intel FPGA IP Core User Guide

Stratix 10 Serial Flash Mailbox Client Intel FPGA IP Core User Guide Stratix 10 Serial Flash Mailbox Client Intel FPGA IP Core User Guide Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents...3

More information

Intel Quartus Prime Pro Edition Software and Device Support Release Notes

Intel Quartus Prime Pro Edition Software and Device Support Release Notes Intel Quartus Prime Pro Edition Software and Device Support Release Notes Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Version 17.1... 3 1.1 New Features and Enhancements...3

More information

Intel Quartus Prime Pro Edition Software and Device Support Release Notes

Intel Quartus Prime Pro Edition Software and Device Support Release Notes Intel Quartus Prime Pro Edition Software and Device Support Release Notes Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1. Version 18.0... 3 1.1. New Features and Enhancements...3

More information

Implementing FIR Filters

Implementing FIR Filters Implementing FIR Filters in FLEX Devices February 199, ver. 1.01 Application Note 73 FIR Filter Architecture This section describes a conventional FIR filter design and how the design can be optimized

More information

Intel Stratix 10 H-tile Hard IP for Ethernet Design Example User Guide

Intel Stratix 10 H-tile Hard IP for Ethernet Design Example User Guide Intel Stratix 10 H-tile Hard IP for Ethernet Design Example User Guide Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents

More information

Intel FPGA Voltage Sensor IP Core User Guide

Intel FPGA Voltage Sensor IP Core User Guide Intel FPGA Voltage Sensor IP Core User Guide Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Intel FPGA Voltage Sensor

More information

Intel FPGA Temperature Sensor IP Core User Guide

Intel FPGA Temperature Sensor IP Core User Guide Intel FPGA Temperature Sensor IP Core User Guide UG-01074 2017.09.14 Subscribe Send Feedback Contents Contents... 3 Intel FPGA Temperature Sensor Features...3 Intel FPGA Temperature Sensor Functional Description...

More information

Generic Serial Flash Interface Intel FPGA IP Core User Guide

Generic Serial Flash Interface Intel FPGA IP Core User Guide Generic Serial Flash Interface Intel FPGA IP Core User Guide Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1. Generic

More information

Intel Stratix 10 H-Tile PCIe Link Hardware Validation

Intel Stratix 10 H-Tile PCIe Link Hardware Validation Intel Stratix 10 H-Tile PCIe Link Hardware Validation Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1. Intel Stratix 10 H-Tile PCIe* Link Hardware Validation... 3 1.1.

More information

Intel Stratix 10 Clocking and PLL User Guide

Intel Stratix 10 Clocking and PLL User Guide Intel Stratix 10 Clocking and PLL User Guide Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1. Intel Stratix 10 Clocking

More information

Intel MAX 10 User Flash Memory User Guide

Intel MAX 10 User Flash Memory User Guide Intel MAX 10 User Flash Memory User Guide Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1. Intel MAX 10 User Flash Memory

More information

Intel Quartus Prime Pro Edition Software and Device Support Release Notes

Intel Quartus Prime Pro Edition Software and Device Support Release Notes Intel Quartus Prime Pro Edition Software and Device Support Release Notes RN-01082-17.0.0 2017.05.08 Subscribe Send Feedback Contents Contents 1 Version 17.0... 3 1.1 New Features and Enhancements...3

More information

Intel Cyclone 10 External Memory Interfaces IP Design Example User Guide

Intel Cyclone 10 External Memory Interfaces IP Design Example User Guide Intel Cyclone 10 External Memory Interfaces IP Design Example User Guide Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents

More information

AN 834: Developing for the Intel HLS Compiler with an IDE

AN 834: Developing for the Intel HLS Compiler with an IDE AN 834: Developing for the Intel HLS Compiler with an IDE Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Developing for the Intel HLS Compiler with an Eclipse* IDE...

More information

Customizable Flash Programmer User Guide

Customizable Flash Programmer User Guide Customizable Flash Programmer User Guide Subscribe Latest document on the web: PDF HTML Contents Contents 1. Customizable Flash Programmer Overview... 3 1.1. Device Family Support...3 1.2. Software Support...

More information

Intel Stratix 10 Low Latency 40G Ethernet Design Example User Guide

Intel Stratix 10 Low Latency 40G Ethernet Design Example User Guide Intel Stratix 10 Low Latency 40G Ethernet Design Example User Guide Updated for Intel Quartus Prime Design Suite: 18.1 Subscribe Latest document on the web: PDF HTML Contents Contents 1. Quick Start Guide...

More information

Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide

Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide UG-01155 2017.06.16 Last updated for Intel Quartus Prime Design Suite: 17.0 Subscribe Send Feedback Contents Contents...3 Device Family Support...

More information

Remote Update Intel FPGA IP User Guide

Remote Update Intel FPGA IP User Guide Remote Update Intel FPGA IP User Guide Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Latest document on the web: PDF HTML Contents Contents 1. Remote Update Intel FPGA IP User Guide... 3

More information

Enabling Impactful DSP Designs on FPGAs with Hardened Floating-Point Implementation

Enabling Impactful DSP Designs on FPGAs with Hardened Floating-Point Implementation white paper FPGA Enabling Impactful DSP Designs on FPGAs with Hardened Floating-Point Implementation Hardened floating-point DSP implementations enable algorithmic performance and faster time to market

More information

External Memory Interfaces Intel Arria 10 FPGA IP Design Example User Guide

External Memory Interfaces Intel Arria 10 FPGA IP Design Example User Guide External Memory Interfaces Intel Arria 10 FPGA IP Design Example User Guide Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents

More information

AN 839: Design Block Reuse Tutorial

AN 839: Design Block Reuse Tutorial AN 839: Design Block Reuse Tutorial for Intel Arria 10 FPGA Development Board Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents

More information

PCI Express Multi-Channel DMA Interface

PCI Express Multi-Channel DMA Interface 2014.12.15 UG-01160 Subscribe The PCI Express DMA Multi-Channel Controller Example Design provides multi-channel support for the Stratix V Avalon Memory-Mapped (Avalon-MM) DMA for PCI Express IP Core.

More information

SerialLite III Streaming IP Core Design Example User Guide for Intel Arria 10 Devices

SerialLite III Streaming IP Core Design Example User Guide for Intel Arria 10 Devices IP Core Design Example User Guide for Intel Arria 10 Devices Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Quick Start

More information

Intel Quartus Prime Pro Edition

Intel Quartus Prime Pro Edition Intel Quartus Prime Pro Edition Version 18.1 Software and Device Support Release Notes Subscribe Latest document on the web: PDF HTML Contents Contents 1. Intel Quartus Prime Pro Edition Version 18.1 Software

More information

Parallel FIR Filters. Chapter 5

Parallel FIR Filters. Chapter 5 Chapter 5 Parallel FIR Filters This chapter describes the implementation of high-performance, parallel, full-precision FIR filters using the DSP48 slice in a Virtex-4 device. ecause the Virtex-4 architecture

More information

Leveraging the Intel HyperFlex FPGA Architecture in Intel Stratix 10 Devices to Achieve Maximum Power Reduction

Leveraging the Intel HyperFlex FPGA Architecture in Intel Stratix 10 Devices to Achieve Maximum Power Reduction white paper FPGA Leveraging the Intel HyperFlex FPGA Architecture in Intel Stratix 1 s to Achieve Maximum Reduction devices leverage the innovative Intel HyperFlex FPGA architecture to achieve power savings

More information

Low Latency 100G Ethernet Design Example User Guide

Low Latency 100G Ethernet Design Example User Guide Low Latency 100G Ethernet Design Example User Guide Updated for Intel Quartus Prime Design Suite: 16.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Quick Start Guide...

More information

Nios II Embedded Design Suite Release Notes

Nios II Embedded Design Suite Release Notes Nios II Embedded Design Suite Release Notes Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1...3 1.1 Product Revision History... 3 1.2 Nios II EDS v15.0 Updates...4 1.3

More information

Intel Stratix 10 External Memory Interfaces IP Design Example User Guide

Intel Stratix 10 External Memory Interfaces IP Design Example User Guide Intel Stratix 10 External Memory Interfaces IP Design Example User Guide Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents

More information

AN 830: Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design

AN 830: Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design AN 830: Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Intel FPGA Triple-Speed Ethernet and On-Board

More information

SerialLite III Streaming IP Core Design Example User Guide for Intel Stratix 10 Devices

SerialLite III Streaming IP Core Design Example User Guide for Intel Stratix 10 Devices SerialLite III Streaming IP Core Design Example User Guide for Intel Stratix 10 Devices Updated for Intel Quartus Prime Design Suite: 17.1 Stratix 10 ES Editions Subscribe Send Feedback Latest document

More information

Nios II Performance Benchmarks

Nios II Performance Benchmarks Subscribe Performance Benchmarks Overview This datasheet lists the performance and logic element (LE) usage for the Nios II Classic and Nios II Gen2 soft processor, and peripherals. Nios II is configurable

More information

AN 825: Partially Reconfiguring a Design on Intel Stratix 10 GX FPGA Development Board

AN 825: Partially Reconfiguring a Design on Intel Stratix 10 GX FPGA Development Board AN 825: Partially Reconfiguring a Design on Intel Stratix 10 GX FPGA Updated for Intel Quartus Prime Design Suite: 18.1 Subscribe Latest document on the web: PDF HTML Contents Contents Partially Reconfiguring

More information

Low Latency 40G Ethernet Example Design User Guide

Low Latency 40G Ethernet Example Design User Guide Low Latency 40G Ethernet Example Design User Guide Subscribe UG-20025 101 Innovation Drive San Jose, CA 95134 www.altera.com TOC-2 Contents Quick Start Guide...1-1 Directory Structure... 1-2 Design Components...

More information

Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide

Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents

More information

Design Guidelines for Using DSP Blocks

Design Guidelines for Using DSP Blocks Design Guidelines for Using DSP Blocks in the LeonardoSpectrum Software April 2002, ver. 1.0 Application Note 194 Introduction Altera R Stratix TM devices have dedicated digital signal processing (DSP)

More information

Intel HLS Compiler: Fast Design, Coding, and Hardware

Intel HLS Compiler: Fast Design, Coding, and Hardware white paper Intel HLS Compiler Intel HLS Compiler: Fast Design, Coding, and Hardware The Modern FPGA Workflow Authors Melissa Sussmann HLS Product Manager Intel Corporation Tom Hill OpenCL Product Manager

More information

Memory Optimization for OpenCL on Intel FPGAs Exercise Manual

Memory Optimization for OpenCL on Intel FPGAs Exercise Manual Memory Optimization for OpenCL on Intel FPGAs Exercise Manual Software Requirements that cannot be adjusted: Intel FPGA SDK for OpenCL version 17.1 Software Requirements that can be adjusted: Operation

More information

AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines

AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines AN-756 2017.05.08 Subscribe Send Feedback Contents Contents 1...3 1.1 Implementing the Altera PHYLite Design... 3 1.1.1 Parameter

More information

AN 447: Interfacing Intel FPGA Devices with 3.3/3.0/2.5 V LVTTL/ LVCMOS I/O Systems

AN 447: Interfacing Intel FPGA Devices with 3.3/3.0/2.5 V LVTTL/ LVCMOS I/O Systems AN 447: Interfacing Intel FPGA Devices with 3.3/3.0/2.5 V LVTTL/ LVCMOS I/O Systems Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents Interfacing Intel FPGA Devices with 3.3/3.0/2.5

More information

Intel Accelerator Functional Unit (AFU) Simulation Environment (ASE) Quick Start User Guide

Intel Accelerator Functional Unit (AFU) Simulation Environment (ASE) Quick Start User Guide Intel Accelerator Functional Unit (AFU) Simulation Environment (ASE) Quick Start User Guide Updated for Intel Acceleration Stack: 1.0 Production Subscribe Send Feedback Latest document on the web: PDF

More information

AN 830: Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design

AN 830: Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design AN 830: Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Subscribe Latest document on the web: PDF HTML Contents Contents 1. Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference

More information

Quad-Serial Configuration (EPCQ) Devices Datasheet

Quad-Serial Configuration (EPCQ) Devices Datasheet Quad-Serial Configuration (EPCQ) Devices Datasheet Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1...4 1.1 Supported Devices...4 1.2 Features...5 1.3 Operating Conditions...5

More information

1. Device Interfaces and Integration Basics for Cyclone V Devices

1. Device Interfaces and Integration Basics for Cyclone V Devices November 2011 CV-55001-1.1 1. Device Interfaces and Integration Basics for Cyclone V Devices CV-55001-1.1 This chapter contains basic information of specific feature in the Cyclone V device interfaces

More information

25G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide

25G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide 25G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1. 25G

More information

AN 831: Intel FPGA SDK for OpenCL

AN 831: Intel FPGA SDK for OpenCL AN 831: Intel FPGA SDK for OpenCL Host Pipelined Multithread Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Intel FPGA SDK for OpenCL Host Pipelined Multithread...3 1.1

More information

Quick Start Guide for Intel FPGA Development Tools on the Nimbix Cloud

Quick Start Guide for Intel FPGA Development Tools on the Nimbix Cloud Quick Start Guide for Intel FPGA Development Tools on the Nimbix Cloud Updated for Intel Quartus Prime Design Suite: 17.0.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents

More information

Intel FPGA USB Download Cable User Guide

Intel FPGA USB Download Cable User Guide Intel FPGA USB Download Cable User Guide Subscribe Latest document on the web: PDF HTML Contents Contents 1. Introduction to Intel FPGA Download Cable...3 1.1. Intel FPGA Download Cable Revision... 3 1.2.

More information

AN 836: RapidIO II Reference Design for Avalon-ST Pass-Through Interface

AN 836: RapidIO II Reference Design for Avalon-ST Pass-Through Interface AN 836: RapidIO II Reference Design for Avalon-ST Pass-Through Interface Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 RapidIO II Reference Design for Avalon -ST Pass-Through

More information

AN 825: Partially Reconfiguring a Design on Intel Stratix 10 GX FPGA Development Board

AN 825: Partially Reconfiguring a Design on Intel Stratix 10 GX FPGA Development Board AN 825: Partially Reconfiguring a Design on Intel Stratix 10 GX FPGA Development Board Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents

More information

Intel Cyclone 10 LP Device Family Pin Connection Guidelines

Intel Cyclone 10 LP Device Family Pin Connection Guidelines Intel Cyclone 10 LP Device Family Pin Connection Guidelines Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents... 3 Intel Cyclone 10 LP Pin Connection Guidelines...4 Clock and

More information

Mailbox Client Intel Stratix 10 FPGA IP Core User Guide

Mailbox Client Intel Stratix 10 FPGA IP Core User Guide Mailbox Client Intel Stratix 10 FPGA IP Core User Guide Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1.1 Feature Description...3 1.2 Command & Error Code...4 1.2.1 Commands...

More information

Intel Arria 10 and Intel Cyclone 10 Avalon -MM Interface for PCIe* Design Example User Guide

Intel Arria 10 and Intel Cyclone 10 Avalon -MM Interface for PCIe* Design Example User Guide Intel Arria 10 and Intel Cyclone 10 Avalon -MM Interface for PCIe* Design Example User Guide Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Quick Start Guide... 3 1.1

More information

AN 797: Partially Reconfiguring a Design on Intel Arria 10 GX FPGA Development Board

AN 797: Partially Reconfiguring a Design on Intel Arria 10 GX FPGA Development Board AN 797: Partially Reconfiguring a Design on Intel Arria 10 GX FPGA Updated for Intel Quartus Prime Design Suite: 18.1 Subscribe Latest document on the web: PDF HTML Contents Contents Partially Reconfiguring

More information

AN 779: Intel FPGA JESD204B IP Core and ADI AD9691 Hardware Checkout Report

AN 779: Intel FPGA JESD204B IP Core and ADI AD9691 Hardware Checkout Report AN 779: Intel FPGA JESD204B IP Core and ADI AD9691 Hardware Checkout Report Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Intel FPGA JESD204B IP Core and AD9691 Hardware

More information

Intel Acceleration Stack for Intel Xeon CPU with FPGAs Version 1.2 Release Notes

Intel Acceleration Stack for Intel Xeon CPU with FPGAs Version 1.2 Release Notes Intel Acceleration Stack for Intel Xeon CPU with FPGAs Version 1.2 Updated for Intel Acceleration Stack for Intel Xeon CPU with FPGAs: 1.2 Subscribe Latest document on the web: PDF HTML Contents Contents

More information

AN 829: PCI Express* Avalon -MM DMA Reference Design

AN 829: PCI Express* Avalon -MM DMA Reference Design AN 829: PCI Express* Avalon -MM DMA Reference Design Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Latest document on the web: PDF HTML Contents Contents 1....3 1.1. Introduction...3 1.1.1.

More information

Arria 10 Transceiver PHY User Guide

Arria 10 Transceiver PHY User Guide Arria 10 Transceiver PHY User Guide Subscribe UG-A10XCVR 101 Innovation Drive San Jose, CA 95134 www.altera.com TOC-2 Arria 10 Transceiver PHY User Guide Contents Arria 10 Transceiver PHY Overview...1-1

More information

H-tile Hard IP for Ethernet Intel Stratix 10 FPGA IP Design Example User Guide

H-tile Hard IP for Ethernet Intel Stratix 10 FPGA IP Design Example User Guide H-tile Hard IP for Ethernet Intel Stratix 10 FPGA IP Design Example User Guide Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents

More information

Intel MAX 10 Embedded Memory User Guide

Intel MAX 10 Embedded Memory User Guide Intel MAX 10 Embedded Memory User Guide Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1. Intel MAX 10 Embedded Memory Overview...4 2. Intel MAX 10 Embedded Memory Architecture

More information

AN 818: Static Update Partial Reconfiguration Tutorial

AN 818: Static Update Partial Reconfiguration Tutorial AN 818: Static Update Partial Reconfiguration Tutorial for Intel Stratix 10 GX FPGA Development Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF

More information

3. ALTGX_RECONFIG IP Core User Guide for Stratix IV Devices

3. ALTGX_RECONFIG IP Core User Guide for Stratix IV Devices July 2014 SIV53004-2014.07.09 3. ALTGX_RECONFIG IP Core User Guide for Stratix IV Devices SIV53004-2014.07.09 This document describes how to define and instantiate the ALTGX_RECONFIG IP core using the

More information

ALTERA_CORDIC IP Core User Guide

ALTERA_CORDIC IP Core User Guide UG-20017 2017.05.08 Subscribe Send Feedback Contents Contents 1... 3 1.1 ALTERA_CORDIC IP Core Features... 3 1.2 DSP IP Core Device Famil Support...3 1.3 ALTERA_CORDIC IP Core Functional Description...4

More information

Design Guidelines for Using DSP Blocks

Design Guidelines for Using DSP Blocks Design Guidelines for Using DSP Blocks in the Synplify Software April 2002, ver. 1.0 Application Note 193 Introduction Altera R Stratix TM devices have dedicated digital signal processing (DSP) blocks

More information

Simulating the ASMI Block in Your Design

Simulating the ASMI Block in Your Design 2015.08.03 AN-720 Subscribe Supported Devices Overview You can simulate the ASMI block in your design for the following devices: Arria V, Arria V GZ, Arria 10 Cyclone V Stratix V In the Quartus II software,

More information

AN 826: Hierarchical Partial Reconfiguration Tutorial for Stratix 10 GX FPGA Development Board

AN 826: Hierarchical Partial Reconfiguration Tutorial for Stratix 10 GX FPGA Development Board AN 826: Hierarchical Partial Reconfiguration Tutorial for Stratix 10 GX FPGA Development Board Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF

More information

PCI Express*: Migrating to Intel Stratix 10 Devices for the Avalon Streaming Interface

PCI Express*: Migrating to Intel Stratix 10 Devices for the Avalon Streaming Interface PCI Express*: Migrating to Intel Stratix 10 Devices for the Avalon Streaming Interface AN791 2017.05.08 Last updated for Intel Quartus Prime Design Suite: Quartus Prime Pro v17.1 Stratix 10 Editions Subscribe

More information

Intel MAX 10 Clocking and PLL User Guide

Intel MAX 10 Clocking and PLL User Guide Intel MAX 10 Clocking and PLL User Guide Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Intel MAX 10 Clocking and PLL

More information

Intel Stratix 10 Power Management User Guide

Intel Stratix 10 Power Management User Guide Intel Stratix 10 Power Management User Guide Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Intel Stratix 10 Power Management Overview... 3 2 Intel Stratix 10 Power Management

More information

Intel MAX 10 Clocking and PLL User Guide

Intel MAX 10 Clocking and PLL User Guide Intel MAX 10 Clocking and PLL User Guide Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1. Intel MAX 10 Clocking and PLL

More information

Implementing 9.8G CPRI in Arria V GT and ST FPGAs

Implementing 9.8G CPRI in Arria V GT and ST FPGAs 03..06 AN 686 Subscribe This application note describes the implementation of 9.8304 Gbps Common Public Radio Interface (CPRI) using the Arria V GT and Arria V ST FPGA transceivers. The hard physical coding

More information

MAX 10 Embedded Memory User Guide

MAX 10 Embedded Memory User Guide MAX 10 Embedded Memory User Guide UG-M10MEMORY 2017.02.21 Subscribe Send Feedback Contents Contents 1 MAX 10 Embedded Memory Overview... 4 2 MAX 10 Embedded Memory Architecture and Features... 5 2.1 MAX

More information

FFT MegaCore Function User Guide

FFT MegaCore Function User Guide FFT MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com MegaCore Version: 11.0 Document Date: May 2011 Copyright 2011 Altera Corporation. All rights reserved. Altera, The

More information

Intel Quartus Prime Pro Edition User Guide

Intel Quartus Prime Pro Edition User Guide Intel Quartus Prime Pro Edition User Guide Block-Based Design Updated for Intel Quartus Prime Design Suite: 18.1 Subscribe Latest document on the web: PDF HTML Contents Contents 1. Block-Based Design Flows...

More information

4. TriMatrix Embedded Memory Blocks in HardCopy IV Devices

4. TriMatrix Embedded Memory Blocks in HardCopy IV Devices January 2011 HIV51004-2.2 4. TriMatrix Embedded Memory Blocks in HardCopy IV Devices HIV51004-2.2 This chapter describes TriMatrix memory blocks, modes, features, and design considerations in HardCopy

More information

Intel High Level Synthesis Compiler

Intel High Level Synthesis Compiler Intel High Level Synthesis Compiler Best Practices Guide Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1. Intel HLS Compiler

More information

Intel Quartus Prime Standard Edition Software and Device Support Release Notes

Intel Quartus Prime Standard Edition Software and Device Support Release Notes Intel Quartus Prime Standard Edition Software and Device Support Release Notes RN-01080-.0 205.08 Subscribe Send Feedback Contents Contents 1 Intel Quartus Prime Standard Edition Software and Device Support

More information

AN 818: Static Update Partial Reconfiguration Tutorial

AN 818: Static Update Partial Reconfiguration Tutorial AN 818: Static Update Partial Reconfiguration Tutorial for Intel Stratix 10 GX Updated for Intel Quartus Prime Design Suite: 18.1 Subscribe Latest document on the web: PDF HTML Contents Contents 1. Static

More information

Intel Quartus Prime Standard Edition Software and Device Support Release Notes

Intel Quartus Prime Standard Edition Software and Device Support Release Notes Intel Quartus Prime Standard Edition Software and Device Support Release Notes Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Intel Quartus Prime Standard Edition Software

More information

10. Introduction to UniPHY IP

10. Introduction to UniPHY IP 10. Introduction to Uni IP November 2012 EMI_RM_008-2.1 EMI_RM_008-2.1 The Altera,, and LP SDRAM controllers with Uni, QDR II and QDR II+ SRAM controllers with Uni, RLDRAM II controller with Uni, and RLDRAM

More information

Intel Quartus Prime Standard Edition User Guide

Intel Quartus Prime Standard Edition User Guide Intel Quartus Prime Standard Edition User Guide Timing Analyzer Updated for Intel Quartus Prime Design Suite: 18.1 Subscribe Latest document on the web: PDF HTML Contents Contents 1. Timing Analysis Introduction...

More information

Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide

Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide 2015.05.04 Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide UG-01155 Subscribe The Altera IOPLL megafunction IP core allows you to configure the settings of Arria 10 I/O PLL. Altera IOPLL

More information

AN 370: Using the Intel FPGA Serial Flash Loader with the Intel Quartus Prime Software

AN 370: Using the Intel FPGA Serial Flash Loader with the Intel Quartus Prime Software AN 370: Using the Intel FPGA Flash Loader with the Intel Quartus Prime Software Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Using the Intel FPGA Flash Loader IP Core

More information