CS8803: Advanced Digital Design for Embedded Hardware

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1 CS883: Advanced Digital Design for Embedded Hardware Lecture 2: Boolean Algebra, Gate Network, and Combinational Blocks Instructor: Sung Kyu Lim Website:

2 Design flow for HDL-based ASICs Design Specification 8 Post-synthesis Design Validation 2 Design Partition 9 Post-synthesis Timing Verification 3 Design Entry: Verilog Behavioral Modeling Test Generation and Fault Simulation 4 Simulation/Functional Verification Cell Placement, Scan Chain and Clock Tree Insertion, Cell Routing 5 Design Integration and Verification 2 Verify Physical and Electrical Design Rules 6 Pre-synthesis Sign-Off 3 Extract Parasitics 7 Synthesize and Map Gate-level Netlist 4 Design Sign-Off Production-ready Masks

3 Copyright 2, 23 MD Ciletti 6 COMBINATIONAL LOGIC Combinational logic forms Boolean functions of the input variables. The outputs at any time, t, are a function of only the inputs at time t. The variables are assumed to be binary. a b c d Combinational Logic y y 2 y 3 y = f (a, b, c, d) y 2 = f 2 (a, b, c, d) y 3 = f 3 (a, b, c, d) y 4 = f 4 (a, b, c, d) A binary variable may have a value of or. Later, the logic value system will be expanded to have more values to support a hardware description language. POSITIVE LOGIC: Low voltage corresponds to logic and a high voltage corresponds to a logic.

4 Copyright 2, 23 MD Ciletti 7 LOGIC GATES And Gate y = a. b Or Gate y = a + b Xor Gate y = a ^ b a b y a b y a b y Nand Gate y = a. b Nor Gate y = a + b Xnor Gate y = a ^ b a b y a b y a b y Buffer y = a Inverter y = a Three-State Buffer y = a if ENB =, else y = z a y a y a y ENB

5 CHAPTER IV-3 GATE DESIGN GATE NETWORKS VALID/INVALID NETWORKS GATE NETWORKS -INTRODUCTION G G 2 G G 3 G 3 G 6 G 2 Valid or Invalid? Valid or Invalid? G G 3 G G 3 G 2 Valid or Invalid? G 2 Valid or Invalid? R.M. Dansereau; v..

6 CHAPTER IV-7 GATE DESIGN LOGIC NETWORKS FROM BOOLEAN FUNCTIONS LOGIC GATES -NON-INVERTING OPER. -INVERTING OPERATORS -INVERTERS Implement the following Boolean function using logic gates F = (( A + BC)D) + C+ DE Possible solution: A B C D E F 3 6 AND OR NOT = 42 transistors for CMOS technology. R.M. Dansereau; v..

7 CHAPTER IV-8 GATE DESIGN LOGIC NETWORKS USING SPECIFIC GATES LOGIC GATES LOGIC NETWORKS -FROM BOOL. FUNCTIONS Because of various implementation reasons, it may be desired to use only specific sorts of logic gates in an implementation. For instance, many CMOS implementations use only NAND gates. Some implementations use on NOR gates. This can be done in a number of manners. One is to rework the Boolean functions so that only the specific gates desired are used. May reduce the physical number of transistors required if the appropriate types of gates are used. R.M. Dansereau; v..

8 CHAPTER IV-9 GATE DESIGN LOGIC NETWORKS EXAMPLE USING NAND GATES LOGIC GATES LOGIC NETWORKS -FROM BOOL. FUNCTIONS -USING SPECIFIC GATES Implement the following Boolean function using NAND gates F = (( A + BC)D) + C+ DE This Boolean function can be expressed as F = ABCDCDE = ((( A ( BC ) ) D)( C )( DE) ) A B How to implement 4-input NAND? C D E 6 4 NAND NAND-4 = NAND NAND NOT = 26 F transistors transistors R.M. Dansereau; v..

9 CHAPTER IV- GATE DESIGN MIXED LOGIC INTRODUCTION LOGIC NETWORKS -FROM BOOL. FUNCTIONS -USING SPECIFIC GATES -EXAMPLE USING NAND Mixed logic is one approach that makes it easier to redesign a logic network to use desired types of gates. Mixed logic is also self-documenting This means that you can see what the original designer started with and see how the logic network was changed for the implementation. The idea behind mixed logic is to diagram out the logic network from the Boolean equations given, and then make small changes to the logic network to achieve desired results for implementation. R.M. Dansereau; v..

10 CHAPTER IV- GATE DESIGN MIXED LOGIC DEMORGAN S SQUARE LOGIC NETWORKS MIXED LOGIC -INTRODUCTION DeMorgan s Square AND OR A B F A B F NAND NOR A B F A B F R.M. Dansereau; v..

11 CHAPTER IV-2 GATE DESIGN MIXED LOGIC MIXED LOGIC PROCEDURE LOGIC NETWORKS MIXED LOGIC -INTRODUCTION -DEMORGAN S SQUARE The procedure for performing mixed logic conversions is as follows: Draw the logic network for the given Boolean equation. Use only AND and OR gates. Replace all complements with a bar (no bubbles or inverters yet!) Once the initial Boolean equation is drawn with AND gates, OR gates and bars, the self-documenting redesign begins: Add complement bubbles and NOT gates within the network to appropriately convert logic gates to desired gate sets. The rules in adding complement bubbles and NOT gates All bubbles must cancel each other out Exactly one and only one bubble needed on each bar R.M. Dansereau; v..

12 CHAPTER IV-3 GATE DESIGN MIXED LOGIC EXAMPLE # () MIXED LOGIC -INTRODUCTION -DEMORGAN S SQUARE -MIXED LOGIC PROC. Implement the following Boolean function using NAND gates and then also using NOR gates. Solution: Start by drawing the logic network for the Boolean function with A B C D the complements as bars. F = AB + CD This completes the information needed to get back original equation. F R.M. Dansereau; v..

13 CHAPTER IV-4 GATE DESIGN MIXED LOGIC EXAMPLE # (2) MIXED LOGIC -DEMORGAN S SQUARE -PROCEDURE -EXAMPLE # continued... using NAND gates A B F C D This logic network now only uses NAND gates and inverters. This results in the following Boolean function, as obtained previously F( A, B, C, D, E) = ABCD R.M. Dansereau; v..

14 CHAPTER IV-5 GATE DESIGN MIXED LOGIC EXAMPLE # (3) MIXED LOGIC -DEMORGAN S SQUARE -PROCEDURE -EXAMPLE # continued... using NOR gates A B F C D This logic network now only uses NOR gates and inverters. This results in the following Boolean function, as obtained previously F( A, B, C, D, E) = A + B + C + D R.M. Dansereau; v..

15 CHAPTER IV-6 GATE DESIGN MIXED LOGIC EXAMPLE #2 () MIXED LOGIC -DEMORGAN S SQUARE -PROCEDURE -EXAMPLE # Implement the following Boolean function using NAND gates F = (( A + BC)D) + C+ DE Solution: Start by drawing the logic network for the Boolean function with the complements as bars. A B C D E F R.M. Dansereau; v..

16 CHAPTER IV-7 GATE DESIGN MIXED LOGIC EXAMPLE #2 (2) MIXED LOGIC -PROCEDURE -EXAMPLE # -EXAMPLE #2 continued... A B C D E F This logic network now only uses NAND gates and inverters. This results in the following Boolean function, as obtained previously F( A, B, C, D, E) = ABCDCDE = ABCDCDE R.M. Dansereau; v..

17 Copyright 2, 23 MD Ciletti 9 BOOLEAN ALGEBRA (p 6) A binary Boolean algebra consists of a set B = {, } and the operators + and., having commutative and distributive properties such that for two Boolean variables A and B having values in B, a + b = b + a, and a. b = b. a. The operators + and. have identity elements and, respectively, such that for any Boolean variable a, a + = a, and a. = a. Each Boolean variable a has a complement, denoted by a', such that a + a' =, and a. a' =. Terminology: + is called the sum operator, the "OR" operator, or the disjunction operator.. is called the product operator, the "AND" operator, or the conjunction operator. The multi-dimensional space spanned by a set of n binary-valued Boolean variables is denoted by B n. A point in B n is called a vertex of and is represented by an n-dimensional vector of binary valued elements, e.g. (). A binary variable can be associated with the dimensions of a binary Boolean space, and a point is identified with the values of the variables.

18 Copyright 2, 23 MD Ciletti BOOLEAN FUNCTIONS A completely specified m-dimensional Boolean function is a mapping from B n into B m, denoted by f: B n B m. An incompletely specified function is defined over a subset of B n, and is considered to have a value of "don't-care" at points outside of the subset of definition: f: B n {,, *}, where * denotes don't-care. "On" Set: {x: x B n and f(x) = } "Off" Set: {x: x B n and f(x) = } "dc" Set: {x: x B n and f(x) = * } The don't-care set accommodates input patterns that never care, or outputs that will not be observed.

19 CHAPTER III-7 BOOLEAN ALGEBRA BOOLEAN ALGEBRA BASIC IDENTITIES BOOLEAN OPERATIONS BOOLEAN ALGEBRA -PRECEDENCE OF OPER. -FUNCTION EVALUATION X + = X X + = X + X = X X + X = ( X ) = X X + Y = Y + X X + ( Y + Z) = ( X + Y) + Z XY ( + Z) XY + XZ X X + XY = X + X Y = X + Y ( X + Y) = X Y X = X X = X X X = XY = YX XYZ ( ) = ( XY)Z = X + YZ = ( X + Y) ( X + Z) X = X XX ( + Y) = X XX ( + Y) = XY ( XY) = X + Y XY + X Z + YZ ( X + Y) ( X + Z) ( Y + Z) = XY + X Z = ( X + Y) ( X + Z) Identity Idempotent Law Complement Involution Law Commutativity Associativity Distributivity Absorption Law Simplification DeMorgan s Law Consensus Theorem R.M. Dansereau; v..

20 CHAPTER III-8 BOOLEAN ALGEBRA BOOLEAN ALGEBRA DUALITY PRINCIPLE BOOLEAN ALGEBRA -PRECEDENCE OF OPER. -FUNCTION EVALUATION -BASIC IDENTITIES Duality principle: States that a Boolean equation remains valid if we take the dual of the expressions on both sides of the equals sign. The dual can be found by interchanging the AND and OR operators along with also interchanging the s and s. This is evident with the duals in the basic identities. For instance: DeMorgan s Law can be expressed in two forms ( X + Y) = X Y as well as ( XY) = X + Y R.M. Dansereau; v..

21 Copyright 2, 23 MD Ciletti 7 REPRESENTATION OF COMBINATIONAL LOGIC Common representations of combinational logic: Truth Table Boolean Equations Binary Decision Diagrams Circuit Schematic EXAMPLE: HALF-ADDER TRUTH TABLE Inputs Outputs a b c_out sum a b Add_half sum c_out a b sum c_out

22 Copyright 2, 23 MD Ciletti 8 REPRESENTATION OF COMBINATIONAL LOGIC (Cont.) EXAMPLE: HALF-ADDER BOOLEAN EQUATIONS sum = a'b + ab' = a b c_out = a. b a b Add_half sum c_out a b sum c_out

23 CHAPTER III-4 BOOLEAN ALGEBRA STANDARD FORMS SUM OF MINTERMS BOOLEAN ALGEBRA STANDARD FORMS -SOP AND POS -MINTERMS Sum-of-minterms standard form expresses the Boolean or switching expression in the form of a sum of products using minterms. For instance, the following Boolean expression using minterms FABC (,, ) = ABC + ABC + ABC + ABC could instead be expressed as FABC (,, ) = m + m + m 4 + m 5 or more compactly FABC (,, ) = m(,, 4, 5) = one-set(,, 4, 5) R.M. Dansereau; v..

24 CHAPTER III-6 BOOLEAN ALGEBRA STANDARD FORMS PRODUCT OF MAXTERMS STANDARD FORMS -MINTERMS -SUM OF MINTERMS -MAXTERMS Product-of-maxterms standard form expresses the Boolean or switching expression in the form of product of sums using maxterms. For instance, the following Boolean expression using maxterms FABC (,, ) = ( A+ B+ C) ( A+ B+ C) ( A+ B + C) could instead be expressed as FABC (,, ) = M M 4 M 7 or more compactly as FABC (,, ) = M(, 4, 7) = zero-set(, 4, 7) R.M. Dansereau; v..

25 CHAPTER III-7 BOOLEAN ALGEBRA STANDARD FORMS MINTERM AND MAXTERM EXP. STANDARD FORMS -SUM OF MINTERMS -MAXTERMS -PRODUCT OF MAXTERMS Given an arbitrary Boolean function, such as FABC (,, ) = AB + B( A + C) how do we form the canonical form for: sum-of-minterms Expand the Boolean function into a sum of products. Then take each term with a missing variable X and AND it with X + X. product-of-maxterms Expand the Boolean function into a product of sums. Then take each factor with a missing variable X and OR it with XX. R.M. Dansereau; v..

26 CHAPTER III-8 BOOLEAN ALGEBRA STANDARD FORMS FORMING SUM OF MINTERMS STANDARD FORMS -MAXTERMS -PRODUCT OF MAXTERMS -MINTERM & MAXTERM Example FABC (,, ) = AB + B( A + C) = AB + AB + BC = AB( C + C) + AB( C + C) +( A + A)BC = ABC + ABC + ABC + ABC + ABC = m(,, 4, 6, 7) A B C F Minterms listed as s in Truth Table R.M. Dansereau; v..

27 CHAPTER III-9 BOOLEAN ALGEBRA STANDARD FORMS FORMING PROD OF MAXTERMS STANDARD FORMS -PRODUCT OF MAXTERMS -MINTERM & MAXTERM -FORM SUM OF MINTERMS Example F( A, B, C) = AB + B( A + C) = AB + AB + BC = = = = ( A + B) ( A + B + C) ( A + B + C) ( A + B + CC) ( A+ B+ C) ( A+ B+ C) ( A + B + C) ( A + B + C) ( A + B + C) M( 2, 3, 5) A B C F (using distributivity) Maxterms listed as s in Truth Table R.M. Dansereau; v..

28 CHAPTER III-2 BOOLEAN ALGEBRA STANDARD FORMS CONVERTING MIN AND MAX STANDARD FORMS -MINTERM & MAXTERM -SUM OF MINTERMS -PRODUCT OF MAXTERMS Converting between sum-of-minterms and product-of-maxterms The two are complementary, as seen by the truth tables. To convert interchange the and, then use missing terms. Example: The example from the previous slides FABC (,, ) = m(,, 4, 6, 7) is re-expressed as F( A, B, C) = M( 2, 3, 5) where the numbers 2, 3, and 5 were missing from the minterm representation. R.M. Dansereau; v..

29 Copyright 2, 23 MD Ciletti 26 SIMPLIFICATION OF BOOLEAN EXPRESSIONS (Cont.) A Boolean expression in SOP form is said to be minimal if it contains a minimal number of product terms and literals (i.e. a given term cannot be replaced by another that has fewer literals). A minimum SOP form corresponds to a two-level logic circuit having the fewest gates and the fewest number of gate inputs. A Boolean expression in POS form is said to be minimal of it contains a minimal number of factors and literals (i.e. a given factor cannot be replace by another having fewer literals). Three approaches: () Karnaugh maps and extended karnaugh maps (Feasible for up to 6 variables) (2) Quine-McCluskey minimization (computer-based) (3) Boolean minimization (manual) uses the theorems describing relationships between Boolean variables to find simpler equivalent expressions (It is not straightforward, is not easy, and requires experience. Now embedded in synthesis tools such as mis II.)

30 CHAPTER III-2 BOOLEAN ALGEBRA SIMPLIFICATION KARNAUGH MAPS STANDARD FORMS -SUM OF MINTERMS -PRODUCT OF MAXTERMS -CONVERTING MIN & MAX Often it is desired to simplify a Boolean function. A quick graphical approach is to use Karnaugh maps. 2-variable Karnaugh map 3-variable Karnaugh map 4-variable Karnaugh map CD AB A B BC A F = AB F = AB + C F = AB + CD R.M. Dansereau; v..

31 CHAPTER III-22 BOOLEAN ALGEBRA SIMPLIFICATION KARNAUGH MAP ORDERING STANDARD FORMS SIMPLIFICATION -KARNAUGH MAPS Notice that the ordering of cells in the map are such that moving from one cell to an adjacent cell only changes one variable. 2-variable Karnaugh map 3-variable Karnaugh map 4-variable Karnaugh map CD D D D AB BC A B C C C 3 2 A A A 3 2 A A 2 3 A A 8 9 B B B B C C B B B This ordering allows for grouping of minterms/maxterms for simplification. R.M. Dansereau; v..

32 CHAPTER III-23 BOOLEAN ALGEBRA SIMPLIFICATION IMPLICANTS STANDARD FORMS SIMPLIFICATION -KARNAUGH MAPS -KARNAUGH MAP ORDER Implicant Bubble covering only s (size of bubble must be a power of 2). Prime implicant Bubble that is expanded as big as possible (but increases in size by powers of 2). Essential prime implicant Bubble that contains a covered only by itself and no other prime implicant bubble. Non-essential prime implicant A that can be bubbled by more then one prime implicant bubble. CD AB R.M. Dansereau; v..

33 CHAPTER III-24 BOOLEAN ALGEBRA SIMPLIFICATION PROCEDURE FOR SOP SIMPLIFICATION -KARNAUGH MAPS -KARNAUGH MAP ORDER -IMPLICANTS Procedure for finding the SOP from a Karnaugh map Step : Form the 2-, 3-, or 4-variable Karnaugh map as appropriate for the Boolean function. Step 2: Identify all essential prime implicants for s in the Karnaugh map Step 3: Identify non-essential prime implicants for s in the Karnaugh map. Step 4: For each essential and one selected non-essential prime implicant from each set, determine the corresponding product term. Step 5: Form a sum-of-products with all product terms from previous step. R.M. Dansereau; v..

34 CHAPTER III-26 BOOLEAN ALGEBRA SIMPLIFICATION EXAMPLE FOR SOP (2) SIMPLIFICATION -IMPLICANTS -PROCEDURE FOR SOP -EXAMPLE FOR SOP Simplify the following Boolean function FABC (,, ) = m(,, 4, 6, 7) = ABC + ABC + ABC + ABC + ABC Solution: BC A zero-set( 235,, ) one-set(,, 4, 6, 7) The essential prime implicants are AB and AB. The non-essential prime implicants are BC or AC. The sum-of-products solution is F = AB+ AB+ BC or F = AB+ AB+ AC. R.M. Dansereau; v..

35 CHAPTER III-27 BOOLEAN ALGEBRA SIMPLIFICATION PROCEDURE FOR POS SIMPLIFICATION -IMPLICANTS -PROCEDURE FOR SOP -EXAMPLE FOR SOP Procedure for finding the SOP from a Karnaugh map Step : Form the 2-, 3-, or 4-variable Karnaugh map as appropriate for the Boolean function. Step 2: Identify all essential prime implicants for s in the Karnaugh map Step 3: Identify non-essential prime implicants for s in the Karnaugh map. Step 4: For each essential and one selected non-essential prime implicant from each set, determine the corresponding sum term. Step 5: Form a product-of-sums with all sum terms from previous step. R.M. Dansereau; v..

36 CHAPTER III-29 BOOLEAN ALGEBRA SIMPLIFICATION EXAMPLE FOR POS (2) SIMPLIFICATION -EXAMPLE FOR SOP -PROCEDURE FOR POS -EXAMPLE FOR POS Simplify the following Boolean function F( A, B, C) = M(,, 5, 7, 8, 9, 5) Solution: The essential prime implicants are B + C and B+ C+ D. The non-essential prime implicants can be A + B + D or A+ C+ D. The product-of-sums solution can be either F = ( B+ C) ( B+ C+ D) ( A + B + D) or F = ( B+ C) ( B+ C+ D) ( A + C + D) zero-set(,, 5, 7, 8, 9, 5) one-set( 2, 3, 4, 6,,, 2, 3, 4) CD AB R.M. Dansereau; v..

37 CHAPTER III-3 BOOLEAN ALGEBRA SIMPLIFICATION DON T-CARE CONDITION SIMPLIFICATION -EXAMPLE FOR SOP -PROCEDURE FOR POS -EXAMPLE FOR POS Switching expressions are sometimes given as incomplete, or with don tcare conditions. Having don t-care conditions can simplify Boolean expressions and hence simplify the circuit implementation. Along with the zero-set () and one-set (), we will also have dc (). Don t-cares conditions in Karnaugh maps Don t-cares will be expressed as an X or - in Karnaugh maps. Don t-cares can be bubbled along with the s or s depending on what is more convenient and help simplify the resulting expressions. R.M. Dansereau; v..

38 CHAPTER III-3 BOOLEAN ALGEBRA SIMPLIFICATION DON T-CARE EXAMPLE () SIMPLIFICATION -PROCEDURE FOR POS -EXAMPLE FOR POS -DON T-CARE CONDITION Find the SOP simplification for the following Karnaugh map CD AB dc(, 3, 4) X X Taken to be X Taken to be Solution: The essential prime implicants are BD and BC. There are no non-essential prime implicants. The sum-of-products solution is F = BC+ BD. zero-set(,, 5, 7, 8, 9, 5) one-set( 2, 3, 4, 6,, 2) R.M. Dansereau; v..

39 CHAPTER III-32 BOOLEAN ALGEBRA SIMPLIFICATION DON T-CARE EXAMPLE (2) SIMPLIFICATION -EXAMPLE FOR POS -DON T-CARE CONDITION -DON T-CARE EXAMPLE Find the POS simplification for the following Karnaugh map CD AB dc(, 3, 4) Taken X X X Taken to be to be Solution: The essential prime implicants are B + C and B + D. There are no non-essential prime implicants. The product-of-sums solution is F = ( B+ C) ( B + D). zero-set(,, 5, 7, 8, 9, 5) one-set( 2, 3, 4, 6,, 2) R.M. Dansereau; v..

40 GLITCHES AND STATIC HAZARDS (p 42) Copyright 2, 23 MD Ciletti 5 The output of a combinational circuit may make a transition even though the patterns applied at its inputs do not imply a change. These unwanted switiching transients are called "glitches." Glitches are a consequence of the circuit structure and the application of patterns that cause the glitch to occur. A circuit in which a glitch may occur under the application of appropriate inputs signals is said to have a hazard. A static -hazard occurs if an output has an initial value of, and an input pattern that does not imply an output transition causes the output to change to and then return to. -Hazard A static -hazard occurs if an output has an initial value of, and an input pattern that does not imply an output transition causes the output to change to and then return to. -Hazard

41 GLITCHES AND STATIC HAZARDS Copyright 2, 23 MD Ciletti 52 Static hazards are caused by differential propagation delays on reconvergent fanout paths. A "minimal"realization of a circuit might not be hazard-free. Static hazards can be eliminated by introducing redundant cubes in the cover of the output expression (the added cubes are called a hazard cover).

42 Copyright 2, 23 MD Ciletti 53 STATIC HAZARDS: Example A C F F Reconvergent fanout paths B F Consider F = AC + BC' Initial inputs: A =, B =, C = and F = New inputs: A =, B =, C = and F = In a physical realization of the circuit (i.e. non-zero propagation delays), the path to F will be longer than the path to F, causing a change in C to reach F later than it reaches F. Consequently, when C changes from to, the output undergoes a momentary transition to and returns to. The presence of a static hazard is apparent in the Karnaugh map of the output.

43 STATIC HAZARDS: Example (Cont.) Copyright 2, 23 MD Ciletti 54 Hazards might not be significant in a synchronous sequential circuit if the clock period can be extended. y Static -Hazard occurs when F and F are both momentarily. A hazard is problematic if the signal serves as the input to an asynchronous subsystem. (e.g a counter or a reset circuit). In this example, the hazard occurs because the cube AC is initially asserted, while BC' is not. The switched input causes AC to de-assert before BC' can assert. C AB F = AC + BC' C AB Redundant cube Hazard Removal: A hazard can be removed by covering the adjacent prime implicants by a redundant cube (AB, a 'hazard cover") to eliminate the dependency on C (the boundary between the cubes is now covered). AC de-asserts before BC' asserts

44 Copyright 2, 23 MD Ciletti 55 STATIC HAZARDS: Example (Cont.) Hazard covers require extra hardware. Example: For the hazard-free cover: F = AC + BC' + AB A C F B

45 Copyright 2, 23 MD Ciletti 56 ELIMINATION OF STATIC HAZARDS (SOP Form) If the output cubes of the initial and final inputs are covered by the same prime implicant, a glitch cannot occur. Otherwise, if the output cubes of the initial and final inputs are not covered by the same prime implicant a glitch can occur, depending on the accumulated delays along the signal propagation paths from the inputs to the output. For a circuit whose static -hazard is caused by a transition in a single bit of a single signal: Form a SOP cover in which every pair of adjacent s is covered by a cube. This gurantees that every single-bit input change is covered by such a prime implicant. The set of prime implicants is a hazard-free cover for a two-level (And-Or) realization of the circuit, but a better alternative might be found.

46 Copyright 2, 23 MD Ciletti 57 ELIMINATION OF STATIC HAZARDS (Cont.) To eliminate a static -hazard: Method #: Cover the adjacent s in the corresponding POS expression. Method #2: First eliminate the static -hazards. Then form complement function and consider whether the implicants of the s of the expression that is free of static -hazards also cover all adjacent s of the original function. If they do not, then a static -hazard exists.

47 Copyright 2, 23 MD Ciletti 58 EXAMPLE: ELIMINATION OF STATIC HAZARDS Static -hazard: f = Σ m(,, 4, 5, 6, 7, 4, 5) = a'c' + bc Static -hazard (First method): From s of the K-map and DeMorgan's Law: f' = ac' + b'c and f = (a' + c) (b + c') a'c' cd ab m m m3 m2 m4 m5 m7 m6 m2 m3 m5 m4 m8 m9 m m Cover the cube boundaries by adding a'bd or a'b to eliminate the static - hazard bc cd ab m m m3 m2 m4 m5 m7 m6 m2 m3 m5 m4 m8 m9 m m Cover by adding (a' + b) to eliminate static- hazard Note: ab'd covers too, but is not mimimal f = a'c' + bc + a'b With a =, b =, and D =, a glitch can occur as c changes from to or visa-versa. Adding the redundant prime implicant term eliminates the static -hazard. Note: m 4 and m 6 interface f = (a' + c) (b + c') (a' + b) Add a'b to f', and including the redundant prime implicant product factor (a' + b) in f to eliminate the static -hazard.

48 DYNAMIC HAZARDS (Multiple glitches) Copyright 2, 23 MD Ciletti 6 A circuit has a dynamic hazard if an input transition is supposed to cause a single transition in an output, but causes two or more transitions before reached its expected value. Dynamic Hazard Dynamic hazards are a consequence of multiple static hazards caused by multiply reconvergent paths in a multilevel circuit. Dynamic hazards are not easy to eliminate. Elimination of all static hazards eliminates dynamic hazards. Approach: Transform a multilevel circuit into a two-level circuit and eliminate all of the static hazards.

49 CHAPTER VI-4 COMBINATIONAL LOGIC MULTIPLEXERS BASIC MULTIPLEXER (MUX) ENCODERS -DESIGN W/ ENCODERS -PRIORITY ENCODERS -DESIGN W/ P-ENCODERS Selects one of many inputs to be directed to an output. Module Enable Inputs E X Y A 3 A 2 A A A X X X X X X A X X X f 2 X X X A 2 A 3 3 4x Multiplexer S S X Y X X X X X X X X X X X X Output F A = A = A 2 = A 3 = A = A = A 2 = A 3 = R.M. Dansereau; v..

50 CHAPTER VI-5 COMBINATIONAL LOGIC MULTIPLEXERS USING PASS GATES ENCODERS MULTIPLEXERS -BASIC MULTIPLEXER The 4x mux can be implemented with pass gates as follows. Y X A A Out (f) A 2 A 3 Only one of A n gets passed to output. Depends on the value of X and Y. R.M. Dansereau; v..

51 CHAPTER VI-6 COMBINATIONAL LOGIC MULTIPLEXERS DESIGN WITH MULTIPLEXERS ENCODERS MULTIPLEXERS -BASIC MULTIPLEXER -USING PASS GATES Any Boolean function can be implemented by setting the inputs corresponding to the function and the selectors as the variables. Example: Module Enable X Y Z F E x Multiplexer S 2 S X Y S Z f R.M. Dansereau; v..

52 Copyright 2, 23 MD Ciletti 69 BUILDING BLOCKS: MULTIPLEXERS (p 6) MUXES PROVIDE STEERING FOR DATAPATHS. a sel y_out b y_out = sel. a + sel'. b

53 Copyright 2, 23 MD Ciletti 7 DEMULTIPLEXERS A demultiplexer has a single datapath input, n datapath outputs, and m address inputs. The m-bit address determines which of the n outputs is connected to the input. Address[m-: ] m Address Data_Out [n-] Data_In Data_In Demultiplexer Data_Out [] Output channel selection: Data_Out [n-: ] = Data_In [Address[k]]

54 Copyright 2, 23 MD Ciletti 72 ENCODERS An encoder has n inputs and m outputs, with n = 2 m. Ordinarily, only one of the inputs is asserted at a time. A unique output bit pattern (code) is assigned to each of the n inputs. The asserted output is determined by the index of the asserted bit of the n-bit binary input word. Data_In[n-] Data_In n Data_Out m Data_Out m Encoder Data_In[] Encoder Example: n = 4, m = 2, Data_In [3] = and Data_In [k] = for < k < n, k 3 Data_Out [:] = 2 = 3 A Mux does not change the data input, but encoders transform the data input to form the data output. The encoder assigns a unique bit pattern to each input line.

55 Copyright 2, 23 MD Ciletti 73 PRIORITY ENCODERS A priority encoder allows multiple input bits to be asserted simultaneously, and uses a priority rule to form an output bit pattern. Example: Data_In [3:] Data_out [2:] xxx xxxx xx xxxx x xxxx xxxx xxx xx x Note: "-" denotes a don't care condition.

56 Copyright 2, 23 MD Ciletti 74 DECODERS A decoder has m inputs and n outputs, with n = 2 m. Only one of the outputs is asserted at a time. The asserted output is determined by the decimal equivalent of the m-bit binary input word. Data_Out[n-] Data_In Data_out Data_In m n m Decoder Decoder Data_Out[] Example: n = 4, m = 2 Data_In = 2 and Data_Out [3] = and Data_Out[k] = for k 3

57 CHAPTER VI-6 COMBINATIONAL LOGIC DECODERS IMPLEMENTATION DECODERS -BASIC DECODER -WITH ENABLE -TRUTH TABLES How can a decoder be implemented? Fill in the circuit! A 2 A A D 7 D 6 D 5 D 4 D 3 D 2 D D A 2 A A A 2 A A A 2 A A A 2 A A A 2 A A A 2 A A A 2 A A A 2 A A R.M. Dansereau; v..

58 CHAPTER VI-7 COMBINATIONAL LOGIC DECODERS DESIGNING WITH DECODERS DECODERS -WITH ENABLE -TRUTH TABLES -IMPLEMENTATION Any Boolean function can implemented using a decoder and OR gates by ORing together the function s minterms. A 2 Inputs A A Outputs F F 2 A 2 2 A A F to-8 Decoder F R.M. Dansereau; v..

59 CHAPTER VI-8 COMBINATIONAL LOGIC DECODERS DECODER NETWORKS DECODERS -TRUTH TABLES -IMPLEMENTATION -DESIGNING W/DECODERS We can also use multiple decoders to form a larger decoder. 3-to-8 Decoder Implemented with two 2-to-4 Decoders A 2 used with enable input to control which decoder will output the. A A A E 2-to-4 Decoder 2 3 D D D 2 D 3 A and A used to select which output on specific decoder will output. 2 2 E 2-to-4 Decoder 2 3 D 4 D 5 D 6 D 7 R.M. Dansereau; v..

60 CHAPTER VI-22 COMBINATIONAL LOGIC ADDERS HALF- AND FULL-ADDERS DEMULTIPLEXERS SHIFTERS ROTATORS -BASIC ROTATOR Two basic building blocks for arithmetic are half- and full-adders as depicted by the block diagrams below. A B A B C OUT Carry-out HA C OUT Carry-out FA C IN Carry-in S Sum S Sum Half-adder Full-adder R.M. Dansereau; v..

61 CHAPTER VI-23 COMBINATIONAL LOGIC ADDERS HALF-ADDER (HA) SHIFTERS ROTATORS ADDERS -HALF- & FULL-ADDERS First of all, how do we add? 2 s complement arithmetic allows us to add numbers normally. Inputs A B Sum Carry-out S = AB+ AB = A B S C OUT A B C OUT = AB S C OUT R.M. Dansereau; v..

62 CHAPTER VI-24 COMBINATIONAL LOGIC ADDERS FULL-ADDER (FA) () ROTATORS ADDERS -HALF- & FULL-ADDERS -HALF-ADDER (HA) Half-adder missed a possible carry-in. A full-adder (FA) includes this additional carry-in. Inputs Carry-in Sum Carry-out A B C IN S C OUT S = ( A B) C IN C OUT = AB + C IN ( A B) R.M. Dansereau; v..

63 CHAPTER VI-25 COMBINATIONAL LOGIC ADDERS FULL-ADDER (FA) (2) ADDERS -HALF- & FULL-ADDERS -HALF-ADDER (HA) -FULL-ADDER (FA) Half-adder S = ( A B) C IN C OUT = AB + C IN ( A B) Half-adder A B S C OUT C IN R.M. Dansereau; v..

64 CHAPTER VI-26 COMBINATIONAL LOGIC ADDERS BINARY ADDITION ADDERS -HALF- & FULL-ADDERS -HALF-ADDER (HA) -FULL-ADDER (FA) A 4-bit binary adder can be formed with four full-adders as follows. A 3 B 3 A 2 B 2 A B A B FA C 3 FA C 2 FA C FA C S 3 S 2 S S C 4 R.M. Dansereau; v..

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