EE 357 Project Multicycle CPU 1

Transcription

1 EE 357 Project Multicycle CPU Introduction You will work in teams of one or two to implement a basic multicycle CPU that can execute five MIPS instruction types (LW/SW, R-Type, BEQ, J, and ADDI). You will complete the datapath and control unit of the CPU and simulate its execution of some instruction sequences. You will then have the option of extending your CPU to implement more instructions for varying degrees of credit. What you will learn This lab will help you: Understand the detailed design of an appropriate datapath and control unit to execute the given instructions Understand the increasing complexity of the processor design as more instructions are supported Understand the value of simulating the processor design before actual circuit design and fabrication 3 Background Information and Notes To limit the scope of this lab, we will start by implementing only five instruction types: load/store, R-type, BEQ, J (jump), and ADDI. The design is based on the datapath and control unit (FSM) presented in the class notes (and reprinted in Figure and Figure 3) and you are encouraged to review these before beginning. You may also refer to Appendix D on the CD-ROM that was included with CO&D 4 th Ed. for a discussion on control unit implementation. Lab Organization: You will be implementing your CPU using the Xilinx ISE software that is currently used in other EE courses. This software is freely available as the Xilinx ISE Webpack from and is also installed on the campus lab PC s in SAL and other user rooms under the ISE label. This lab will require you to use Verilog to describe the hardware design. System Inputs/Outputs: The inputs to your CPU are clk, rst (active-high), and the memory interface signals. We will also bring out the interface signals to the register file for checking purposes in our testbench to ensure your design is working properly. The provided testbench will instantiate your CPU design and a memory model and connect them together. This is depicted in the Figure below. This lab was originally created by Prof. Gandhi Puvvada and adapted by Prof. Mark Redekopp Last Revised: 3/6/

2 ee357_mcpu_tb (Testbench) For checking purposes reg_ra[4:] reg_rb[4:] reg_radata[3:] reg_rbdata[3:] reg_wa[4:] reg_wdata[3:] regwrite ee357_mcpu (your design) clk rst mem_addr[3:] mem_wdata[3:] mem_rdata[3:] mem_read mem_write Initial Memory clk clk ee357_mem Contents read rst (provided 56x3 mem) from userprovided text mem_addr[9:] mem_addr[7:] file (e.g. memfile.txt) mem_wdata[3:] mem_rdata[3:] mem_read mem_write For checking purposes ee357_mcpu_chkr (Testbench + Checker) Figure - System Block Diagram Important Note: You may NOT change, add, or remove any I/O from your CPU design (leave it alone). However, you may need to change the output declarations to output reg type if you choose to implement that signal in an always block. Provided Components: We have implemented (either fully or partially) several components for you to make the task more manageable. These have been instantiated in the provided CPU skeleton design. ee357_regfile_rw.v: Implements a read-port, write-port, 3x3 register file. The I/O is defined below. It is complete and need not be modified by you. Signal I/O Description ra[4:], rb[4:] Input register select port a and port b data from selected registers (from ra and rb) radata[3:], Output rbdata[3:] wa[4:] Input register select wdata Input Data to write to selected register regwrite Input enable for register selected by wa. ee357_alu.v: You should have completed this design in an earlier lab. You will need to import it to your project via Project..Add Source. A function table is provided below. Be sure you completed the SLT operation near the bottom of the file. You may also modify this component if you want to implement additional instructions, but it should be sufficient for the base CPU design. Last Revised: 3/6/

3 Operation FUNC[5:] RES[3:] UOV (unsigned overflow) ADD OPA + OPB * * SUB OPA OPB * * AND OPA & OPB OR OPA OPB XOR OPA ^ OPB NOR ~(OPA OPB) SLT if OPA < OPB (signed), otherwise * * * = output as traditionally defined SOV (signed overflow) ee357_mcpu_cu.v: Skeleton file starting the design of your control unit state machine. You will need to complete this file. If you choose to implement additional instructions, you may feel free to generate new control signals or modify the current control signal outputs. Note: we have shortened some signal names from those used in the in-class slides (e.g. pcw instead of pcwrite., pcs instead of pcsource, etc.) Just be aware. Datapath Completion: You will need to add all the additional datapath logic (beyond the components provided you) such as muxes, glue logic, glue control, sign extension, temporary registers for the PC, IR, and Target register, etc. You can do this by taking a structural approach (i.e. creating other basic modules [in other files if desired] and instantiating them) or at an RTL-level (using always blocks and assign statements to describe the desired operations. The basic datapath considered in class is shown in Figure 3. You will need to consider additional functionality needed for the ADDI instruction. Control Unit Completion: You will implement the FSM (finite state machine) to generate appropriate control signals for fetch, decode, and instruction execution states. The basic control unit is shown in Figure. Additional states for the ADDI instruction may need to be added. When you complete the control unit you can choose an encoded style implementation or a one-hot implementation. We have provided some opcode declaration/constant (OP_LW, OP_SW, OP_RTYPE, etc.) that will help you decode instruction opcodes to choose the next state to transition to after the decode state. Use these as desired. One important aspect of this project is the size of the memory. While your processor will implement a byte-addressable 3-bit address, we will only interface it to a much smaller 56x3 memory (i.e. 56 words) to limit the amount of initialization and make simulation faster. To this end, while your processor will generate mem_addr[3:], we will only connect 8 bits of the address to the memory (since it has 56 locations). Those 8-bits will be mem_addr[9:]. Mem_addr[:] Last Revised: 3/6/ 3

4 PC Mem Mem [5:] Reg PC MemtoReg RegDst EE 357 Project - Multicycle CPU are unneeded since we will always do word accesses. [In an actual design these bits would be converted to byte enable signals that would select the appropriate bytes from the word.] Mem. Addr. Computation Memory Access 3 Reset Instruc. Fetch Mem ALUSelA= IorD= IR ALUSelB= ALUOp= PCSource= PC Instruc. Decode + Reg. Fetch ALUSelA= ALUSelB= ALUOp= IorD= Mem ALUSelA= ALUSelB= ALUOp= IorD= Memory Access Execution -back 5 Mem ALUSelA= ALUSelB= ALUOp= IorD= 7 ALUSelA= ALUSelB= ALUOp= RegDst= MemtoReg= Reg (Op= BEQ ) ALUSelA= ALUSelB= ALUOp= Target (Op= JMP ) ALUSelA= ALUSelA= ALUSelB= PC ALUSelB= ALUOp= PCSource= ALUOp= PCCond PCSource= Branch Completion (Op= ADDI ) ADDI Exec. ADDI Exec. Jump Completion -back 4 Mem ALUSelA= ALUSelB= ALUOp= IorD= MemtoReg= RegDst= Reg Figure - Multicycle CPU FSM (with dummy states for the ADDI implementation should you need them) IorD PC PCCond IR Control Unit PCSource Target ALUOp ALUSelB ALUSelA PC[3:8] Target Reg. Zero 6 3 Sh. Left 3 Addr. Data Data Memory Instruc[3:6] Instruc[5:] Instruc. Reg. [5:] [:6] [5:] Reg. # Reg. # Reg. # Data data data Register File 4 3 ALU Zero Res. [5:] Sign 6 Extend 3 Sh. Left ALU Ctrl [5:] Figure 3 Base Multicycle CPU Datapath (ADDI not considered) 4 Last Revised: 3/6/

5 Testbench and Checker: A Verilog testbench has been provided for you that will generate the rst signal and hold it active for the first few clock cycles. It also generates the clock signal. You will use Modelsim XE simulator to simulate your CPU fetching and executing instructions from memory. This requires that the memory be initialized with the machine code of some instructions before simulation begins. The memory component provided to you will initialize itself with the values in mem_file.txt in your project folder. The format of this file assumes a single 3-bit word per line, specified in hex. The provided mem_file.txt file has no instructions but does have data at line 33 and 34, which corresponds to address x8 and x84 (recall each line is a 4-byte word so the line number of the text file can be related to address via: Address = (line_no * 4) 4 [the - 4 is because the text editor starts at line while the memory starts at address ]). You will need to convert some instructions to machine code and fill in this memfile.txt by hand. The value of the PC at reset will be address, thus your instructions should start at address in memory. Note: Use the Xilinx Text Editor (File..Open..) to edit mem_file.txt and do NOT use Notepad as it handles the newline characters incorrectly. A simple program (Program ) that uses all the basic instruction classes and loops twice is provided below. Convert that program to machine code manually and enter it into the mem_file.txt to start at address. When you are done remove some lines containing s to ensure the data is still at line 33 and 34 (address x8 and x84). Use this program as an initial test to verify correct execution of your instructions. Another program is provided in mem_file_p.txt that implements a loop to sum an array of integers. It can be used as a second test of your design by copying mem_file_p.txt to mem_file.txt (the memory will always use the contents of mem_file.txt ). It would be wise to save a copy of the original memfile that contained the machine code you hand-assembled for later testing. Just rename it or copy it to another filename and then copy it back if needed. Program to be assembled by you addi $9,$,x84 xor $8,$,$ nor $8,$,$ L: lw $4,-4($9) # data at addr x8 = x lw $5,($9) # data at addr x84 = xfffffffe add $7,$4,$5 sub $8,$4,$5 and $6,$4,$5 or $6,$4,$5 slt $6,$7,$8 slt $9,$8,$ beq $9,$,L sw $6,($9) addi $8,$8, j L L: beq $,$,L # inf. loop Program in mem_file_prog.txt # assumes memory address 8-8c are # filled with an array of 4 integers. add $,$,$ # clear $ addi $,$,4 # set $ = x4 addi $8,$,x8 # setup ptr. addi $4,$,4 # set $4 = x4 addi $,$,- # set $ = - L: slt $,$,$ # comp to $ beq $,$,DONE # b if $ >= lw $6,($8) # get A[i] add $,$,$6 add $8,$8,$4 add $,$,$ j L DONE: sw $,($8) lw $3,($8) L: beq $,$,L # inf. loop Last Revised: 3/6/ 5

6 When hand-assemblying instructions, use the machine code format below: R-Type: 3:6 5: :6 5: :6 5: ADD $rd,$rs,$rt rs rt rd SUB $rd,$rs,$rt rs rt rd AND $rd,$rs,$rt rs rt rd OR $rd,$rs,$rt rs rt rd XOR $rd,$rs,$rt rs rt rd NOR $rd,$rs,$rt rs rt rd SLT $rd,$rs,$rt rs rt rd I-Type: 3:6 5: :6 5: LW $rt,disp 6 ($rs) rs rt disp 6 SW $rt,disp 6 ($rs) rs rt disp 6 ADDI $rt,$rs,imm 6 rs rt imm 6 BEQ $rs,$rt,disp 6 rs rt disp 6 *Note: BEQ adds two s to the LSB s of the displacement and adds that value to the already incremented PC (i.e. target addr. = addr. of BEQ (disp.*4) ). Make sure you remove the two s when you calculate the stored disp. value. J-Type: 3:6 5: J addr 6 addr 6 *Note: J adds two s to the LSB s of the jump address. Thus, you should store the desired address with the two s removed. When you simulate your design you will be able to see the signals that have been brought out as outputs. To determine if your design is working or not, it is likely easiest to look at the memory address, read and write values as well as register read and write values to see if they match expectation [obviously you will need to calculate the expected values from each instruction and ensure the actual values match your expectation]. Once an error is found, you can drill down into the design hierarchy in the Workspace pane to find the component and internal signals that you d like to view and drag the desired signal name to the waveform window. Restart the simulation [restart f] and re-run the simulation [run XXXns]. 6 Last Revised: 3/6/

7 To make debugging easier we have written a Verilog checker model. This checker simulates our own model of the CPU and compares it with what your design produces. If there are errors in your design some limited error messages will be output to the console area of the Modelsim window. Find the first error message and use its timestamp to view the time where your design produces an error. If there are errors in the first 3 ns you can ignore these as this is the system reset time window. Challenge Options: For additional credit, you can add an implementation for more instructions to your CPU design. This will likely entail adding to the datapath and may or may not require adding new states to the control unit (though the state sequences you have are likely generic enough for most of the instructions below). Challenge instructions are the easiest to implement while challenge instructions are harder. If you want to implement challenge instructions you must implement challenge instructions as well. [You can t just choose the hardest]. Challenge Instruction(s): I-Type: 3:6 5: :6 5: BNE $rs,$rt,disp 6 * Rs rt disp 6 R-Type: 3:6 5: :6 5: :6 5: SLL $rd,$rt,shamt Unused rt rd shamt SRL $rd,$rt,shamt Unused rt rd shamt SRA $rd,$rt,shamt Unused rt rd shamt * NO NEW states may be added to the control unit / state machine for BNE Notice the $rt field holds the register operand and shamt (shift amount) is really the second operand. When plugging these into the ALU, let rt still go to inb of the ALU and shamt should be provided to ina. All shift operations MUST write their result (regwrite) on the nd execution state (i.e. F, D, E, E). Challenge Instruction(s): J-Type: 3:6 5: JAL addr 6 addr 6 R-Type: 3:6 5: :6 5: :6 5: JR $rs rs Note: Same operation as J addr and also stores address of following instruction (i.e. PC+4) into register $3. MUST write value to $3 on st execution state (i.e. F, D, E). Note: Loads PC = $rs. Last Revised: 3/6/ 7

8 4 Prelab None. 5 Procedure. Download the ee357_mcpu_proj.zip file from Blackboard and extract the source files to a folder of your choice.. Download the ee357_mcpu_lib.zip file that contains a compiled version of the Golden model of the CPU to compare against your implementation. Be sure to download the version that matched your Modelsim version. Extract it to a folder. 3. Start ModelSim and from the File menu choose Change Directory. Browse and choose the folder where you extracted your source files (in procedure ). Do this each time you re-start the Modelsim application. 4. Using the Modelsim Editor, open the ee357_mcpu.v file (instance name uut ). It is the top-level design file which instantiates the ALU, control unit, and register file. Familiarize yourself with code provided in it. 5. Copy your completed ee357_alu.v into the project folder being sure the implementation of the all the operation is completed (especially slt ). 6. In ee357_mcpu_cu.v complete the state machine design to implement the control logic. For challenge instructions, try to reuse states where possible (i.e. where behavior is the same). 7. In ee357_mcpu.v complete the datapath of the design (adding appropriate code to model the muxes, register, glue logic, etc. 8. Hand assemble program listed earlier in this document using paper and pen. 9. Open mem_file.txt (in the File..Open Dialog, choose TXT files to find it. Type in the machine code from program for each instruction (one per line) and remove as many lines of s as you add so that the provided data is still only line 33 and 34. Save this file.. In ModelSim we need to create a logical mapping to the ee357_mcpu_lib that you downloaded that contains the compiled golden version of the CPU. In Modelsim, choose File..New..Library. Select the middle button a map to an existing library. Enter a library name of ee357_mcpu_lib and then Browse to the library folder you unzipped from step.. Compile all your Verilog design and testbench files by choosing Compile..Compile and browse to the folder with your source files. In the Library drop down box at the top of the Compile window and be sure to 8 Last Revised: 3/6/

9 change it to ee357_mcpu_lib. Select all the Verilog files and click compile. Check the transcript pane to look for errors in compiling your files. Fix them appropriately until it compiles successfully.. Simulate your design by choosing Simulation Start Simulation. Expand the ee357_mcpu_lib library and find the ee357_mcpu_tb. Select it and click OK. You can open waveform window (View..Waveform) and drag signals from the object pane into it Then run the simulation by typing run 5 ns at the prompt in the bottom transcript window. You can view the signals in the Waveform for debug purposes. 3. Modelsim will then run your design for 5 ns using the provided instructions in mem_file.txt and verify its correct operation. To do this, check the Modelsim console area for output errors from the provided checker model. Any errors before 6 ns can be ignored as this is the reset time. You should also review the resulting waveform. You can make this small window its own window by clicking the float button in the upper left. You may also want to convert wide bus signals from binary to hex (right-click and choose Radix..Hexadecimal). Note: It is likely easiest to verify the operation in the waveform by looking at the regwdata and the regwrite signals as well as the PC. Most instructions will affect a register or the PC and thus you can simply verify the result in the last state of execution. It may help to drag these signals to be next to each other on the waveform. Find any errors and deduce their cause by adding more signals to the waveform window and re-running the simulation (type: restart f followed by run 5 ns in the console area of the main Modelsim window). Fix the errors in the Xilinx design files, close Modelsim and re-run the behavioral simulation. 4. Now go to your source folder, save a copy of mem_file.txt (i.e. to mem_file_p.txt ) and copy mem_file_p.txt to mem_file.txt (Essentially, Modelsim will always use mem_file.txt as the memory image, so to run a different program we need to change its contents). This new program implements a loop to sum up a 4-element integer array starting at address x8. Simulate and run this program. Verify its correctness, fixing any errors. 5. Once both programs are working you can choose to implement any of the challenge instruction sets. We recommend saving a copy of any Verilog files you will change (ee357_mcpu.v, ee357_mcpu_cu.v, ee357_alu.v) so that you have a copy of what was working in case you are unsuccessful in adding the new instructions. A challenge program that uses the challenge instructions is provided in the source files ( memfile_challenge.txt ) though it uses both challenge and challenge instructions (i.e. if you implement only challenge instructions you will need to pull out the jal and jr instructions in that file). To figure out what instructions are coded in this program you will need to disassemble the machine code. Last Revised: 3/6/ 9

10 6 Lab Report Name(s): Score: Due: Thurs. April 9 th in lecture. (Detach and turn this sheet along with any other requested work or printouts). Our team implemented. BASE IMPLEMENTATION / CHALLENGE / CHALLENGE Electronic Submission. Submit electronic versions of your any verilog files you modified or created (likely ee357_mcpu.v, ee357_mcpu_cu.v, ee357_alu.v, and any other files you created). AT THE TOP OF ee357_mcpu.v add a comment indicating which options/challenges you implemented.. Zip (not BZIP, not WinRAR, etc.) your files into a zip file and submit the zip file via Blackboard. Hard-Copy Submission 3. Print a title sheet indicating which challenge instruction sets (if any) you chose to implement (i.e. Indicate BASE, CHALLENGE or CHALLENGE ). 4. Print the machine code for your hand-assembled program (i.e. printout just the first page of mem_file.txt we need just the instruction code and not the whole contents of memory). 5. On the datasheet scratch sheet shown on the following page, add the modifications you implemented for the ADDI instruction or any challenge instructions (e.g. needed to increase the ALUSELA mux to be a 3-to- mux with XXX as the 3 rd input.). Add a text explanation on a separate page for each modification explaining what it is for. 6. On the FSM scratch sheet shown after the datapath scratch page, show the control signals in the appropriate ADDI states that you implemented. Also, markup the state diagram or add other states to match your implementation of any challenge instructions. Last Revised: 3/6/

11 PC PC Memory Data Data Addr. Mem Mem Instruc. Reg. Instruc[5:] Instruc[3:6] [5:] Zero IR PCCond PC IorD [5:] [5:] Sign 6 Extend 3 Sh. Left ALU Ctrl Register File 3 Data 4 [5:] Reg. # data ALU Res. [:6] Reg. # data Zero Reg. # [5:] RegDst MemtoReg Reg 6 3 PC[3:8] Control Unit PCSource Target ALUOp ALUSelB ALUSelA Target Reg. Sh. Left 3 Last Revised: 3/6/

12 Instruc. Fetch Mem Instruc. Decode + ALUSelA= Reg. Fetch IorD= IR ALUSelB= ALUOp= PCSource= PC (Op= ADDI ) Reset ADDI ALUSelA= ALUSelB= ALUOp= Target Exec. (Op= JMP ) ADDI Exec. (Op= BEQ ) ALUSelA= Execution ALUSelA= ALUSelA= ALUSelB= ALUSelB= ALUSelB= ALUOp= ALUOp= ALUOp= PCCond IorD= Mem. Addr. PCSource= (Op= SW ) Computation Memory Branch Jump (Op= LW ) Access -back Completion Completion 3 Memory Access Mem ALUSelA= ALUSelB= ALUOp= IorD= 5 Mem 7 ALUSelA= ALUSelB= ALUOp= IorD= ALUSelA= ALUSelB= ALUOp= RegDst= MemtoReg= Reg PC PCSource= -back 4 Mem ALUSelA= ALUSelB= ALUOp= IorD= MemtoReg= RegDst= Reg Last Revised: 3/6/

13 7 EE 357 Project Grading Rubric Name: Score: / Req. / Guideline Base Instrucs Challenge Challenge Mult Sco re (Excellent) 6 ADD SUB AND OR SLT LW SW BEQ JMP BNE SLL SRL SRA JAL JR 8 (Good) 5 (Avg.) (Poor) () Failure / 4 / / / / 4 / 4 / 4 / / / / 4 / / 4 / / Machine Code Test Program Datapath Mods Control Unit Mods Errors Errors -3 Errors 4-5 Errors More than 5 Errors Correct additions that utilized current datapath well to arrive at minimal additions for necessary instructions State sequences correctly implemented added instructions and reused current states to a high degree Journal Carefully considered alternative approaches and described their impact on both FSM & datapath Late - per day, TOTAL max - MAX / Correct additions but did not fully utilize current datapath configuration State sequences correctly implemented added instructions but missed several reuse opportunities Considered several alternative approaches but w/o detail description of their impact Missing a major datapath component that affects a single instruction class. Missing necessary states for at least one instruction class Listed some alternatives w/ no description of impact Missing or more major datapath components that affecting several instruction classes Missing necessary states for more than one instruction class. Alternatives were incomplete or unviable. Missing Missing Missing Last Revised: 3/6/ 3