Introduction to CPU architecture using the M6800 microprocessor

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1 Introduction to CPU architecture using the M6800 microprocessor Basics Programs are written in binary object codes which could be understood (after the decoding process) by the designated target CPU. The programs are stored in main memory (RAM) to allow the CPU to read. Even the programs are originally stored in disk files, they must first be loaded into memory before reading by the CPU. Fetch-decode-execute cycle Fetch After object codes are loaded into memory, CPU will read in the codes one by one from the memory. This is called the Fetch process. Decode Then it decodes the fetched object code and tries to understand the code inside the CPU. Execute After decoding, it executes the instruction accordingly. This is called the Execute process. The above Fetch-decode-execute cycle will go on until the end of the program. Some basic parts inside CPU Regarding the above cycle, write down the operation sequence involving the following: Memory Address Register Or Address Buffer (MAR) Program Counter (PC) Memory Data Register (MDR) Or Data Buffer (MAR) Address Bus (AB) Data Bus (DB) Instruction Register (IR)

Functionalities of the above parts Pc stores the next fetch address. Fetch MAR receives the address from PC and prepare it for address bus Address Bus connects the address to external devices e.g.

2 Functionalities of the above parts Pc stores the next fetch address. Fetch MAR receives the address from PC and prepare it for address bus Address Bus connects the address to external devices e.g. RAM Data Bus transfer data to/from external devices MDR stores the data from data bus Decode IR receives fetched data from MDR and decodes the data (recognize the instruction) Execute Then the CPU will execute the decoded instruction. Visit the on-line M6800 (Motorola 6800 CPU) Screen Layout Assembly language program Main memory CPU internal structure Operation procedures Operation panel 1. Put in the assembly language source program.

2. In Operation panel, press Assemble to start assembling the source program. If no error, the program binary object code will be produced and stored in the Main Memory. 3.

3 2. In Operation panel, press Assemble to start assembling the source program. If no error, the program binary object code will be produced and stored in the Main Memory. 3. Press Step in Operation panel to trace the data paths. Activity A 1. Put in the Assembly language: LDAA #100.org 0C Press Assemble 3. Check if Main Memory would like the following. Note: In M6800 CPU, the program binary code of LDAA (immediate mode) is 86(hex) and it is stored in location address C000(hex) which is instructed by the command.org (means origin). #100 means the immediate data is 100(denary) or 64(hex). It is stored in the next memory location C001(hex). 4. Now press Step and observe the data flow. 5. Answer the following questions.

4 Questions 1. Regarding the data flow among the CPU components, which of the following is the right sequence? Note: PC Program Counter, MAR Memory Address Register, MDR Memory Data Register, AB Address Bus, DB Data Bus, IR Instruction Register A. PC MAR AB DB MDR IR B. AB DB MDR IR PC MAR C. DB MDR IR PC AB MAR D. MAR PC AB DB MDR IR Ans: PC MAR AB DB MDR IR 2. Which of the following is correct? A. Fetch Execute Decode B. Decode Fetch Execute C. Execute Fetch Decode D. Fetch Decode Execute Ans: Fetch Decode Execute 3. Considering about CPU Decode operations, which of the following is correct? A. It is done inside Program Counter. B. It is done inside Instruction Register. C. It is done inside Accumulator. D. It is done inside Memory Registers. Ans: It is done inside Instruction Register. 4. In a program statement, it usually involves instruction and data, e.g. load the value 100 into Accumulator A (in M6800, it is LDAA #100). Which of the following is correct? A. LDAA is data, 100 is instruction. B. LDAA is instruction, 100 is data. C. Both are instructions. D. Both are data. Ans: LDAA is instruction, 100 is data.

5 5. The above LDAA (note: immediate mode) is code 86(hex), 100 is code 64(hex). That is to say, will be stored in two consecutive memory location addresses, e.g. C000(hex) and C001(hex) respectively in our activity. Hence, the address size and data size will be: A. 16 bits, 16 bits B. 8 bits, 8 bits C. 16 bits, 8 bits D. 8 bits, 8 bits Ans: 16 bits and 8 bits. 6. Hence the address range will be A. 2 4 B. 2 8 C D Ans: 2 16 = 65536, i.e. from 0000(hex) to FFFF(hex) 7. After the first Fetch-Decode-Execute cycle, code 86 in address C000(hex) is loaded into CPU. Which of the following does best describe the next operation on reading code 64? A. CPU will guess the next code and need not do anything. B. CPU will always start another Fetch Decode Execute cycle to read in the 2 nd code in the next address (i.e. current address+1). C. Depending on the previous code, after decoding, CPU will decide the next upcoming address to load. If it is a Jump instruction or a Branch instruction, the next address will be very different to the current one. D. Each Fetch Decode Execute cycle will read in the whole program and it needs not read in statement by statement. Ans: Depending on the previous code, after decoding, CPU will decide the next upcoming address to load. If it is a Jump instruction or a Branch instruction, the next address will be very different to the current one. 8. What will be the execution result of LDAA #100? A. 64(hex) will be stored in PC. B. 86(hex) will be stored in IR. C. 64(hex) will be stored in IR. D. 64(hex) will be stored in Accumulator A.

6 Ans: 64(hex) will be stored in Accumulator A. Activity B 1. Put in the Assembly language: LDAA #100 CLRA.org 0C Press Assemble 3. Press Run and Observe the effect of the extra CLRA (Clear Accumulator A) command. Answer the following questions: 1. What is the usage of ALU? Ans: ALU is Arithmetic and Logic Unit. It is for doing calculations in CPU. It works closely with Accumulator. Under the Clear command, content of Accumulator will first load into ALU, then inside, it is cleared to zero. Then the zero value will be loaded into Accumulator again. 2. What is the result of CCR? Which bit among HINZVC is set? Ans: CCR is the Condition Code Register which reflects the conditions inside Accumulators for many instructions like branch and jump instructions. When the Accumulator is zero after the CLR command, the Zero flag (Z) will be set to 1. Further reading: Basic Microprocessors and the 6800 By Ron Bishop 1979

CPU ARCHITECTURE. QUESTION 1 Explain how the width of the data bus and system clock speed affect the performance of a computer system.

CPU ARCHITECTURE. QUESTION 1 Explain how the width of the data bus and system clock speed affect the performance of a computer system. CPU ARCHITECTURE QUESTION 1 Explain how the width of the data bus and system clock speed affect the performance of a computer system. ANSWER 1 Data Bus Width the width of the data bus determines the number