IF1/IF2. Dout2[31:0] Data Memory. Addr[31:0] Din[31:0] Zero. Res ALU << 2. CPU Registers. extension. sign. W_add[4:0] Din[31:0] Dout[31:0] PC+4
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1 12 1 CMPE110 Fall 2006 A. Di Blas 110 Fall 2006 CMPE pipeline concepts Advanced ffl ILP ffl Deep pipeline ffl Static multiple issue ffl Loop unrolling ffl VLIW ffl Dynamic multiple issue Textbook Edition: 6.8, 6.9 Second Third Edition: 6.9, 6.10
2 1) Increase the pipeline depth 12 3 CMPE110 Fall 2006 A. Di Blas Instruction-level parallelism (ILP): deep pipeline Exploit the parallelism among instructions. Two ways: What is the advantage?
3 1 0 IF1/IF2 IF2/ID ID/EX EX/MEM1 MEM1/MEM2 MEM2/WB + PC PC Addr[31:0] Instruction Memory Dout[31:0] R_add1[4:0] R_add2[4:0] W_add[4:0] Din[31:0] Dout1[31:0] Dout2[31:0] CPU Registers 0 1 << 2 Zero Res ALU Addr[31:0] Din[31:0] Data Memory Dout[31:0] 1 0 sign extension CMPE110 Fall 2006 A. Di Blas Example of deeper pipeline Increasing the size of the caches: ffl improves hit rate ffl makes the caches slower Solution: pipeline cache access
4 2) Multiple issue 12 5 CMPE110 Fall 2006 A. Di Blas Instruction-level parallelism (ILP): multiple issue ffl IPC ffl Static vs Dynamic multiple issue
5 12 6 CMPE110 Fall 2006 A. Di Blas Issues with...multiple issue ffl Packing the issue slot n 1 0 Unit 1 Unit 2 Unit 3
6 12 7 CMPE110 Fall 2006 A. Di Blas Issues with...multiple issue ffl Dealing with data and control hazards IF ID EX MEM WB What about structural hazards? (RF)
7 Static multiple issue 0 << IF/ID ID/EX EX/MEM MEM/WB + PC+8 PC 8 A[31:0] DA[31:0] Radd1A[4:0] Dout1A[31:0] DinA[31:0] WaddA[4:0] Radd2A[4:0] CPU Registers Dout2A[31:0] 0 1 Zero Res ALU Data Memory DM[31:0] Radd1M[4:0] DinM[31:0] WaddM[4:0] Radd2M[4:0] Dout[31:0] + Addr[31:0] sign extension sign extension Din[31:0] 0 1 ffl instructions are paired on 64-bit boundaries, ALU first ffl expand and/or add harware ffl hazards compiler or hardware? intra and inter dependencies ffl problem with loads 12 8 CMPE110 Fall 2006 A. Di Blas Example: static dual-issue pipeline for MIPS
8 Code scheduling: Example a a Second Ed. p. 513, Third Ed. p CMPE110 Fall 2006 A. Di Blas Schedule this loop on the static two-issue MIPS pipeline on page Loop: lw $t0, 0($s1) # $t0 = array element addu $t0, $t0, $s2 # add scalar in $s2 sw $t0, 0($s1) # store result addi $s1, $s1, -4 # decrement pointer bne $s1, $zero, Loop # branch if $s1!= 0 Label ALU/branch instruction Memory instruction Clock cycle
9 12 10 CMPE110 Fall 2006 A. Di Blas Loop unrolling Compiler optimization technique: replicate the body of a loop multiple times to execute the transformed loop fewer times. ffl reduces loop overhead in any case ffl exposes more ILP ffl generally requires register renaming Register renaming ffl eliminates dependencies that are not true dependencies ffl allows rearrangement of the code preserving program correctness In our example, ffl assume that the loop counter is a multiple of 4 ffl assume that additional registers ($t1, $t2, $t3) are available
10 12 11 CMPE110 Fall 2006 A. Di Blas First step: Unroll the loop by 4 1 Loop: lw $t0, 0($s1) 2 addu $t0, $t0, $s2 3 sw $t0, 0($s1) 4 addi $s1, $s1, -4 5 lw $t0, 0($s1) 6 addu $t0, $t0, $s2 7 sw $t0, 0($s1) 8 addi $s1, $s1, -4 9 lw $t0, 0($s1) 10 addu $t0, $t0, $s2 11 sw $t0, 0($s1) 12 addi $s1, $s1, lw $t0, 0($s1) 14 addu $t0, $t0, $s2 15 sw $t0, 0($s1) 16 addi $s1, $s1, bne $s1, $zero, Loop
11 Second step: Adjust the loop counter (and whatever depends on it...) CMPE110 Fall 2006 A. Di Blas 1 Loop: lw $t0, 0($s1) 2 addu $t0, $t0, $s2 3 sw $t0, 0($s1) 4 addi $s1, $s1, -4 5 lw $t0, 0($s1) 6 addu $t0, $t0, $s2 7 sw $t0, 0($s1) 8 addi $s1, $s1, -4 9 lw $t0, 0($s1) 10 addu $t0, $t0, $s2 11 sw $t0, 0($s1) 12 addi $s1, $s1, lw $t0, 0($s1) 14 addu $t0, $t0, $s2 15 sw $t0, 0($s1) 16 addi $s1, $s1, bne $s1, $zero, Loop
12 12 13 CMPE110 Fall 2006 A. Di Blas Third step: Rename the registers 1 Loop: lw $t0, 0($s1) 2 addu $t0, $t0, $s2 3 sw $t0, 0($s1) 5 lw $t0, -4($s1) 6 addu $t0, $t0, $s2 7 sw $t0, -4($s1) 9 lw $t0, -8($s1) 10 addu $t0, $t0, $s2 11 sw $t0, -8($s1) 13 lw $t0, -12($s1) 14 addu $t0, $t0, $s2 15 sw $t0, -12($s1) 16 addi $s1, $s1, bne $s1, $zero, Loop
13 12 14 CMPE110 Fall 2006 A. Di Blas Fourth step: Schedule the code Loop: lw $t0, 0($s1) addu $t0, $t0, $s2 sw $t0, 0($s1) lw $t1, -4($s1) addu $t1, $t0, $s2 sw $t1, -4($s1) lw $t2, -8($s1) addu $t2, $t0, $s2 sw $t2, -8($s1) lw $t3, -12($s1) addu $t3, $t0, $s2 sw $t3, -12($s1) addi $s1, $s1, -16 bne $s1, $zero, Loop Label ALU/branch instruction Memory instruction CC
14 12 15 CMPE110 Fall 2006 A. Di Blas VLIW and EPIC ffl Who schedules the instructions? When it is the compiler, the architecture is called VLIW: Very Long Instruction Word. ffl Intel's IA-64 architecture is almost VLIW, and they call it EPIC: Explicitly Parallel Instruction Computer. ffl Instruction bundles, 128-bit long: 5-bit template field, and three 41-bit instructions. ffl Instruction group: sequence of consecutive instructions with no register data dependency among them they could be all executed in parallel (in principle). The compiler places stops between groups. ffl NOTE: IA-64 architecture is different from Intel-64 architecture, which is just an extension to the IA-32 architecture (!).
15 predicate. Example: without predication, this code requires a branch CMPE110 Fall 2006 A. Di Blas Predication Eliminate branches by making individual instructions dependent on a if(p) else statement1; statement2; With predication, both statements are issued, but only one will execute: (p) statement1; (~p)statement2;
16 Dynamic issue: stall on hazards Dynamic scheduling: choose which instructions to execute and when CMPE110 Fall 2006 A. Di Blas Dynamic multiple-issue INSTRUCTION FETCH INSTRUCTION DECODE RESERVATION STATION RESERVATION STATION RESERVATION STATION RESERVATION STATION INTEGER UNIT 1 INTEGER UNIT 2 LOAD/STORE UNIT FLOATING POINT UNIT COMMIT UNIT REORDER BUFFER
17 Summary a a From Hennessy, Patterson Computer Architecture A Qantitative Approach, 3rd ed. p CMPE110 Fall 2006 A. Di Blas Hazard Distinguishing Name Issue detection Scheduling characteristic Examples Superscalar dynamic hardware static in-order execution Sun UltraSPARC II/III (static) Superscalar dynamic hardware dynamic some out-of-order IBM Power2 (dynamic) execution Superscalar dynamic hardware dynamic with out-of-order with Pentium 3/4, MIPS R10K, (speculative) speculation speculation Alpha 21264, HP PA 8500 VLIW/LIW static software static no hazards between Trimedia, i860 issue packets EPIC mostly mostly mostly explicit dependencies Itanium static software static marked by compiler
18 12 19 CMPE110 Fall 2006 A. Di Blas Recommended exercises ffl Second Ed.: 6.30 ffl Third Ed.: 6.47 (equiv. to second ed.'s 6.30), 6.49
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