Microcontroller Systems

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1 µcontroller systems 1 / 43 Microcontroller Systems Engineering Science 2nd year A2 Lectures Prof David Murray david.murray@eng.ox.ac.uk dwm/courses/2co Michaelmas 2014

2 µcontroller systems 2 / 43 Lecture 2 The, Instruction Fetch & Execute Introduction A Bog Standard Architecture The flow of information Starting the processing: Fetching an instruction A few instructions Executing an instruction

3 µcontroller systems 3 / 43 At the end of the first lecture we introduced the von Neumann architecture we suggested that special instruction data might be read from a memory into the data section, then passed to the control section change the transfer function of the data section. In this lecture we see that idea realized in the architecture for a simple central processing unit (). Rather than introduce individual components one by one, we ll dive in at the deep end and revealing our Bog Standard Architecture.

4 µcontroller systems 4 / 43 Our Bog Standard Architecture to Registers,,, etc The contains registers,,,,, an arithmetic logic unit () a control unit () internal data pathways Outside the connected to by an address bus a data bus

5 µcontroller systems 5 / 43 Registers to Registers,,, etc Outside the The Buffer Register stores information that is being sent to, or received from, the memory along data bus. The Accumulator is used to store data that is being worked on by the. The key register in the data section of the cpu.

6 µcontroller systems 6 / 43 Registers to Registers,,, etc Outside the The Address Register is used to store the address to access memory. The Program Counter holds the address in memory of the next program instruction. The is a register & counter. The Stack Pointer hold the address of part of main memory used for temporary storage

7 µcontroller systems 7 / 43 Registers to Registers,,, etc Outside the If the data read from memory is an instruction it gets moved to the Instruction Register. It has two parts: (opcode) The most significant bits of the instruction tell the cpu what to do. It is decoded by the. (address) The least significant bits are actually data. They get moved to (address). They usually form all or part of an address for later use in the.

8 µcontroller systems 8 / 43 Register types Registers,,, are just row of D-type latches sharing a common CLK input providing temporary storage on the. Because these registers output onto buses they have tri-state buffers are connected to a single input OE (Output Enable). Here they are falling edge-triggered (inverter on the CLK input). D7 D6 D0 D Q D Q D Q CLK OE O7 O6 O0 The can be incremented like a counter, or loaded like a register. If INCpc=1, the clock pulse increments, but if INCpc=0 it loads. The can be incremented, decremented, or loaded like a register.

9 µcontroller systems 9 / 43 Units in the to Registers,,, etc Outside the The Control Unit is responsible for timing the register transfers required to fetch and execute each instruction. It has a number of control lines coming out of it, which transmit CSL and C levels and pulses to the various registers,, etc

10 µcontroller systems 10 / 43 Units in the to Registers,,, etc Outside the The Arithmetic Logic Unit is responsible for bit operations on data held in the and. Contains full adders, logical AND-ers and OR-ers, etc. Collection of 1bit flags Carry C, Overflow V, negative N, and zero Z that indicate the outcome of operations that the has just carried out. The flags are monitored by the.

11 µcontroller systems 11 / 43 Data bus & data register widths : While s use 32 or 64 bits, microcontrollers have data bus widths of 4 bits, 8-bits, 16-bits and 32-bits. to Registers,,, etc Outside the Let s assume that the memory is 16 bits or 2 Bytes wide and that the data bus is also 16 bits wide. The and registers on the data side of the will therefore be 16 bits wide

12 µcontroller systems 12 / 43 Address bus & register widths : n lines can address 2 n locations. Intel 8086 (1979): n = 20 Pentium (2009): n = Microcontrollers haves smaller main memories, and n = 18 ( 256k locations) is largest. to Registers,,, etc Outside the But it is convenient here (i) to have different numbers on the address and data side, and (ii) to keep things in multiple of 8 Let s assume a 24 bit address bus The,, and in our cpu will therefore be 24 bits wide.

13 µcontroller systems 13 / 43 Width of the Instruction Register The (opcode) part should be wide enough to take the largest opcode. We will assume the opcode is a fixed 8 bits wide, allowing 256 different instructions which is plenty. to Registers,,, etc Outside the The (address) part has to have the same width as the address bus, 24 bits. So the whole is 32 bits wide. It is however fed from the internal data bus which is only 16 bits wide in our architecture. We will return to solve this conundrum later.

14 µcontroller systems 14 / 43 Brief introduction to the Main memory 24bit Address 0xFFFFFF x Contents 0x3FC9 0x01FF 0x9A76 0x0001 0x0000 0x3FC9 16 bits wide The main memory does not reside in the cpu chip but is connected to the cpu via an external data bus address bus, and control bus (not shown yet). The memory will comprise mostly random access memory (RAM) with some additional read-only memory (ROM) to help the machine start up. The address bus has been chosen to be 24 bits wide, so the address space is from 0x0 to (2 24 1) or 0xFFFFFF in hex. The data bus is here 16 bits 2 B wide, and so too are the contents.

15 µcontroller systems 15 / 43 Trivia... When calculating address space sizes, remember that 2 10 = n = 10, 20, 30 lines 1k,1M,1G locations NB! 1k locations does not mean that the memory has size 1kB. The memory size in Bytes is No. of locations with physical memory Width in Bytes. What is the maximum size of our memory? What is the largest +ve integer that can be held in it? (Use unsigned arithmetic.) Suppose all address lines are zero except A23, A22, A15, A13, A8, A1, and A0. What is the address in hex? Lines A23-A20 A19-A16 A15-A12 A11-A8 A7-A4 A3-A0 Binary x

16 µcontroller systems 16 / 43 Trivia When calculating address space sizes, remember that 2 10 = n = 10, 20, 30 lines 1k,1M,1G locations NB! 1k locations does not mean that the memory has size 1kB. The memory size in Bytes is No. of locations with physical memory Width in Bytes. What is the maximum size of our memory? 32 MB What is the largest +ve integer that can be held in it? (Use unsigned arithmetic.) = Suppose all address lines are zero except A23, A22, A15, A13, A8, A1, and A0. What is the address in hex? Lines A23-A20 A19-A16 A15-A12 A11-A8 A7-A4 A3-A0 Binary x C 0 A 1 0 3

17 µcontroller systems 17 / 43 Notation for reading, writing is just a large collection of registers, each with its own address which is selected by the number in the Reading and writing involves register transfers. to Registers,,, etc To read from memory the register transfer is To write to memory the rt is read from memory into write into memory means the memory location addressed by the Outside the

18 µcontroller systems 18 / 43 OK... What are we trying to do? With the structure of registers, units, memory and buses wired up and assuming our program of instructions is stored in memory we remind ourselves that the overall aim is... to work through the program by repeatedly (until we reach a halt) Fetching the next instruction from memory Decoding it that is, figuring out which instruction it is Executing that instruction These three will involve little more than moving words of data from memory to registers, and between registers, sometimes passing data through the, and then stuffing it back into the memory all in some nicely ordered sequence.

19 µcontroller systems 19 / 43 OK... What are we trying to do? A useful analogy is that we are playing trains" with words of information. The control unit issues the proper sequence of 1 Levels, to establish the route from source register to destination register 2 Pulses, to send the word to its destination

20 µcontroller systems 20 / 43 Fetching an instruction To start processing, the cpu needs to fetch the next instruction from the main memory. At any time, the holds the address of the next program instruction in memory. So the very first step is Copy the into the memory address register: Now read the memory (this leaves the unaltered) Now copy the instruction to the At the same time, we do a touch of housekeeping. The next instruction is likely to be in the next highest memory location, so Increment the program counter! +1

21 µcontroller systems 21 / 43 Summary of instruction fetch to Registers,,, etc ; Then decode opcode Outside the

22 µcontroller systems 21 / 43 Summary of instruction fetch to Registers,,, etc ; Then decode opcode Outside the

23 µcontroller systems 21 / 43 Summary of instruction fetch to Registers,,, etc ; Then decode opcode Outside the

24 µcontroller systems 21 / 43 Summary of instruction fetch to Registers,,, etc ; Then decode opcode Outside the

25 µcontroller systems 22 / 43 A small instruction set LDA, etc, are assembler language mnemonics. Inst Overall RT Opcode Meaning HALT Stop the clock LDA x x Load with contents of mem address x STA x x Store in memory at address x ADD x + x Add mem contents at x to AND x = x Logical and... JMP x x Jump to instruction at address x BZ x if Z=1 x if Z-flag is set then jump NOT Two s complement the SHR RShift() Shift the 1bit to right There is no universal architecture there is no standard set You do not have to learn any specific assembler language, but you should feel comfortable with the interpretation of any.

26 µcontroller systems 23 / 43 Instruction execution: LDA x Inst Overall RT Opcode Meaning LDA x x Load with contents of mem address x During the instruction fetch the opcode is transferred to the (opcode); and the operand x is transferred to (address). The operand is data that is bound into the instruction 6 instructions in the small set have operands. The overall effect of LDA x is x

27 µcontroller systems 24 / 43 Instruction execution: LDA x to Registers,,, etc 10. (address) ; (S fetch ) Outside the

28 µcontroller systems 24 / 43 Instruction execution: LDA x to Registers,,, etc 10. (address) ; (S fetch ) Outside the

29 µcontroller systems 24 / 43 Instruction execution: LDA x to Registers,,, etc 10. (address) ; (S fetch ) Outside the

30 µcontroller systems 25 / 43 Notes LDA x 10. (address) ; (S fetch ) 1 No computation has be been done by this instruction! Information has been moved around from memory to accumulator, but not altered. The only part of the cpu that can alter data is the. 2 For reasons that become clear later, we have given the execution phase an RTL starting step of (S fetch ) means goto the start of the next fetch. As the instruction fetch started at RTL step 1, (S fetch ) could be written as (1).

31 µcontroller systems 26 / 43 LDA x Fetch and Execute to Registers,,, etc ; Then decode opcode 10. (address) ; (S fetch ) Outside the

32 µcontroller systems 26 / 43 LDA x Fetch and Execute to Registers,,, etc ; Then decode opcode 10. (address) ; (S fetch ) Outside the

33 µcontroller systems 26 / 43 LDA x Fetch and Execute to Registers,,, etc ; Then decode opcode 10. (address) ; (S fetch ) Outside the

34 µcontroller systems 26 / 43 LDA x Fetch and Execute to Registers,,, etc ; Then decode opcode 10. (address) ; (S fetch ) Outside the

35 µcontroller systems 26 / 43 LDA x Fetch and Execute to Registers,,, etc ; Then decode opcode 10. (address) ; (S fetch ) Outside the

36 µcontroller systems 26 / 43 LDA x Fetch and Execute to Registers,,, etc ; Then decode opcode 10. (address) ; (S fetch ) Outside the

37 µcontroller systems 26 / 43 LDA x Fetch and Execute to Registers,,, etc ; Then decode opcode 10. (address) ; (S fetch ) Outside the

38 µcontroller systems 26 / 43 LDA x Fetch and Execute to Registers,,, etc ; Then decode opcode 10. (address) ; (S fetch ) Outside the

39 µcontroller systems 27 / 43 Where were we? We learned that the elemental f i in O = f i (I) are instructions We learned that instructions have 3 phases fetch, decode and execute Instructions always have an opcode and (often) an operand That a binary opcode can be referred to by an assembler language mnemonic Inst Overall RT Opcode Meaning HALT Stop the clock LDA x x Load with contents of mem address x STA x x Store in memory at address x ADD x + x Add mem contents at x to AND x = x Logical and... JMP x x Jump to instruction at address x BZ x if Z=1 x if Z-flag is set then jump NOT Two s complement the SHR RShift() Shift the 1bit to right The overall RT in the execute phase has to be broken down into a set of actual RTs.

40 µcontroller systems 28 / 43 LDA x Fetch and Execute to Registers,,, etc ; Then decode opcode 10. (address) ; (S fetch ) Outside the

41 µcontroller systems 28 / 43 LDA x Fetch and Execute to Registers,,, etc ; Then decode opcode 10. (address) ; (S fetch ) Outside the

42 µcontroller systems 28 / 43 LDA x Fetch and Execute to Registers,,, etc ; Then decode opcode 10. (address) ; (S fetch ) Outside the

43 µcontroller systems 28 / 43 LDA x Fetch and Execute to Registers,,, etc ; Then decode opcode 10. (address) ; (S fetch ) Outside the

44 µcontroller systems 28 / 43 LDA x Fetch and Execute to Registers,,, etc ; Then decode opcode 10. (address) ; (S fetch ) Outside the

45 µcontroller systems 28 / 43 LDA x Fetch and Execute to Registers,,, etc ; Then decode opcode 10. (address) ; (S fetch ) Outside the

46 µcontroller systems 28 / 43 LDA x Fetch and Execute to Registers,,, etc ; Then decode opcode 10. (address) ; (S fetch ) Outside the

47 µcontroller systems 28 / 43 LDA x Fetch and Execute to Registers,,, etc ; Then decode opcode 10. (address) ; (S fetch ) Outside the

48 µcontroller systems 29 / 43 Example of LDA x fetch and execute In the example, the instruction is found in memory location 2, and the instruction itself is LDA 5. 2? don t care don t care don t care don t care??? LDA x So, < (address) < M<>? <

49 µcontroller systems 29 / 43 Example of LDA x fetch and execute In the example, the instruction is found in memory location 2, and the instruction itself is LDA don t care don t care don t care don t care??? LDA x So, < (address) < M<>? <

50 µcontroller systems 29 / 43 Example of LDA x fetch and execute In the example, the instruction is found in memory location 2, and the instruction itself is LDA don t care 2 3 don t care don t care 0 don t care?? LDA x So, < (address) < M<> <?

51 µcontroller systems 29 / 43 Example of LDA x fetch and execute In the example, the instruction is found in memory location 2, and the instruction itself is LDA don t care 3 3 don t care don t care 0 don t care (opcode) (address) LDA x So, < (address) < M<> <?

52 µcontroller systems 29 / 43 Example of LDA x fetch and execute In the example, the instruction is found in memory location 2, and the instruction itself is LDA don t care 3 3 don t care don t care 0 don t care (opcode) (address) LDA x So, < (address) < M<> <?

53 µcontroller systems 29 / 43 Example of LDA x fetch and execute In the example, the instruction is found in memory location 2, and the instruction itself is LDA don t care 3 3 don t care don t care 0 don t care (opcode) (address) LDA x So, < (address) < M<> <?

54 µcontroller systems 29 / 43 Example of LDA x fetch and execute In the example, the instruction is found in memory location 2, and the instruction itself is LDA don t care 3 3 don t care don t care 0 don t care (opcode) (address) LDA x So, < (address) < M<> <?

55 µcontroller systems 29 / 43 Example of LDA x fetch and execute In the example, the instruction is found in memory location 2, and the instruction itself is LDA don t care 3 3 don t care don t care 0 don t care (opcode) (address) LDA x So, < (address) < M<> < 0x020F (or 527 decimal)

56 µcontroller systems 30 / 43 STA x (Store in memory location x) Every instruction fetch is the same: reminder... to Registers,,, etc ; Then decode opcode Outside the

57 µcontroller systems 30 / 43 STA x (Store in memory location x) Every instruction fetch is the same: reminder... to Registers,,, etc ; Then decode opcode Outside the

58 µcontroller systems 30 / 43 STA x (Store in memory location x) Every instruction fetch is the same: reminder... to Registers,,, etc ; Then decode opcode Outside the

59 µcontroller systems 30 / 43 STA x (Store in memory location x) Every instruction fetch is the same: reminder... to Registers,,, etc ; Then decode opcode Outside the

60 µcontroller systems 31 / 43 Execute STA x (Store in memory location x) Overall effect is x the reverse of LDA x. to NoOP to Registers,,, etc Outside the 13. (address); 14. ; (S fetch ) (Note: Here we can do 2 transfers at the same time...)

61 µcontroller systems 31 / 43 Execute STA x (Store in memory location x) Overall effect is x the reverse of LDA x. to Registers,,, etc Outside the 13. (address); 14. ; (S fetch ) (Note: Here we can do 2 transfers at the same time...)

62 µcontroller systems 32 / 43 ADD x (Add contents of location x to the ) to Registers,,, etc This instruction involves the. 15. (address) ; (S fetch ) Outside the

63 µcontroller systems 32 / 43 ADD x (Add contents of location x to the ) to Registers,,, etc This instruction involves the. 15. (address) ; (S fetch ) Outside the

64 µcontroller systems 32 / 43 ADD x (Add contents of location x to the ) to ADD to Registers,,, etc This instruction involves the. 15. (address) ; (S fetch ) Outside the

65 µcontroller systems 33 / 43 AND x (AND contents of location x to the ) to Registers,,, etc This instruction again involves the. 18. (address) ; (S fetch ) Outside the

66 µcontroller systems 33 / 43 AND x (AND contents of location x to the ) to Registers,,, etc This instruction again involves the. 18. (address) ; (S fetch ) Outside the

67 µcontroller systems 33 / 43 AND x (AND contents of location x to the ) to AND to Registers,,, etc This instruction again involves the. 18. (address) ; (S fetch ) Outside the

68 µcontroller systems 34 / 43 JMP x (Unconditional branch) opcode operand opcode operand opcode operand x Loc+1 Loc to Registers,,, etc Outside the JMP x jumps or branches unconditionally to instruction at x 21. (address); (S fetch ) always incremented during the fetch cycle but then overwritten with x

69 µcontroller systems 35 / 43 BZ x Branch if Zero jumps if the Z flag is 1. Yes, there are BNZ, BN, BNN, BV, BNV, BC, BNC instructions too! 22. (Z)/(S fetch ) 23. (address); (S fetch ) Z flag to Registers,,, etc Outside the

70 µcontroller systems 35 / 43 BZ x Branch if Zero jumps if the Z flag is 1. Yes, there are BNZ, BN, BNN, BV, BNV, BC, BNC instructions too! 22. (Z)/(S fetch ) 23. (address); (S fetch ) to Registers,,, etc Outside the

71 µcontroller systems 36 / 43 NOT NOT complements (inverts) the contents of the. An operation, so we need a level to configure the. 24. ; (S fetch ) to CoMPlement to Registers,,, etc Outside the

72 µcontroller systems 37 / 43 SHR SHR RightShifts the contents of the. An operation, so we need a level to configure the. 25. RightShift; (S fetch ) to RightSHift to Registers,,, etc Outside the

73 µcontroller systems 38 / 43 Decoding the opcode Earlier on, when discussing the Instruction Fetch, we wrote 4. Then decode opcode (opcode) 8 Suppose we have hardware see the picture that outputs LDA=1 and STA=0, ADD=0, etc, when the opcode is LDA, and similarly for other opcodes. What s this? We could write the the decoding phase using RTL s conditional goto: AND ADD STA LDA Decoding (this is RTL) 4. (LDA,STA,ADD,AND,..., SHR,HALT)/(10,13,15,18,...,25,99) HALT We ll see all the hardware to do this soon. But now let s use decoding to solve a problem we had with the...

74 µcontroller systems 39 / 43 Using decoding to solve a conundrum In our standard architecture, the and data bus are 16 bits wide. Hence, can only supply the 8 bit opcode with an 8 bit operand, like this Loc+1 Loc bits (23 16) bits (15 8) bits (7 0) (opcode) (address) If operands were only 8 bits long, we could only access 256 of our 2 24 addresses, which is useless! How can we fill the operand up to its full 24 bits?

75 µcontroller systems 40 / 43 Make an additional read of memory... Those opcodes that require a full length operand can make an additional read of memory Loc+1 Loc bits (23 16) bits (15 8) bits (7 0) (opcode) (address) This comes after the opcode is decoded (obviously!) but before the execution. It would pull in an extra 2 Bytes.

76 µcontroller systems 41 / 43 The RTL to make this work In our set of opcodes, LDA, STA, ADD, AND, JMP, and BZ require an extra read to obtain their 3 Byte operands. The Fetch and Decoding phases become... Instruction fetch with extra memory read after first decode (opcode) and (bits of address) ; (NOT,SHR,...)/(24,25,...) //Ie, all that don t need extra [23:8] ; (LDA,STA,...)/(10,13,...) //Ie, all that do need extra

77 µcontroller systems 42 / 43 Having sorted that out... The detail of this step is often missed out in text books, and it is assumed that the fetch (lines 1-3) provides an operand of full length. We too will neglect the problem unless explicitly asked to worry about it!

78 µcontroller systems 43 / 43 Summary: In lecture 2 we have described the in terms of its data registers and control unit, the alu and memory.... learned how an instruction is fetched from memory, and how its opcode reaches the control unit... seen the execute phases of number of different instructions... seen how the fetch and executes are defined (for the most part) by a succession of register transfers

A3 Computer Architecture

A3 Computer Architecture Engineering Science 3rd year A3 Lectures Prof David Murray david.murray@eng.ox.ac.uk www.robots.ox.ac.uk/ dwm/courses/3co Michaelmas 2000 1 / 1 2: Introduction to the CPU 3A3 Michaelmas