Graduate Institute of Electronics Engineering, NTU Design of Datapath Controllers

Transcription

1 Design of Datapath Controllers Lecturer: Wein-Tsung Shen Date: ACCESS IC LAB

2 Outline Sequential Circuit Model Finite State Machines Useful Modeling Techniques pp. 2

3 Model of Sequential Circuits Modeling system outputs depend not only on current input Depend on inputs Depend on current state Fundamental components Combinational circuits Memory elements Inputs Combinational Logic Outputs Current State Memory Elements Next State clock pp. 3

4 Types of Memory Elements Flip-Flop Latch Registers Others Register Files Cache Flash memory ROM RAM pp. 4

5 D-FF vs. D-Latch D FF is edge sensitive (can be either positive or negative edge) At trigger edge of clock, input transferred to output Latch is level sensitive (can be either active-high or active-low) When clock is active, input passes to output (transparent) When clock is not active, output stays unchanged in out in D Q clk D Q FF clk Latch E out in clk out in clk out pp. 5

6 FF Based, Edge Trigger Clocking T d = delay of combinational logic T cycle = cycle time of clock Duty cycle does not matter Timing requirements for T d T dmax < T cycle T setup T cq T dmin > T hold T cq no setup time violation no hold time violation clk FF Combinational Logic Td FF T cycle T cq T d T setup pp. 6

7 Latch Based, Single Phase Clocking Aka. Pulse Mode clocking T cycle = cycle time of clock; T w = pulse width of clock Timing requirements for T d T dmax < T cycle T dq T dmin > T w T dq data latched correctly no racing through next stage clk Latch Combinational Logic Td Latch T w T cycle T dq T d pp. 7

8 Flip-Flop Based Larger in area Comparison Larger clocking overhead (T setup, T cq ) + Design more robust Only have to worry about T dmax T dmin usually small, can be easily fixed by buffer + Pulse width does not matter Latch Based Single Phase + Smaller area + Smaller clocking overhead ( only T dq ) Worry about both T dmax and T dmin Pulse width DOES matter (unfortunately, pulse width can vary on chip) pp. 8

9 D Flip-Flop Flop with Positive-Edge Clock module flop (Q, D, C, S, R); output Q; // Flip-Flop Output input D; // Data Input input C; // Positive Edge Clock input E; // Clock Enable D C Q reg Q; // Register Type C) begin if (E) // Check Enable Q <= D; end endmodule D E C Q pp. 9

10 D Flip-Flop Flop with Positive-Edge Clock module flop (Q, D, C, S, R); output Q; // Flip-Flop Output input D; // Data Input input C; // Positive Edge Clock input R; // Asynchronous Reset input S; // synchronous Set reg Q; // Register Type C or negedge R) begin if (!R) Q <= 1 b0; else if (S) Q <= 1 b1; else Q <= D; end endmodule S D C R Q pp. 10

11 D-Latch Active High with Clear/Preset module flop (Q, D, G, C, P); output Q; // Flip-Flop Output input D; // Data Input input G; // Positive Gate input C; // synchronous Clear input P; // synchronous Preset reg Q; // Register Type or G or C or P) begin if (!C) Q <= 1 b0; else if (P) Q <= 1 b1; else if (G) Q <= D; end endmodule P D G C Q pp. 11

12 Finite State Machine ACCESS IC LAB

13 Finite State Machine Used control the circuit core Partition FSM and non-fsm part Controller Non-FSM Circuit core FSM pp. 13

14 Finite State Machines Synchronous (i.e. clocked) finite state machines (FSMs) have widespread application in digital systems, e.g. as datapath controllers in computational units and processors. Synchronous FSMs are characterized by a finite number of states and by clock-driven state transitions. Mealy Machine: The next state and the outputs depend on the present state and the inputs. Moore Machine: The next state depends on the present state and the inputs, but the output depends on only the present state. Mealy machine Moore machine Inputs Next State and Output Combinational Logic State Register Outputs Inputs Next State Combinational Logic clock State Register Output Combinational Logic Outputs clock pp. 14

15 What is FSM A model of computation consisting of a set of states, (limited number) a start state, input symbols, a transition function that maps input symbols and current states to a next state. pp. 15

16 Memory Elements (ME) Elements of FSM Memorize Current States (CS) Usually consist of FF or latch N-bit FF have 2 n possible states Next-state Logic (NL) Combinational Logic Produce next state Based on current state (CS) and input (X) Output Logic (OL) Combinational Logic Produce outputs (Z) Based on current state, or Based on current state and input pp. 16

17 Output is function of both Input and current state Mealy Machine pp. 17

18 Output is function of CS only Not function of inputs Moore Machine pp. 18

19 Mealy Finite State Machine A serially-transmitted BCD (8421 code) word is to be converted into an Excess-3 code. An Excess-3 code word is obtained by adding 3 to the decimal value and taking the binary equivalent. Excess-3 code is self-complementing [Wakerly, p. 80], i.e. the 9's complement of a code word is obtained by complementing the bits of the word. Decimal Excess-3 Digit Code Code (BCD) B in = 8 bcd LSB MSB B out = 8 Excess-3 MSB MSB B in t clk LSB Excess-3 Code Converter B out t pp. 19

20 Mealy Finite State Machine The serial code converter is described by the state transition graph of a Mealy FSM. State Transition Graph 0/1 S_0 1/0 S_1 1/0 S_2 0/1 S_3 S_4 0/0, 1/1 0/1 0/0, 1/1 1/0 S_5 S_6 input / output Next State/OutputTable next state/output state input 0 1 S_0 S_1 / 1 S_2 / 0 S_1 S_3 / 1 S_4 / 0 S_2 S_4 / 0 S_4 / 1 S_3 S_5 / 0 S_5 / 1 S_4 S_5 / 1 S_6 / 0 S_5 S_0 / 0 S_0 / 1 S_6 S_0 / 1 - / - 0/0, 1/1 The vertices of the state transition graph of a Mealy machine are labeled with the states. The branches are labeled with (1) the input that causes a transition to the indicated next state, and (2) with the output that is asserted in the present state for that input. The state transition is synchronized to a clock. 0/1 The state table summarizes the machine's behavior in tabular format. pp. 20

21 Design of a Mealy Finite State Machine To design a D-type flip-flop realization of a FSM having the behavior described by a state transition graph, (1) select a state code, (2) encode the state table, (3) develop Boolean equations describing the input of a D-type flip-flop, and (4) using K-maps, optimize the Boolean equations. Encoded Next state/ Output Table state next state output Next State/Output Table next state/output state input 0 1 S_0 S_1 / 1 S_2 / 0 S_1 S_3 / 1 S_4 / 0 S_2 S_4 / 0 S_4 / 1 S_3 S_5 / 0 S_5 / 1 S_4 S_5 / 1 S_6 / 0 S_5 S_0 / 0 S_0 / 1 S_6 S_0 / 1 - / - State Assigment q S_0 S_1 0 1 S_6 S_4 1 0 S_2 1 1 S_5 S_3 q 2 q + 2 q + 1 q + 0 input input S_ S_ S_ S_ S_ S_ S_ pp. 21

22 Design of a Mealy Finite State Machine B in S_0 S_0 S_1 S_ S_6 S_6 S_4 S_ S_5 S_5 S_3 S_3 x x 1 1 S_2 + = ' S_2 B in S_0 S_0 S_ x x 0 0 S_1 S_6 S_6 S_4 S_4 S_5 S_5 S_3 S_3 S_2 S_2 B in S_0 S_0 S_1 S_ S_6 S_6 S_4 S_ S_5 S_5 S_3 S_3 x x 1 1 S_2 + = S_2 B in q x x 1 0 S_0 S_0 S_1 S_1 S_6 S_6 S_4 S_4 S_5 S_5 S_3 S_3 S_2 S_2 Note: We will optimize the equations individually. In general -this does not necessarily produce the optimal (area, speed) realization of the logic. We'll address this when we consider synthesis. q 2 + = ' 'B in + q 2 ' B in ' + q 2 q 2 + = ' 'B in + q 2 ' B in ' + q 2 q 2 + = ' 'B in q 2 ' B in ' q 2 q 2 + = ' 'B in q 2 ' B in ' q 2 q 2 + = ' 'B in + q 2 ' B in ' + q 2 B out = q 2 'B in ' + q 2 B in pp. 22

23 Design of a Mealy Finite State Machine Realization of the sequential BCD-to-Excess-3 code converter (Mealy machine): q 2 + = ' 'B in + q 2 ' B in ' + q 2 q 2 + = ' 'B in + q 2 ' B in ' + q 2 q 2 + = ' 'B in q 2 ' B in ' q 2 ' D Q q 2 + = ' 'B in q 2 ' B in ' q 2 Q ' q 2 D Q Q ' Bin B in q 2 ' B in ' ' ' D Q Q q 2 q 2 ' B in ' B out clk pp. 23

24 Design of a Mealy Finite State Machine Simulation results for Mealy machine: B_in B_out pp. 24

25 Examples Design of A Serial Line Code Converter Serial Line Codes [Wakerly] are used for serial data time transmission or storage. NRZ Code NRZI Code RZ Code Manchester Code Serial Bit Value B_in NRZ Mealy NRZ Moore NRZI Mealy NRZI Moore RZ Manchester clock_1 clock_2 pp. 25

26 Serial Line Code Converter Mealy FSM Objective: Design a Mealy-type FSM that converts a data stream in NRZ format to a data stream in Manchester code format. Data NRZ NRZ-to- Manchester Code Converter Data Manchester time Serial Bit Value S_2 1 / 0 S_0 0 / 1 S_1 B_in 1 / 1 0 / 0 NRZ Mealy Manchester clock_1 clock_2 pp. 26

27 Serial Line Code Converter Mealy FSM State Transition Graph State Code: 1 / 0 0 / S_2 S_0 S_1 0 S_0 S_1 1 / 1 0 / 0 1 S_2 State Table: next state/output state input 0 1 S_0 S_1 / 0 S_2 / 1 S_1 S_0 / 1 - S_2 - S_0 / 0 Encoded State Table: state next state output q + 1 q + 0 input input S_ S_ S_ pp. 27

28 Encoded State Table: Graduate Institute of Electronics Engineering, NTU Serial Line Code Converter Mealy FSM state next state output + + input input S_ S_ S_ ' ' D Q B_in' q Q 0 ' ' B in ' D Q B q Q 1 ' in clk B out Karnaugh Maps: B in S_0 0 0 S_1 - - S_0 S_1 0 S_2 0 S_2 + = ' 'B in B in S_0 0 0 S_ S_2 S_0 S_1 S_2 + = ' 'B in ' B in S_0 1 1 S_ S_2 S_0 S_1 S_2 B out = ' ( + B in ) pp. 28

29 Serial Line Code Converter Mealy FSM Input and output bit times coincide Note: The Mealy machine's output is subject to glitches in the input bit stream. pp. 29

30 Serial Line Code Converter Moore FSM Objective: Design a Moore-type FSM that converts a data stream in NRZ format to a data stream in Manchester code format. Data NRZ NRZ-to- Manchester Code Converter Data Manchester time Serial Bit Value S_0 0 0 S_1 0 B_in NRZ Mealy Manchester clock_1 1 S_ S_2 1 0 clock_2 pp. 30

31 Serial Line Code Converter Moore FSM State Transition Graph S_0 0 0 S_1 0 State Code: S_0 S_1 0 1 S_2 S_3 S_3 1 1 S_2 1 State Table: Encoded State Table: state next state/output input 0 1 S_0 S_1 / 0 S_3 / 1 S_1 S_2 / 1 - S_3 - S_0 / 1 S_2 S_1 / 0 S_3 / 0 state next state output q + 1 q + 0 input 0 1 S_ S_ S_ S_ pp. 31

32 Encoded State Table: Karnaugh Maps: Graduate Institute of Electronics Engineering, NTU Serial Line Code Converter Moore FSM state next state output + + input 0 1 S_ S_ S_ S_ ' ' B in B out D Q Q ' clk D Q q Q 0 ' B in S_0 1 - S_1-0 S_3 S_0 S_1 S_3 0 S_2 1 S_2 + = ' + 'B in B in S_0 0 - S_1 - S_3 S_ S_2 S_1 S_3 S_2 + = ' S_0 1 1 S_1 S_0 S_1 B_out = pp. 32

33 Serial Line Code Converter Moore FSM NRZ bit time Manchester bit time Note: The Manchester encoder must run at twice the frequency of the incoming data. The output bit stream lags the input bit stream by one-half the input cycle time. pp. 33

34 Building Behavioral Models ACCESS IC LAB

35 Modeling FSM in Verilog Sequential Circuits Memory elements of States (CS) Combinational Circuits Next-state Logic (NL) Output Logic (OL) Three coding styles (1) Separate CS, OL and NL (2) Combines NL+ OL, separate CS (3) Combine CS + NL, separate OL pp. 35

36 CS Graduate Institute of Electronics Engineering, NTU Coding Style 1 Separate CS, NL, OL NL OL pp. 36

37 CS Graduate Institute of Electronics Engineering, NTU Coding Style 2 Combine NL+OL; Separate CS NL+OL pp. 37

38 CS+NL Graduate Institute of Electronics Engineering, NTU Coding Style 3 Combine CS+NL; Separate OL OL pp. 38

39 Behavioral Models of FSM Example1 brake=0 accelerator=1 brake=0 accelerator=1 low speed medium speed brake=1 brake=1 brake=1 stopped high speed brake=1 brake=0 accelerator=1 brake accelerator clock speed brake=0 accelerator=1 pp. 39

40 Verilog Coding 1 (CS, NL, OL) module speed_machine ( clock, accelerator, brake, speed ); input clock, accelerator, brake; output [1:0] speed; reg [1:0] current_state, next_state; // state encoding parameter stopped = 2`b00; parameter s_slow = 2`b01; parameter s_medium = 2`b10; parameter s_high = 2`b11; // CS ( posedge clock ) current_state <= next_state; // OL, Output Logic assign speed = current_state; // NL, Next-state Logic always@( state or accelerator or brake ) if ( brake == 1`b1 ) case ( current_state ) stopped: next_state <= stopped; s_low: next_state <= stopped; s_medium:next_state <= s_low; s_high: next_state <= s_medium; default: next_state <= stopped; endcase else if ( accelerator == 1`b1 ) case ( current_state ) stopped: next_state <= s_low; s_low: next_state <= s_medium; s_medium:next_state <= s_high; s_high: next_state <= s_high; default: next_state <= stopped; endcase else next_state <= current_state; endmodule pp. 40

41 Verilog Coding 3 (CS+NL, OL) module speed_machine2 ( clock, accelerator, brake, speed ); input clock, accelerator, brake; output [1:0] speed; reg [1:0] speed; `define stopped 2`b00 `define s_low 2`b01 `define s_medium 2`b10 `define s_high 2`b11 // OL is empty // because speed itself is state // NL + CS ( posedge clock ) if ( brake == 1`b1 ) case ( speed ) `stopped: speed <= `stopped; `s_low: speed <= `stopped; `s_medium:speed <= `s_low; `s_high: speed <= `s_medium; default: speed <= `stopped; endcase else if ( accelerator == 1`b1 ) case ( speed ) `stopped: speed <= `s_low; `s_low: speed <= `s_medium; `s_medium:speed <= `s_high; `s_high: speed <= `s_high; default: speed <= `stopped; endcase endmodule pp. 41

42 State encoding pp. 42

43 FSM Design Conclusion Partition FSM and non-fsm logic Partition combinational part and sequential part Use parameter to define names of the state vector Assign a default (reset) state pp. 43

44 Homework #4 Design a traffic signal controller at crossroads One pair traffic signal controller State Diagram State Coding Performance [Optional] With interrupt/extra setting 1 2 Other example: Automatic Vending Machine Automatic Teller Machine 2 1 pp. 44

45 Useful Modeling Techniques ACCESS IC LAB

46 Learning Objectives Describe procedural continuous assignment statements assign, deassign, force, and release. Understand how to override parameters by using the defparam statement at the time of module instantiation. Explain conditional compilation and execution of parts of the Verilog. Identify system tasks for file output, displaying hierarchy, strobing, random number generation, memory initialization, and value change dump. pp. 46

47 Procedural Continuous Assignments Procedural Assignments assign a value to a register. The value stays in the register until another procedural assignment puts another value in that register. Procedural Continuous Assignments behave differently. They are procedural statements which allow value of expressions to be driven continuously onto register or net for limited periods of time. They override existing assignments to a register or net, They provide an useful extension to regular procedural assignment statement. pp. 47

48 assign & deassign First type of procedural continuous assignment. The LHS of procedural continuous assignments can only be a register or a concatenation of registers. It cannot be a part or bit select of a net or an array of registers. Procedural continuous assignments override the effect of regular procedural assignments. Procedural continuous assignments are normally used for controlled periods of time. pp. 48

49 Example module edge_dff(q, qbar, d, clk, reset); output q, qbar; input d, clk, reset; reg q, qbar; clk) begin q = d; qbar = ~d; end if (reset) begin assign q = 1 b0; assign qbar = 1 b1; end else begin deassign q; deassign qbar; end endmodule pp. 49

50 force & release Second form of the procedural continuous assignments. They can be used to override assignments on both register and nets. Typically, used in the interactive debugging process, where certain registers or nets are forced to a value and the effect on other registers and nets is noted. They not be used inside design blocks. They should appear only in stimulus or as debug statements. pp. 50

51 Example module stimulus; // instantiate the d-flip-flop edge_dff dff(q, Qbar, D, CLK, RESET); initial begin // these statements force value of 1 // on dff.q between time 50 and 100, // regardless of the actual output of // the edge_dff #50 force dff.q = 1 b1; #50 release dff.q; end endmodule module top; assign out = a & b & c; initial begin #50 force out = a b & c; #50 release; end endmodule pp. 51

52 Overriding Parameters Parameters can be defined in a module definition. However, during compilation of Verilog modules, parameter values can be altered separately for each module instance. this allows us to pass a distinct set of parameter values to each module during compilation regardless of predefined parameter values. Two ways to override parameter values: defparam statement module instance parameter value assignment. pp. 52

53 Example // Define a module hello_world module hello_world; parameter id_num = 0; // define a module identification number = 0 initial $display( Displaying hello_world id number = %d, id_num); endmodule // Define top-level module module top; // Change parameter values in the instantiated modules // Use defparam statement defparam w1.id_num = 1, w2.id_num = 2; // Instantiate two hello_world modules hello_world w1( ); hello_world w2( ); Displaying hello_world id number = 1 Displaying hello_world id number = 2 endmodule pp. 53

54 Condition Compilation and Execution A portion of Verilog might be suitable for one environment and not for the other. The designer does not wish to create two versions of Verlog design for the two environments. Instead, the designer can specify that the particular portion of the code be compiled only if certain flag is set. This is called conditional compilation. A designer might also want to execute certain parts of the Verilog design only when a flag is set at run time. This is called conditional execution. pp. 54

55 Conditional Compilation Conditional compilation can be accomplished by using compiler directives `ifdef, `else, and `endif. // Conditional Compilation // Example 1 `ifdef TEST // compile module test only if module test; // text marco TEXT is defined endmodule `else // compile the stimulus as default module stimulus; endmodule `endif // completion // Conditional Compilation // Example 2 module top; bus_master b1 ( ); `ifdef ADD_B2 bus_master b2 ( ); `endif endmodule pp. 55

56 Conditional Execution Conditional execution flags allow the designer to control statement execution flow at run time. All statements are compiled but executed conditionally. Conditional execution flags can be used only for behavioral statements. The system task keywork $test$plusargs is used for conditional execution. // Conditional Execution module test; initial begin end if ($test$plusargs( DISPLAY_VAR )) $display( Display = %b, {a, b, c} ); // display only if flag is set else endmoduel $display( No Display ); // otherwise no display pp. 56

57 File Output Files Open/Write/Close Opening a file integer filepointer; initial filepointer = $fopen( file.out ); Writing to file fdisplay(filepointer, Display ); fmonitior(filepointer, P1=%b, P1); Closing files $fclose(filepointer); pp. 57

58 Strobing Useful System Tasks The $strobe task is very similar to the $display task except for a slight difference The $strobe task provides a synchronization mechanism to ensure that data is displayed only after all other assignment statements. Random Number Generation $random; or $random(seed); returns a 32-bit random number. pp. 58

59 Useful System Tasks Initializing memory form file reg[7:0] memory[0:7]; initial begin $readmemb( init.dat, memory); // display contents of initialized memory for (i=0; i<8; i=i+1) $display( Memory[%0d] = %b, i, memory[i]); end Memory[0] = xxxxxxxx Memory[1] = xxxxxxxx Memory[2] = Memory[3] = Memory[4] = Memory[5] = Memory[6] = 1111zzzz Memory[7] = zzzz uninitialized locations default to x pp. 59