Module Instantiation. Finite State Machines. Two Types of FSMs. Finite State Machines. Given submodule mux32two: Instantiation of mux32two

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1 Give submodule mux32two: 2-to- MUX module mux32two (iput [3:] i,i, iput sel, output [3:] out); Module Istatiatio Fiite Machies esig methodology for sequetial logic -- idetify distict s -- create trasitio diagram -- choose ecodig -- write combiatioal Verilog for ext- logic -- write combiatioal Verilog for output sigals ots of examples assig out = sel? i : i; edmodule Istatiatio of mux32two module zyz (iput xi,... output yout,...) mux32two adder_mux(.i(b),.i(32'd),.sel(f[]),.out(addmux_out)); mux32two sub_mux(.i(b),.i(32'd),.sel(f[]),.out(submux_out)); module ames (uique) istace ames correspodig iputs/ for mux32two explicitly declared for each istace 6. Fall 26 ecture 3 2 Fiite Machies Fiite Machies (FSMs) are a useful abstractio for sequetial circuits with cetralized s of operatio At each clock edge, combiatioal logic computes ad ext as a fuctio of iputs ad preset iputs preset Combiatioal ext Moore FSM: iputs x...x Mealy FSM: iputs x...x Two Types of FSMs Moore ad Mealy FSMs : differet output geeratio ext preset S direct combiatioal path! S y k = f k (S) y k = f k (S, x...x ) 3 4

2 esig Example: evel-to-ulse A level-to-pulse coverter produces a siglecycle pulse each time its iput goes high. It s a sychroous risig-edge detector. Sample uses: Buttos ad switches pressed by humas for arbitrary periods of time Sigle-cycle eable sigals for couters Step : Trasitio iagram Block diagram of desired system: usychroized user iput Sychroizer trasitio diagram is a useful FSM represetatio ad desig aid: Edge etector evel to ulse FSM if = at the clock edge, the jump to. = = Biary values of s Wheever iput goes from low to high... evel to ulse Coverter...output produces a sigle pulse, oe clock period wide. = if = at the clock edge, the stay i. ow iput, Waitig for rise = = Edge etected! = = High iput, Waitig for fall = = This is the output that results from this. (Moore or Mealy?) 5 6 Valid Trasitio iagrams Choosig Represetatio = ow iput, Waitig for rise = = = Edge etected! = = High iput, Waitig for fall = = Arcs leavig a are mutually exclusive, i.e., for ay combiatio iput values there s at most oe applicable arc Arcs leavig a are collectively exhaustive, i.e., for ay combiatio of iput values there s at least oe applicable arc So for each : for ay combiatio of iput values there s exactly oe applicable arc Ofte a startig is specified Each specifies values for all (Moore) 7 = Choice #: biary ecodig For N s, use ceil(log 2 N) bits to ecode the with each represeted by a uique combiatio of the bits. Tradeoffs: most efficiet use of registers, but requires more complicated combiatioal logic to detect whe i a particular. Choice #2: oe-hot ecodig For N s, use N bits to ecode the where the bit correspodig to the curret is, all the others. Tradeoffs: more registers, but ofte much less combiatioal logic sice decodig is trivial. 8

3 = ow iput, Waitig for rise = Step 2: erivatio Trasitio diagram is readily coverted to a trasitio table (just a truth table) = = = Edge etected! = High iput, Waitig for fall = = = Curret Combiatioal logic may be derived usig Karaugh maps S S for : X X S S for : X X = S = S = S S I Next Out S S S for : S S X iputs x...x Moore evel-to-ulse Coverter = S = ext preset S y k = f k (S) Moore FSM circuit implemetatio of level-to-pulse coverter: S S S S = S S 9. Whe = ad S=, this output is asserted immediately ad util the trasitio occurs (or chages). = = esig of a Mealy evel-to-ulse S Sice are determied by ad iputs, Mealy FSMs may eed fewer s tha Moore FSM implemetatios Iput is low = = = = direct combiatioal path! Iput is high 2. While i S= ad as log as remais at, this output is asserted util ext clock. = = Clock Stat e Output trasitios immediately. trasitios at the clock edge. 2 = = Mealy evel-to-ulse Coverter Iput is low res. Mealy FSM circuit implemetatio of level-to-pulse coverter: = = = = Iput is high S = = S I Next Stat e Out S FSM s simply remembers the previous value of Circuit beefits from the Mealy FSM s implicit sigle-cycle assertio of durig trasitios 2

4 Moore/Mealy Trade-Offs How are they differet? Moore: = f( ) oly Mealy = f( ad iput ) Mealy geerally occur oe cycle earlier tha a Moore: Moore: delayed assertio of Clock [ ] Mealy: immediate assertio of Compared to a Moore FSM, a Mealy FSM might... Be more difficult to coceptualize ad desig Have fewer s Clock Example: Itersectio Traffic ights esig a cotroller for the traffic lights at the itersectio of two streets two sets of traffic lights, oe for each of the streets. Step : raw startig trasitio diagram. Just hadle the usual gree-yellow-red cycle for both streets. How may s? Well, how may differet combiatios of the two sets of lights are eeded? Step 2: add support for a walk butto ad walk lights to your trasitio diagram. Step 3: add support for a traffic sesor for each of the streets whe the sesor detects traffic the gree cycle for that street is exteded. Example to be worked collaboratively o the board 3 4 FSM Example Step A: Block iagram GOA: Build a electroic combiatio lock with a reset butto, two umber buttos ( ad ), ad a ulock output. The combiatio should be. UNOCK Clock geerator Butto Eter lock fsm_clock fsm ulock reset butto reset Ulock E STES:. esig lock FSM (block diagram, trasitios) 2. Write Verilog module(s) for FSM Butto Butto b_i b_i butto butto b b E ISAY 5 6

5 Step B: trasitio diagram Step 2: Write Verilog Ulock = Ulock = Ulock = Ulock = Ulock = Ulock = module lock(iput clk,reset_i,b_i,b_i, output out); // sychroize push buttos, covert to pulses // implemet trasitio diagram reg [2:],ext_; begi // combiatioal logic! ext_ =???; ed clk) <= ext_; // geerate output assig out =???; // debuggig? edmodule 6 s 3 bits 7 8 Step 2A: Sychroize buttos // butto // push butto sychroizer ad level-to-pulse coverter // OUT goes high for oe cycle of wheever IN makes a // low-to-high trasitio. out module butto( r r2 r3 iput clk,i, i output out ); clk reg r,r2,r3; clk) sychroizer begi r <= i; // first reg i sychroizer r2 <= r; // secod reg i sychroizer, output is i syc! r3 <= r2; // remembers previous of butto ed // risig edge = old value is, ew value is assig out = ~r3 & r2; edmodule 9 Step 2B: trasitio diagram parameter S_ = ; // assigmets parameter S_ = ; parameter S_ = 2; parameter S_ = 3; parameter S_ = 4; parameter S_ = 5; reg [2:], ext_; Ulock = Ulock = begi // implemet trasitio diagram if (reset) ext_ = S_; else case () S_: ext_ = b? S_ : b? S_ : ; S_: ext_ = b? S_ : b? S_ : ; S_: ext_ = b? S_ : b? S_ : ; S_: ext_ = b? S_ : b? S_ : ; S_: ext_ = b? S_ : b? S_ : ; S_: ext_ = b? S_ : b? S_ : ; default: ext_ = S_; // hadle uused s edcase ed clk) <= ext_; Ulock = Ulock = Ulock = Ulock = 2

6 Step 2C: geerate output // it s a Moore machie! Output oly depeds o curret assig out = ( == S_); Step 2: debuggig? // hmmm. What would be useful to kow? Curret? // hex_display o labkit shows 6 four bit values assig hex_display = {6 b, 'b, [2:]}; Step 2: fial Verilog implemetatio module lock(iput clk,reset_i,b_i,b_i, output out, output [3:] hex_display); wire reset, b, b; // sychroize push buttos, covert to pulses butto b_reset(clk,reset_i,reset); butto b_(clk,b_i,b); butto b_(clk,b_i,b); parameter S_ = ; parameter S_ = ; // assigmets parameter S_ = 2; parameter S_ = 3; parameter S_ = 4; parameter S_ = 5; reg [2:],ext_; begi // implemet trasitio diagram if (reset) ext_ = S_; else case () S_: ext_ = b? S_ : b? S_ : ; S_: ext_ = b? S_ : b? S_ : ; S_: ext_ = b? S_ : b? S_ : ; S_: ext_ = b? S_ : b? S_ : ; S_: ext_ = b? S_ : b? S_ : ; S_: ext_ = b? S_ : b? S_ : ; default: ext_ = S_; // hadle uused s edcase ed (posedge clk) <= ext_; assig out = ( == S_); // assig output: Moore machie assig hex_display = {'b,}; // debuggig edmodule 2 22 Real FSM Security System The 6. Vedig Machie ab assistats demad a ew soda machie for the 6. lab. You desig the FSM cotroller. All selectios are $.3. The machie makes chage. (imes ad ickels oly.) Iputs: limit per clock - quarter iserted - dime iserted N - ickel iserted Outputs: limit per clock C - dispese ca - dispese dime N - dispese ickel 3 3 COINS ONY 25 Co 5 Sprite Jolt Water S

7 What s are i the System? A Moore Veder A startig () : A for each possible amout of moey captured: got5c gotc got5c... What s the maximum amout of moey captured before purchase? 25 cets (just shy of a purchase) oe quarter (largest coi)... got35c got4c got45c got5c s to dispese chage (oe per coi dispesed): got45c ispese ime ispese Nickel Here s a first cut at the trasitio diagram. See a better way? So do we. o t go away... got5c gotc got5c got2c got25c got3c got35c chg35 got4c got45c chg4 chg45 chg45b got5c chg5 chg5b Reductio Verilog for the Moore Veder got5c gotc got5c got2c got25c got3c got35c got4c got45c got5c chg35 chg4 chg45 chg5 uplicate s have: The same, ad The same trasitios There are two duplicates i our origial diagram. chg45b chg5b 7 s 5 bits 5 s 4 bits got5c gotc got5c got2c got25c got3c got35c got4c got45c got5c rt5 rt rt5 rt2 Register FSMs are easy i Verilog. Simply write oe of each: register (sequetial always block) Next- combiatioal logic (comb. always block with case) Output combiatioal logic block (comb. always block or assig mets) module mooreveder ( iput N,,, clk, reset, output C, N,, output reg [3:] ); reg ext; s defied with parameter keyword parameter IE = ; parameter GOT_5c = ; parameter GOT_c = 2; parameter GOT_5c = 3; parameter GOT_2c = 4; parameter GOT_25c = 5; parameter GOT_3c = 6; parameter GOT_35c = 7; parameter GOT_4c = 8; parameter GOT_45c = 9; parameter GOT_5c = ; parameter RETURN_2c = ; parameter RETURN_5c = 2; parameter RETURN_c = 3; parameter RETURN_5c = 4; register defied with sequetial always block (posedge clk or egedge reset) if (!reset) <= IE; else <= ext; 27 28

8 Verilog for the Moore Veder Simulatio of Moore Veder Next- logic withi a combiatioal always block GOT_25c: if () ext = GOT_5c; else if () ext = GOT_35c; else if (N) ext = GOT_3c; else ext = GOT_25c; ( or N or or ) begi case () IE: if () ext = GOT_25c; else if () ext = GOT_c; else if (N) ext = GOT_5c; else ext = IE; GOT_5c: if () ext = GOT_3c; else if () ext = GOT_5c; else if (N) ext = GOT_c; else ext = GOT_5c; GOT_c: if () ext = GOT_35c; else if () ext = GOT_2c; else if (N) ext = GOT_5c; else ext = GOT_c; GOT_3c: ext = IE; GOT_35c: ext = RETURN_5c; GOT_4c: ext = RETURN_c; GOT_45c: ext = RETURN_5c; GOT_5c: ext = RETURN_2c; RETURN_2c: ext = RETURN_c; RETURN_5c: ext = RETURN_5c; RETURN_c: ext = IE; RETURN_5c: ext = IE; default: ext = IE; edcase ed Combiatioal output assigmet GOT_5c: if () ext = GOT_4c; else if () ext = GOT_25c; else if (N) ext = GOT_2c; else ext = GOT_5c; GOT_2c: if () ext = GOT_45c; else if () ext = GOT_3c; else if (N) ext = GOT_25c; else ext = GOT_2c; assig C = ( == GOT_3c == GOT_35c == GOT_4c == GOT_45c == GOT_5c); assig N = ( == RETURN_5c); assig = ( == RETURN_2c == RETURN_5c == RETURN_c); edmodule Output got5c got2c got5c got45c rt5 rt gotc got2c FSM Output Glitchig FSM bits may ot trasitio at precisely the same time Combiatioal logic for may cotai hazards Result: your FSM may glitch! durig this trasitio......the registers may trastio like this... gotc got3c got2c...causig the C output to glitch like this! assig C = ( == GOT_3c == GOT_35c == GOT_4c == GOT_45c == GOT_5c); If the soda dispeser is glitch-sesitive, your customers ca get a 2-cet soda! glitch iputs Registered FSM Outputs are Glitch-Free Next- ext Move output geeratio ito the sequetial always block Calculate based o ext Output preset S elays by oe clock cycle. roblematic i some applicatio. reg C,N,; Output // Sequetial always block for assigmet (posedge clk or egedge reset) begi if (!reset) <= IE; else if (clk) <= ext; C <= (ext == GOT_3c ext == GOT_35c ext == GOT_4c ext == GOT_45c ext == GOT_5c); N <= (ext == RETURN_5c); <= (ext == RETURN_2c ext == RETURN_5c ext == RETURN_c); ed registered 3 32

9 Where should come from? Optio : exteral crystal Stable, kow frequecy, typically 5% duty cycle Optio 2: iteral sigals Optio 2A: output of combiatioal logic No! If iputs to logic chage, output may make several trasitios before settlig to fial value several risig edges, ot just oe! Hard to desig away output glitches Optio 2B: output of a register Okay, but timig of 2 wo t lie up with 2 33