AN INTRODUCTION TO VERILOG HDL

Transcription

1 AN INTRODUCTION TO VERILOG HDL Departamento de Tecnología Electrónica Universidad de Sevilla Rev.7 (feb 2013)

2 Index Introducction Part I: combinational circuits Part II: sequential circuits 2

3 Introducción Verilog is a formal language for describing and implementing electronic circuits. It can be similar to an imperative programming language Differences: Often, sentences are executed concurrently It is used for describing hardware 3

4 Bibliography & references Online: Verilog-1995 Quick Reference Guide by Stuart Sutherland of Sutherland HDL, Inc., Portland, Oregon, USA at Verilog Tutorial: Verilog HDL Quick Reference Guide (Verilog-2001 standard) 4

5 Part I Combinational circuits 5

6 Part I: Index Sections of a Verilog description Description styles Signals, I/O ports and arrays Sintax 6

7 Sections of a Verilog description module mi_circuito ( input x, y, input z, output f1, f2 ); wire cable_interno; reg variable_a; endmodule This is the header. It is used to name the module and to to declare its inputs and outputs. Here we declare the signals and variables to be used internally within the module. Here we declare the module. We have several description styles to choose from. 7

8 Example: a voting circuit a b votador z Logic expression: z=ab+ac+bc c module votador (input a,b,c,output z); assign z= (a & b) (a & c) (b & c); endmodule 8

9 Description styles Functional description It is used to model combinational circuits. By using the assign keyword it is stated that the value of a digital signal is a logic function of other signals. Assign sentences are executed concurrently. module votador(input a,b,c, output z); assign z = a&b a&c b&c; endmodule 9

10 Description styles Procedural description We can use control statements here to describe an algorithm. It is usefull for describing complex functions. It is just an always sentence followed by an imperative sentence. module votador( input a,b,c, output reg z) if(a==1) if(b==1 c==1) z=1; else z=0; else if(b==1 && c==1) z=1; else z=0; endmodule 10

11 Description styles Structural description Here we list the internal components of the module and their interconnections. These components must be previously described, but basic logic gates are predefined in Verilog. It is usefull for describing component interconnections. a b c and1 and3 and2 module votador( input a,b,c, output z) out3 out1 or1 out2 wire out1,out2,out3; and and1(out1,a,b); and and2(out2,b,c); and and3(out3,a,c); or or1(z,out1,out2,out3); z endmodule 11

12 Description styles assign and always sentences are executed concurrently. Structural description is used to describe the interconnection of the declared components. Descriptions using structural style can form a hierachy. 12

13 Description styles Example: describing a 4-bit full-adder made of several 1-bit full-adders b3 b2 b1 b0 a3 a2 a1 a0 cout4 FA 4bits cin s3 s2 s1 s0 a3 b3 a2 b2 a1 b1 a0 b0 cout4 FA3 cout3 FA2 cout2 FA1 cout1 FA0 cin s3 s2 s1 s0 13

14 Description styles Steps: 1. Describe the module for the 1-bit full-adders. 2. Describe the module for the 4-bit full-adder by instantiating four 1-bit full-adders and describing their interconnections. 14

15 Description styles a b Description of the 1-bit full-adder cout FA cin module fulladder( input a, input b, input cin, output s, output cout); assign s = a ^ b ^ cin; assign cout = a & b a & cin b & cin; endmodule cin a b cout s s s=a b c cout=a b + a cin + b cin 15

16 Description styles Connecting the full-adders: positional connection. a3 b3 a2 b2 a1 b1 a0 b0 module fulladder4( input [3:0] a, input [3:0] b, input cin, output [3:0] s, output cout4); cout4 FA3 s3 cout3 FA2 s2 cout2 FA1 s1 cout1 FA0 s0 cin wire cout1,cout2,cout3; fulladder fa0 (a[0], b[0], cin, s[0], cout1); fulladder fa1 (a[1], b[1], cout1, s[1], cout2); fulladder fa2 (a[2], b[2], cout2, s[2], cout3); fulladder fa3 (a[3], b[3], cout3, s[3], cout4); endmodule 16

17 Description styles Connecting the full-adders: named connection. a3 b3 a2 b2 a1 b1 a0 b0 module fulladder4( input [3:0] a, input [3:0] b, input cin, output [3:0] s, output cout4); cout4 FA3 s3 cout3 FA2 s2 cout2 FA1 s1 cout1 FA0 s0 cin wire cout1,cout2,cout3; fulladder fa0 (.a(a[0]),.b(b[0]),.cin(cin),.s(s[0]),.cout(cout1)); fulladder fa1 (.a(a[1]),.b(b[1]),.cin(cout1),.s(s[1]),.cout(cout2)); fulladder fa2 (.a(a[2]),.b(b[2]),.cin(cout2),.s(s[2]),.cout(cout3)); fulladder fa3 (.a(a[3]),.b(b[3]),.cin(cout3),.s(s[3]),.cout(cout4)); endmodule 17

18 Signal types You can declare signals of two types wire: physical nets interconnecting componentes. They have no memory. reg: (variable). Mainly used to store values within procedural descriptions. They do have memory. reg signals are usually used to model data storing (memories) but any signal assigned within an always statement must be declared as reg even if it just a wire. 18

19 Input/Output ports When declaring a module you can specify if its ports are wire or reg wire is assumed by default if not specified otherwise The left part of an assign sentence can only be a wire signal. Only reg signals can be assigned within procedures. module mi_circuito ( input wire x, input z, output reg mem );... endmodule 19

20 Arrays signal arrays can be very usefull: It is easier to handle I/O ports if you group them into buses. You can handle registers of multiple bits. Sintax: [M:N] A3 A2 A1 A0 B3 B2 B1 B0 COMPARADOR GEL G E L module comparador_gel ( input wire [3:0] a, input [3:0] b, output g,e,l );... endmodule 20

21 Sintax Literals Assign sentences Always sentences Operators and expressions Conditional sentences 21

22 Sintax Verilog is case sensitive You can write comments: One line comments: preceded by double slash // wire a; // Este cable se conecta con f2 Multi line comments: between /* and */ /* Este cable conecta muchos componentes y necesito varias lineas para explicarlo correctamente */ wire a; 22

23 Sintax Literals: You can use several formats Example: The 8-bit word BINARY OCTAL HEXADECIMAL DECIMAL 8'b 'o052 8'h2A 8'd42 ó 42 Number of bits base (b,o,h,d) 23

24 Sintax Example: a circuit whose outputs are always set to 1 module siempre_uno ( input x, output [7:0] salida1, output [3:0] salida2 ); assign salida2 = 4'b1111; assign salida1 = 8'hFF; endmodule 24

25 Assign sentences assign sentences are executed concurrently You can change the second assign sentence on the right by the following: assign f2 = x & y & z; module otro_ejemplo ( input x, y, z, output f1, f2 ); assign f1 = x & y; assign f2 = f1 & z; endmodule 25

26 Always sentences Any always sentence is executed concurrently with other always and assign sentences. An always sentence includes a sensitivity list : La lista de sensibilidad consiste en una lista de señales. El código del bloque always se ejecuta sólo si cambia alguna de las señales de la lista de sensibilidad. La sintaxis es: c = a b; 26

27 Always sentences If you want a set of sentences to be executed sequentially you can write them within a beginend statement. module (input a, b, c, d output reg f1, output reg f2); begin f1 = a b; f2 = c & d; end endmodule 27

28 WARNING: Always sentences When describing combinational components every input must be included in the sensitivity list. You can write for short. module (input a, b, c, d, input e, f, g, h, output f1, f2); begin... end endmodule = module (input a, b, c, d, input e, f, g, h, output f1, f2); begin... end endmodule 28

29 Operators Bitwise operators: Operator Example & c = a&b; // AND operation c = a b; // OR operation ^ c = a^b; // XOR operation ~ b = ~a; // NOT operation You can use them with individual bits and arrays. 29

30 Operators More bitwise operators: Operator ~& Example d = a ~& b; // NAND operation ~ d = a ~ b; // NOR operation ~^ d = a ~^ b; // NEXOR operation 30

31 Operators Example: A module for calculating the ones' complement of a 16-bit word module complemento_a1( input [15:0] palabra, output [15:0] complemento_1); assign complemento_1 = ~palabra; endmodule 31

32 Operators relational operators: Operator Example < a < b; // Is a lower than b? > a > b; // Is a greater than b? >= a >= b; // Is a greater than or equal to b? <= a <= b; // Is a lower than or equal to b? == a == b; // Is a equal to b?!= a!= b; // Is a different from b? 32

33 Operators Logical operators: they are not the same as the bitwise operators. Operator && Example a && b; // logic and operator a b; // logic or operator!!a; // logic not operator 33

34 Operators Arithmetic operators Operator Example * c = a * b; // multiplication / c = a / b; // division + sum = a + b; // addition - resta = a - b; // subtraction 34

35 Other operators Operators operator Example << b = a << 1; // 1-bit left shift >> b = a >> 1; // 1-bit right shift?: c = sel? a : b; // if c is true then c=a // otherwise c =b {} {a, b, c} = 3'b101; // concatenanion: // a=1, b=0 y c=1 There are more operators (see the bibliography) 35

36 Conditional sentences if else sentence if ( a > 0 ) Sentencia else Sentencia if ( a == 0 ) Sentencia else if( b!= 1 ) Sentencia You can only use it within always statements You can write the condition using logical and relational operators 36

37 Conditional sentences If you want more than one sentence to be executed when the condition is true you must group them within a begin end sentence. begin if ( a > 0 ) f1 = 1; f2 = 1; else f1 = 0; end WRONG begin if ( a > 0 ) begin f1 = 1; f2 = 1; end else f1 = 0; end OK 37

38 Conditional sentences Example: a GEL comparator module comparador_gel( input [3:0] a, input [3:0] b, output g, // si a < b => (g,e,l) = (0,0,1) output e, // si a = b => (g,e,l) = (0,1,0) output l); A3 A2 A1 A0 B3 B2 B1 B0 COMPARADOR GEL G E L reg g, e, l; b) begin g = 0; e = 0; l = 0; if (a > b) g =1; else if (a < b) l = 1; else e = 1; end endmodule 38

39 Conditional sentences Case sentence You can only use it within always statements. If you want more than one sentence to be executed for one case you must group them within a begin end sentence. You can use the default keyword to take into account the values not explicitly mentioned. reg [1:0] x; begin case(x) 0: salida_1 = 1; 1: begin salida_1 = 1; salida_2 = 0; end 2: salida_2 = 1; 3: salida_1 = 0; endcase end 39

40 Conditional sentences Example: a multiplexer module mux8_1( input [2:0] s, input [7:0] in, output out); in0 in1 in2 in3 in4 in5 in6 in7 s2 s1 s0 out reg out; in) case (s) 3'h0: out = in[0]; 3'h1: out = in[1]; 3'h2: out = in[2]; 3'h3: out = in[3]; 3'h4: out = in[4]; 3'h5: out = in[5]; 3'h6: out = in[6]; default: out = in[7]; endcase endmodule 40

41 Part II Sequential Circuits 41

42 Part II: Index Sintax II Bistables Finite State Machines Registers Counters 42

43 Sintax II Constant definitions Concatenation operator Edge detection blocking/non blocking assignments 43

44 Sintax II You can define constants within a module by using the parameter keyword. It is useful for describing state machines. Example: parameter uno_con_tres_bits = 3'b001, ultimo = 3'b111; reg [2:0] a; a = ultimo; 44

45 Sintax II You can group signals to form an array by using the concatenation operator Sintax: {signal, signal,...} Example: Circuit to detect number 3 module concatena( input a,b,c, output reg igual_a_3 ); case({a,b,c}) 3'b011: igual_a_3 = 1; default: igual_a_3 = 0; endcase endmodule 45

46 Sintax II Edge detection You can use edge detection if you want a process to be executed only if some of the signals in the sensitive list rise (or fall). To do so you must use the following prefixes in the sensitive list: - posedge for detecting rising edges - negedge for detecting falling edges 46

47 Sintax II Example: module detector_flanco( input clk, output reg z); clk)... endmodule 47

48 Sintax II Blocking assignment: = When executed the new value is assumed immediately. It is useful for modeling combinational outputs. Multiple blocking assignments within the same always statement can only execute sequentially so their order is relevant. 48

49 Sintax II Non blocking assignment: <= It is useful for modeling register writing. When multiple blocking assignments within an always statement are executed, every right part is evaluated first. Afterwards the assignments are executed simultaneously. So, their order is not relevant. 49

50 Sintax II module no_bloqueante(input a,clk, output reg z1); reg q; clk) begin q <= a; z1 <= q; end endmodule module bloqueante(input a,clk, output reg z2); reg q; clk) begin q = a; z2 = q; end endmodule clk a z1 z2 50

51 Bistables Example: D q module biestable_d( input clk,d, output reg q); (posedge clk) q <= d; clk endmodule clk d q 51

52 Bistables Triggered by falling edge: q D ck module biestable_d( input ck,d, output reg q); (negedge ck) q <= d; endmodule ck d q 52

53 Bistables asynchronous reset: module biestable_d( input ck,d,reset, output reg q); D RESET q (posedge ck or posedge reset) if (reset) q <= 1'b0; else q <= d; endmodule ck ck d reset q 53

54 Bistables synchronous reset: clk d reset q module biestable_d( input clk,d,reset, output reg q); (posedge clk) if (reset) q <= 1'b0; else q <= d; endmodule 54

55 Bistables JK bistable: module jk_flip_flop ( J q input ck, input j, input k, output reg q); JK q 0 1 K ck Q ck) case ({j,k}) 2'b11 : q <= ~q; // Cambio 2'b01 : q <= 1'b0; // reset. 2'b10 : q <= 1'b1; // set. 2'b00 : q <= q; // endcase endmodule 55

56 Bistables T bistable: q T ck T=1 T=0 T=0 q=0 q=1 module biestable_t( input ck, input t, output reg q); ck) if (t == 1) q <= ~q; endmodule T=1 56

57 Bistables practice: Describe the following bistables. CL and PR must be asynchronous. CL PR CL PR CL PR CL PR S q J q D q T q R ck K ck ck ck 57

58 State machines 1/0 A 0/0 0/0 1/1 1/0 B 1/0 D 0/0 C 0/0 We will describe them by using two process: One will assign values to the state registers. The other will calculate the outputs and the next state of the machine. 58

59 State machines module mi_diagrama_de_estados( input YOUR_LIST_OF_INPUTS_HERE, output reg YOUR_LIST_OF_OUTPUTS_HERE); // DEFINICION Y ASIGNACIÓN DE ESTADOS parameter YOUR_LIST_OF_STATES_HERE // VARIABLES PARA ALMACENAR EL ESTADO PRESENTE Y SIGUIENTE reg [N:0] current_state, next_state; // PROCESO DE CAMBIO DE ESTADO clk or posedge reset)... // PROCESO SIGUIENTE ESTADO Y SALIDA YOUR_LIST_OF_INPUTS_HERE)... endmodule 59

60 State machines Our description will have four parts: 1. The first one will be used for naming and assigning binary codes to every state of the machine. 2. In the second one the state registers will be declared. There must be one for each bit of the state codes. 3. The third one will be the process assigning values to the state registers. Its code is always the same. 4. The last one will be the process calculating the next state codes and the outputs of the sequential circuit. Its behaviour is described by the state graph. 60

61 State machines module maquina_estados( input x, clk, reset, output reg z); 1/0 B 1/0 0/0 parameter A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11; State codes assignment reg [1:0] current_state,next_state; 0/0 A 1/1 1/0 C clk, posedge reset) begin if(reset) current_state <= A; else current_state <= next_state; end To be continued -> 0/0 D process assigning values to the state registers 0/0 61

62 State machines the process calculating the next state codes and the outputs of the sequential circuit can be describe with a single case statement. Every state must be taken into account. It is recommended to assign a default value to each output before the case statement. 62

63 State machines begin z = 0; case(current_state) A: if(x == 1) next_state = B; else next_state = A; B: if(x == 1) next_state = B; else next_state = C; The output is set to zero by default state A state B 0/0 1/0 A 0/0 1/1 B D 1/0 1/0 0/0 C 0/0 63

64 State machines C: if(x == 1) next_state = B; else next_state = D; D: if(x == 1) begin z = 1; next_state = B; end else next_state = A; endcase end endmodule state C state D 0/0 1/0 A 0/0 1/1 B D 1/0 1/0 0/0 C 0/0 64

65 Registers Register with clear and parallel load operations C L LD C K x 3 x 2 x 1 x 0 REG z 3 z 2 z 1 z 0 CL, LD Operation Type 0x q 0 async. 11 q x sync. 10 q q sync. module registro( input ck, input cl, input ld, input [3:0] x, output [3:0] z ); reg [3:0] q; ck, negedge cl) if (cl == 0) q <= 0; else if (ld == 1) q <= x; assign z = q; endmodule 65

66 Registers Shift register C L E N C K REG x L module reg_shl( input ck, input cl, input en, input xl, output zl ); reg [3:0] q; z L CL, EN Operation Type 0x q 0 async. 11 q SHL(q) sync. 10 q q sync. ck, negedge cl) if (cl == 0) q <= 0; else if (en == 1) q <= {q[2:0], xl}; assign zl = q[3]; endmodule 66

67 Counters counter with clear operation: C L C K COUNT z 3 z 2 z 1 z 0 CL Operation Type 1 q 0 async. 0 q q+1 mod 16 sync. module count_mod16( input ck, input cl, output [3:0] z); reg [3:0] q; ck, posedge cl) if (cl == 1) q <= 0; else q <= q + 1; assign z = q; endmodule 67

68 Counters Up/Down counter with clear operation: C L E N U D C K COUNT z 3 z 2 z 1 z 0 CL, EN, UD Operation Type 1xx q 0 async. 00x q q sync. 010 q q+1 mod 16 sync. 011 q q-1 mod 16 sync. C module rev_counter1( input ck, input cl,en, ud, output [3:0] z, output c); reg [3:0] q; ck, posedge cl) begin if (cl == 1) q <= 0; else if (en == 1) if (ud == 0) q <= q + 1; else q <= q - 1; end assign z = q; assign c = ud? ~( q) : &q; endmodule 68