Reconfigurable Computing Systems ( L) Fall 2012 Tiny Register Machine (TRM)

Transcription

1 Reconfigurable Computing Systems ( L) Fall 2012 Tiny Register Machine (TRM) L. Liu Department of Computer Science, ETH Zürich Fall semester,

2 Introduction Jumping up a few levels of abstraction. Architecture: the programmer s view of the computer Defined by instructions (operations) and operand locations Microarchitecture: how to implement an architecture in hardware Application Software O perating System s Architecture M icroarchitecture Logic D igital Circuits Analog Circuits Devices program s device drivers instructions registers datapaths controllers adders m em ories AND gates N O T gates am plifiers filte rs transistors diodes Physics electrons Adapted from Digital Design and Computer Architecture, David Money Harris & Sarah L. Elsevier 2

3 Assembly Language To command a computer, you must understand its language. Instructions: words in a computer s language Instruction set: the vocabulary of a computer s language Instructions indicate the operation to perform and the operands to use. Assembly language: human-readable format of instructions Machine language: computer-readable format (1 s and 0 s) Assembler: a tool to translate assembly code into machine code TRM (Tiny Register Machine) architecture: Designed by Prof. Niklaus Wirth and implemented on Xilinx Spartan-3, Virtex-5 and Spartan-6 by Ling Liu. A RISC processor that only contains the necessary instructions to run an application written in a high-level language. Once you ve learned one architecture, it s easy to learn others. 3

4 Architecture Design Principles Underlying design principles, as articulated by Hennessy and Patterson: 1.Simplicity favors regularity 2.Make the common case fast 3.Smaller is faster 4.Good design demands good compromises 4

5 Design Principle 1 Simplicity favors regularity - Consistent instruction format - Same number of operands, easier to encode and handle in hardware TRM instruction encoding 5

6 Design Principle 2 Make the common case fast - ALU operations are performed on registers and constants - TRM is a reduced instruction set computer (RISC), with a small number of simple instructions. - The main characteristic of RISC architecture is to allow most instructions to be executed in one clock cycle. 6

7 Design Principle 3 Smaller is Faster - TRM includes only a small number of registers - Just as retrieving data from a few books on your table is faster than sorting through 1000 books, retrieving data from 32 registers is faster than retrieving it from 1000 registers or a large memory. 7

8 Design Principle 4 Good design demands good compromises - Multiple instruction formats allow flexibility - ADD, SUB: use 2 register operands - LD, ST: use 2 register operands and a constant - Number of instruction formats kept small - to adhere to design principles 1 and 3 (simplicity favors regularity and smaller is faster). 8

9 TRM Machine Language Computers only understand 1 s and 0 s Machine language: binary representation of instructions 18-bit instructions Three instruction types: Type a: arithmetical and logical operations Type b: load and store instructions Type c: branch instructions (for jumping) 9

10 Type a: Arithmetical and Logical Instructions 1 or 2 register operands: Rs: source registers Rd: destination register n: immediate, zero-extended Other fields: op: the operation code or opcode regsel: bit 10 (1 means source operand comes from Rs register) 10

11 The TRM Registers Name R0~R7 R7 R6 PC C N Z V Register Number 0 ~ Usage Working register Normally used as link register Normally used as stack pointer Program pointer Carry flag (1 bit) Sign flag (1 bit) Zero flag (1 bit) Overflow flag (1 bit) 11

12 can be ignored

13 The Power of the Stored Program 18-bit instructions and 32-bit data stored in memory Sequence of instructions: only difference between two applications (for example, a text editor and a video game) To run a new program: No rewiring required Simply store new program in memory The processor hardware executes the program: fetches (reads) the instructions from instruction memory in sequence performs the specified operation The program counter (PC) keeps track of the current instruction In TRM, programs start at memory address 0x000 13

14 The Stored Program Assembly Code LD R2, [R0+32] ADD R1, R2 SUB R0, 12 SUB R0, R5 Machine Code 0x x08C02 0x0C00C 0x0C405 Stored Program Address Instructions 003 0C C00C C PC Instruction Memory 14

15 Type b: Load and Store Instructions memory base address register (Rs) 7-bit offset (n), zero-extended Bit 10 is always 0 for TRM, 1 for VTRM 15

16 op instruction operation code (binary) 1100 LD Rd, Rs, n If Rs = R7 then Rd := mem[n] else Rd := mem[rs+n] 1101 ST Rd, Rs, n If Rs = R7 then Mem[n] := Rd else Mem[Rs+n] := Rd 1100ddd0nnnnnnnsss 1101ddd0nnnnnnnsss

17 Type c: Branch Instructions Jump conditions (cond) 10/14-bit address offset operand (off) 17

18 Branch Instructions op instruction operation code (binary) 1110 Bc n PC := PC n, on condition c 1111 BL n R7 := PC + 1; PC := PC +1+n 1110ccccnnnnnnnnnn 1111nnnnnnnnnnnnnn 18

19 Branching Allows a program to execute instructions out of sequence. Types of branches: Conditional branches branch if equal (BEQ) branch if not equal (BNE) Unconditional branches BT jump register (BR) jump and link (BL, BLR) 19

20 cond condition meaning Mnemonic 0000 Z Zero / equal BEQ (BZS) 0001 ~Z Non-zero / unequal BNE (BZC) 0010 C Carry / above or equal (unsigned) BAE (BCS) 0011 ~C No carry / below (unsigned) BB (BCC) 0100 N Negative BN (BNS) 0101 ~N Not negative BNN (BNC) 0110 V Overflow BO (BVS) 0111 ~V No overflow BNO (BVC) 1000 ~(~C Z) Carry and no zero / above (unsigned) BA 1001 ~C Z No carry or zero / below or equal (unsigned) BBE 1010 ~(N V) N=V / greater or equal (signed) BGE 1011 N V N V / less (signed) BLT 1100 ~((N V) Z) greater or equal and ~ZF / greater (signed) BGT 1101 (N V) Z less or Z / less or equal (signed) BLE 1110 TRUE Always BT (B) 1111 FALSE Never BF N = bit 31 of result Z = all 32 bits are zero C = carry V = overflow

21 Conditional Branching (*TRM assembly*) MOV R0, 4 (*R0 = 4*) MOV R1, 1 (*R1 = 1*) SUB R0, R1 (*R0 = R0 R1 = 3*) BNE target (*branch is taken*) ADD R1, 3 (*not executed*) target: (*label*) ADD R1, R1 (*R1 = 1+1 = 2*) Labels indicate instruction locations in a program. 21

22 The Branch Not Taken (*TRM assembly*) MOV R0, 4 (*R0 = 4*) MOV R1, 1 (*R1 = 1*) SUB R0, R1 (*R0 = R0 R1 = 3*) BEQ target (*branch is not taken*) ADD R1, 3 (*executed*) target: (*label*) ADD R1, R1 (*R1 = 1+1 = 2*) 22

23 Unconditional Branching / Jumping (BT) (*TRM assembly*) MOV R0, 4 (*R0 = 4*) MOV R1, 1 (*R1 = 1*) BT target (*jump to target*) ROR R1 2 (*not executed*) target: ADD R1, R0 (*R1 = = 5*) 23

24 Review: Instruction Formats 24

25 High-Level Code Constructs if statements if/else statements while loops for loops 25

26 If Statement High-level code IF i = j THEN f := g + h; TRM assembly code (* R0 = f, R1 = g, R2 = h R3 = i, R4 = j*) f := f i; 26

27 If Statement High-level code IF i = j THEN f := g + h; f := f i; TRM assembly code (* R0 = f, R1 = g, R2 = h R3 = i, R4 = j*) SUB R4, R3 BNE L1 ADD R1, R2 MOV R0, R1 L1: SUB R0, R3 Done: BT Done Notice that the assembly tests for the opposite case (i!= j) than the test in the high-level code (i == j). 27

28 If / Else Statement High-level code IF i = j THEN f := g + h; ELSE f := f i; TRM assembly code (* R0 = f, R1 = g, R2 = h R3 = i, R4 = j *) 28

29 If / Else Statement High-level code IF i = j THEN f := g + h; ELSE f := f i; TRM assembly code (* R0 = f, R1 = g, R2 = h R3 = i, R4 = j*) SUB R4, R3 BNE L1 ADD R1, R2 MOV R0, R1 BT Done L1: SUB R0, R3 Done: BT Done 29

30 While Loops High-level code (* determines the power of x such that 2 x = 128*) TRM assembly code (*R0 = pow, R1 = x*) VAR pow, x: INTEGER; BEGIN pow := 1; x := 0; END WHILE pow # 128 DO pow := pow * 2; x := x + 1; END 30

31 While Loops High-level code (* determines the power of x such that 2 x = 128*) VAR pow, x: INTEGER; BEGIN pow := 1; x := 0; END WHILE pow # 128 DO pow := pow * 2; x := x + 1; END TRM assembly code (*R0 = pow, R1 = x*) MOV R0, 1 MOV R1, 0 while: MOV R2, R0 SUB R2, 128 BEQ done ADD R0, R0 ADD R1, 1 BT while done: BT done Notice that the assembly tests for the opposite case (pow == 128) than the test in the high-level code (pow!= 128). 31

32 For Loops The general form of a for loop is: FOR initialization TO condition BY loop operation DO loop body END initialization: executes before the loop begins condition: is tested at the beginning of each iteration loop operation: executes at the end of each iteration loop body: executes each time the condition is met 32

33 For Loops High-level code (* add the numbers from 0 to 9*) VAR sum, i: INTEGER BEGIN sum := 0; TRM assembly code (*R0 = i, R1 = sum*) END FOR i:=0 TO 9 BY 1 DO sum := sum + i; END 33

34 For Loops High-level code (* add the numbers from 0 to 9*) VAR sum, i: INTEGER BEGIN sum := 0; END FOR i:=0 TO 9 BY 1 DO sum := sum + i; END TRM assembly code (*R0 = i, R1 = sum*) MOV R1, 0 MOV R0, 0 for: MOV R2, R0 SUB R2, 10 BEQ done ADD R1, R0 ADD R0, 1 BT for done: BT done Notice that the assembly tests for the opposite case (i == 10) than the test in the high-level code (i!= 10). 34

35 Arrays Useful for accessing large amounts of similar data Array element: accessed by index Array size: number of elements in the array 35

36 Arrays 5-element array Base address = 0x010 (address of the first array element, array[0]) First step in accessing an array: load base address into a register 36

37 Arrays // high-level code int array[5]; array[0] = 5; array[0] = array[0] * 2; array[1] = array[1] * 2; ; TRM assembly code ; Array base address = R0 37

38 Arrays (*high-level code*) VAR array: ARRAY 5 OF INTEGER; array[0] := 5; array[0] := array[0] * 2; array[1] := array[1] * 2; (* TRM assembly code array base address = R0*) MOV R0, 0 (*put 0x00 in R0*) MOV R1, 5 ST R1, [R0] (*array[0] = 5*) LD R1, [R0] (*R1 = array[0]*) ROR R1, 31 BIC R1, 1 (*array[0] = array[0] * 2*) ST R1, [R0] LD R1, [R0+1] (*R1 = array[1]*) ROR R1, 31 BIC R1, 1 ST R1 [R0+1] 38

39 Arrays Using For Loops (*high-level code*) VAR array : ARRAY 1000 OF INTEGER; i: INTEGER; BEGIN FOR i:=0 TO 999 DO array[i] = array[i] * 8; END END (* TRM assembly code R0 = array base address, R3 = i*) 39

40 Arrays Using For Loops (* TRM assembly code R0 = array base address, R3 = i*) MOV R0, 0 (*R0 = 0x00*) MOV R3, 0 (*i = 0*) loop: MOV R2, R3 SUB R2, 1000 BAE done (*if i >= 1000 then done*) MOV R2, R3 ADD R2, R0 LD R1, [R2] (*R0 = array[i]*) ROR R1, 29 BIC R1, 7 ST R1, [R2] ADD R3, 1 (*i = i + 1*) BT loop (*repeat*) done: BT done 40

41 Procedure Calls Definitions Caller: calling procedure (in this case, main) Callee: called procedure (in this case, sum) High-level code VAR y: INTEGER PROCEDURE sum(a, b: INTEGER):INTEGER; BEGIN RETURN (a + b); END BEGIN y := sum(42, 7);... END 41

42 Procedure Calls Procedure calling conventions: Caller: Callee: passes arguments to callee. jumps to the callee performs the procedure returns the result to caller returns to the point of call must not overwrite registers or memory needed by the caller TRM conventions: Call procedure: branch and link (BL) Return from procedure: jump register (BR) Argument values: can be passed via stack or registers Return value: passed via register R0 42

43 Procedure Calls TRM assembly code code --- BR R x019 BL > [Proc.sum] 0x BL: jumps to sum and saves PC+1 in the return address register (R7). In this case, R7 = 0x020 after BL executes. BR R7: jumps to address in R7, in this case 0x

44 Looking Ahead Microarchitecture building TRM processor in hardware! Bring colored pencils 44