k (check node degree) and j (variable node degree)

Size: px
Start display at page:

Download "k (check node degree) and j (variable node degree)"

Transcription

1 A Parallel Turbo Decodig Message Passig Architecture for Array LDPC Codes Kira Guam, Pakaj Bhagawat, Weihuag Wag, Gwa Choi, Mark Yeary * Dept. of Electrical Egieerig, Texas A&M Uiversity, College Statio, TX * Dept. of Electrical ad Computer Egieerig, Uiversity of Oklahoma, Norma, OK Abstract The VLSI implemetatio complexity of a low desity parity check (LDPC) decoder is largely iflueced by itercoect ad the storage requiremets. Here, the proposed layout-aware layered decoder architecture utilizes the data reuse properties of mi-sum, layered decodig ad structured properties of array LDPC codes. This results i a sigificat reductio of logic ad itercoects requiremets of the decoder whe compared to the state-of-the-art LDPC decoders. The ASIC implemetatio of the proposed fully parallel architecture achieves throughput of 4.6 Gbps (for a maximum of 15 iteratios). The chip size is.3 mm x.3 mm with a gate cout of 787 K i 0.13 micro techology. 1. Itroductio Low-Desity Parity Check (LDPC) codes ad turbo codes are amog the best kow codes that operate ear Shao limit [1]. Whe compared to the decodig of turbo codes, LDPC decoders require simpler computatioal processig ad they are more suitable for parallelizatio, low implemetatio complexity, ad low latecy. While iitial LDPC decoder desigs suffered from complex itercoect issues, structured LDPC codes simplify the itercoect complexity. LDPC codes are cosidered for error correctio codig i ext geeratio digital video broadcastig (DVB-S), MIMO- WLAN 80.11,, 80.1, 80.0, Gigabit Etheret 80.3, magetic chaels(storage/recordig systems),ad log-haul optical commuicatio systems. N, K LDPC code is a liear block A biary code of codeword legth N ad iformatio block legth K that ca be described by a sparse M N parity check matrix where M deotes the umber of parity check equatios. LDPC codes ca be decoded by the Gallager s iterative two-phase message passig algorithm (TPMP) which ivolves check-ode update ad variable-ode update as two phase schedule. Various algorithms are available for check-ode updates ad widely used algorithms are sum of products (SP), misum (MS) ad Jacobia based BCJ (amed after its discoverers Bah Cocke, Jeliik ad aviv). Masour ad Shabhag [] itroduced the cocept of turbo decodig message passig (TDMP), which is sometimes also called as layered decodig, usig BCJ for their architecture-aware LDPC (AA-LDPC) codes. TDMP offers x throughput ad sigificat memory advatages whe compared to TPMP. This is later studied ad applied for differet LDPC codes usig sum of products algorithm ad its variatios i [3]. TDMP is able to reduce the umber of iteratios required by up to 50% without performace degradatio whe compared to the stadard message passig algorithm. A quatitative performace compariso for differet check updates was give by Che ad Fossorier et al [4]. Their research showed that the performace loss of offset based misum with 5-bit quatizatio is less tha 0.1dB i SN as compared with that of floatig poit SP ad BCJ. While fully-parallel LDPC decoder desigs [5] suffered from complex itercoect issues, various semi-parallel ad parallel implemetatios based o structured LDPC codes [, 6-9] alleviate the itercoect complexity. I this paper, we propose a ovel parallel micro-architecture structure for check-ode message processig uit (CNU) for the mi-sum decodig of LDPC codes. This ew micro-architecture structure employs the miimum umber of comparator uits by exploitig the cocept of survivors i the search, which results i reduced umber of comparisos, additio operatios ad additioal reductio of the memory requiremet. TDMP is applied for the offset MS for array LDPC codes. The resultig decoder architecture has sigificatly lower requiremets of logic ad itercoects whe compared to the published decoder implemetatios. The rest of the paper is orgaized as follows. Sectio itroduces the backgroud of array LDPC codes ad mi-sum the decodig algorithm. Sectio 3 presets the value-reuse property ad proposed micro-architecture structure of CNU. The data flow graph ad parallel architecture for TDMP usig offset MS is icluded i Sectio 4. Sectio 5 shows the ASIC implemetatio results ad performace compariso with related work ad Sectio 6 cocludes the paper.. Backgroud.1 Array LDPC Codes A brief review of the array codes is provided to facilitate the TDMP ad the decoder architecture. The array LDPC parity-check matrix is specified by three parameters: a prime umber p ad two itegers k (check ode degree) ad j (variable ode degree) such that j, k < p. It is give by

2 H I I I I I α α... α k 1 4 ( k 1) A = I α α... α I α α α j 1 ( j 1) ( j 1)( k 1) p p (1) where I is the idetity matrix, ad α is a permutatio matrix represetig a sigle left or p p I. Power of α i H deotes right cyclic shift of multiple cyclic shifts, with the umber of shifts give by the value of the expoet. I the followig discussio, we use the α as a permutatio matrix p p represetig a sigle left cyclic shift of I.. Mi-sum decodig of LDPC Assume biary phase shift keyig (BPSK) modulatio (a 1 is mapped to -1 ad a 0 is mapped to -1) over a additive white Gaussia oise (AWGN) chael. The received values are Gaussia with mea = ±1 x ad variaceσ. y The reliability messages used i belief propagatio (BP) based mi-sum algorithm ca be computed i two phases, viz. (1) check ode processig ad () variable ode processig. The two operatios are repeated iteratively util the decodig criterio is satisfied. This is also referred to as stadard message passig or two-phase message passig (TPMP). For the i th iteratio, Q is the message from variable ode to m check ode m, is the message from check ode m to bit ode, Μ() odes for variable ode, Ν(m) is the set of the eighborig check is the set of the eighborig variable odes for check ode m. The message passig for TPMP are calculated i the followig steps as i [4]: (1) check-ode processig: for each m ad Ν(m), ( i ) ( i ) = δ κ () ( i 1) κ = = mi Q. Ν ( m) \ m The sig of check-ode message is defied as δ ( i 1) = sg Q m Ν ( m) \ δ takes value of 1 where + or 1 (4) (3) () Variable-ode processig: for each ad m Ν(), ( 0) Qm = L + m (5) m Μ ( m) \ m ( 0) where the log-likelihood ratio of bit is L = y. (3) Decisio P = L + (6) m M A hard decisio is take where x ˆ = 0 if P ( x) 0, T ad x ˆ = 1 if P ( x ) < 0. If xˆ H = 0, the decodig process is fiished with x ˆ as the decoder output; otherwise, go to step (1). If the decodig process does t ed withi some maximum iteratio it, stop ad max output a error messeger. The reliability messages computed i misum algorithm are overestimated. The overestimatio is corrected i offset mi-sum algorithm by subtractig a positive costat β from the magitude of the i the followig way: = δ max κ β,0 (7) For (3, 6) rate 0.5 code, β is computed as 0.15 usig the desity evolutio techique [4]..3 Parallel TDMP for array LDPC I TDMP, the array LDPC with j block rows ca be viewed as cocateatio of j layers or costituet sub-codes similar to observatios made for AA-LDPC codes i []. After the check-ode processig is fiished for oe block row, the messages are immediately used to update the variable odes (), whose results are the provided for processig the ext block row of check odes(1). This differs from TPMP where all check odes are processed first ad the the variable ode messages will be computed. Each decodig iteratio i TDMP has j umber of subiteratios. I the begiig of the decodig process, variable messages are iitialized as chael values ad they are used to process the check odes of the first block row. After completio of that block row, variable messages are updated with the ew check ode messages. This cocludes the first sub-iteratio. I similar fashio, result of check-ode processig of the secod block row is immediately used i the same iteratio to update the variable ode messages for third block row. The completio of check-ode processig ad associated variable-ode processig of all block rows costitutes oe iteratio. The TDMP ca be described with equatio (8-11): (0) (0) = P = L (8) 0, i = 1,, it, [Iteratio loop] max

3 l = 1,,, j = 1,,... k ( ) ( ) i Ql, = P l ( l, ) l, = f ( Q l, ) ( l, ) i ( l, ) i = Q +, [Sub-iteratio loop] [Block colu loop] ( i 1) [ ] [ ] [ ] [ ], (9) (10) P (11) where the vectors ( i ) ad ( i ) represet all the ad Q l, Q l, messages i each block of H matrix, s( ) deotes the shift coefficiet for the block i l th block row ad th i 1 S ( ) block colu of the H matrix [ ] deotes that i 1 the vector is cyclically shifted up by the amout s( ), k is the check-ode degree of the block row. A egative sig o s( ) idicates that it is cyclic dow shift (equivalet cyclic left shift). f ( ) deotes the check-ode processig, which ca be doe usig BCJ, SP or MS. For the proposed work we use MS as defied i equatio (-7). As soo as the output vector correspodig to each block colu i H matrix l, for a block row l is available, this could be used to S ( ) produce updated sum [ ] P (10). This could be immediately used i (9) to process block row l + 1 except that the shift s( ) imposed o P has to be udoe ad a ew shift s( l + 1, ) has to be imposed. This could be simply doe by imposig a shift correspodig to the differece of s( l + 1, ) ad s( ). Due to the structure of array LDPC H S, ) matrix, the [ ] ( l P i each block colu eed to go through either a) a cyclic dow shift of 1or b)cyclic up shift of ( 1 if we do layered decodig. I j ) additio we ca do parallel processig of block-colu loop usig p parallel CNUs. The property a) is possible due to costat differece of shift across block colus i array code s H matrix ad layers are processed i the order from 1 to j i each iteratio while the property b) is due to the fact that we eed to process layer 1 after processig layer j. We utilize this property i the proposed layout aware architecture by implemetig the two required cyclic shifts with wirig (ad cocetric layout) ad by processig all block colus i a layer i parallel. 3. Value-reuse Properties of Check Node Processig of Mi-Sum Decodig Oe of the key cotributios of this paper is the observatio that offset mi-sum decodig algorithm share the value-reuse property, as explaied below, hece reduce the logic ad message passig requiremet of the decoder. For each check ode m, Ν m takes oly values ad they are the two least miimum of iput magitude values., δ takes value of either + 1or 1 Sice Ν( m) ad ( i ) takes oly values. Equatio (3) gives rise to oly 3 possible values for the whole set Ν m. I a VLSI implemetatio, this property greatly simplifies the logic ad reduces the memory. This result would greatly simplify the umber of comparisos required as well as the memory eeded to store CNU outputs. This also meas reductio i correctio computatios. Normally CNU (check-ode uit) processig is doe usig the siged magitude arithmetic for (3) ad VNU (variable-ode uit processig) equatio (4) is doe i s complemet arithmetic. This requires s complemet to siged coversio at the iputs of CNU ad siged to s complemet at the output of CNU. This would mea that we eed to apply s complemet to oly two values istead of k values at the output of CNU. The work i [8] proposed a parallel CNU for MS that requires k( (log k 1)) comparators, 4 k 5-bit addersthe reaso for this complexity is ot usig the value reuse property of MS. I steps 1 ad below, cosider the k = case of rate 0.5 (4,8) code so that 8 ad assume the word legth of siged magitude bit ode messages is 5 so that there are 4 bits allocated for magitude. Step 1: Locate the two miimum values of the array Step1.1: Fid the first miimum usig the biary tree. Figure 1a gives a biary tree of comparators. Each comparator take two 4 bit iput words ad produces the miimum ad a flag which is set to 1 if the upper iput is less tha the lower iput Step 1.: Select the survivors by usig the comparator output flags as the cotrol iputs to multiplexes. For example i the last stage of the comparator tree the value other tha the least miimum is the survivor. No further comparisos are ecessary alog the tree path to the survivor. We trace back the survivors usig the comparator outputs. For a biary tree for iput vector of legth 8, we eed to 1, 4 to 1 ad 8 to 1 multiplexers. At ay stage of biary tree we have oly oe survivor. So there would be comparisos i sequetial fashio log k survivors ad log k 1

4 Step 1.3: Perform the required comparisos amog survivors i sequetial fashio. to K1 ad K to produce M1 ad M. Now compute M1 ad/or M. Now based o computed sig iformatio by XO logic(4) ad idex of K1, is set to oe of the 3 possible values M1,-M1, +/- M. (see Figure ). (a) a) Figure 1: Fider for the two least miimum i CNUBiary tree to fid the least miimum. (b) Traceback multiplexers ad comparators o survivors to fid the secod miimum. Multiplexers for selectig survivors are ot show. I Figure 1, C0, C1 ad C are 1 bit outputs correspodig to A<B coditio. 0 i C0 otatio is used to deote first level of outputs from right ad so o C[0] does mea the 1 bit comparator output at the first output of comparators at 3 rd level outputs from right ad so o. A,A1 ad A0 are magitudes(usually 4 bits wide[]) of bit ode messages. 0 i A0 otatio is used to deote first level of iputs ad so o. A0[0] does mea the 4bit iput word at the first iput of first level of iputs ad so o. It does ot mea 0 th bit of A0. K1 =A0 [C0 C1[C0] C[C0C1[C0]]] is the least miimum. The 3 bit trace back C0 C1[C0] C[C0C1[C0]] gives the locatio of the least miimum. See Figure c. The followig iputs are obtaied from the itermediate odes of the search tree. We have to use -i 1, 4-i 1 ad 8-i 1multiplexers respectively to obtai the followig survivors. B= A[c0];, B1= A1[!c1 c0]]; B0= A0[!c c1 c0] Step : This steps produces the outputs accordig to (7) i the followig optimized fashio. Apply the offset Figure : Proposed Parallel CNU based o Value-reuse property of Mi-Sum 4. Fully Parallel Architecture Usig TDMP ad Mi-Sum A ew data flow graph, see Figure 3, is desiged based o the TDMP ad o the value reuse property of mi-sum algorithm described above. For ease of discussio, we will illustrate the architecture for a specific structured code: Array code of legth 08 described i sectio, j = 3, k = 6 ad p = 347. First, fuctioality of each block i the architecture is explaied. A check ode process uit (CNU) is the parallel CNU based o offset mi-sum described i previous sectio. The CNU array is composed of p computatio uits that compute the messages for each block row i fully parallel fashio. Sice messages of previous j 1 block rows, are eeded for TDMP, the compressed iformatio of them is stored i FS register baks. There is oe register bak of depth 1, which j is i this case, coected with each CNU. Each fial state cotais M1,-M1,+/-M ad idex for M1. The sig bits are stored i sig flip-flops. The total umber of sig flip-flops is k ad each block row has pk sig flip-flops. We eed 1 j of such sig flip-flop baks i total. p umber of select uits is used for old. A select uit, whose fuctioality ad structure is the same as the block deoted as select i CNU, geerates the messages for 6( = k) edges of a check ode from 3 values stored i fial state register i parallel fashio. This uit ca be treated as de-compressor of the check ode edge iformatio which is stored i compact form i FS registers.i the begiig of the decodig process (9-11), P matrix(of dimesios px k) is set to received chael values i the first clock cycle(i.e. the first subiteratio) while the output matrix of select uit is set to zero matrix. The multiplexer array at the iput of P buffer is used for this iitializatio. The P matrix is computed by addig the shifted Q matrix(labeled as l Q shift i Figure 3)to the output matrix l of the CNU

5 array(labeled as ew ). The compressed iformatio is stored i the register baks FS ad sig so that these ca be used to geerate old for the l th sub-iteratio i ext iteratio. to each row i H matrix. MPU I commuicates with its 5(=k-1) adjacet eighbors (MPUs whose umbers are mod(i+1,p)...mod(i+5,p)) to achieve cyclic dow shifts of 1,,..5 respectively for block colus, 3 6 i H matrix (1) as show i Figure ASIC IMPLEMENTATION ESULTS Figure 3: Dataflow graph of the proposed parallel architecture for layered decoder Figure 4: a)illustratio of coectios betwee Message Processig uits to achieve cyclic dow shift of (-1) o each block colu b) Cocetric layout to accommodate 347 message processig uits. Coectios for cyclic up shift of (=(j-1).) are ot show. Note that the P matrix that is geerated ca be used immediately to geerate the Q matrix as the iput to the CNU array as CNU array is ready to process the ext block row. Now each block colu i the P message matrix will udergo a cyclic shift by the amout of differece of the shifts of the block row that is processed ad the previous block row that was just processed i the previous sub-iteratio. Figure 4 gives the layout details for the proposed decoder. The k adder uits, k select uit is termed as the parallel variable-ode uit (VNU). A message processig uit (MPU) cosists of a parallel CNU, a parallel VNU ad associated registers belogig Figure 5: BE Performace of the decoder To achieve the same BE as that of TPMP schedule o SP, TDMP schedule o offset MS eed half the umber of iteratios. This essetially doubles the throughput for the give amout of parallelizatio. Parallel decoder for TDMP or layered decodig eeds to use the hardware to decode oe layer oly while the parallel decoder for TPMP will have the hardware to decode all the layers simultaeously. So TDMP decoder takes j clock cycles to fiish j sub-iteratios(for j layers) to costitute iteratio as explaied i Sectio. If we use 5-bit precisio i ad Q messages ad 6-bit precisio i P messages to achieve almost the same performace as that of the floatig poit SP with oly 0. db performace degradatio. The proposed parallel CNU for offset MS is of very low complexity ad requires k + k 4-bit comparators ad k + 4 log 5-bit adders. The work i [8] proposed a parallel CNU for MS that requires k( (log k 1)) comparators, 4 k 5-bit adders-the reaso for this complexity is ot usig the value re-use property of MS. It is also observed that istead of storig all the messages, the compressed iformatio is stored alog with the sig bits of the messages. This result i a reductio of memory is aroud of 0%-7% for 5 bit messages based o the check ode degree k of the code. So, i the proposed architecture desiged to support the code with k = 6, the savigs of memory is 0%. I additio there are sigificat savigs due to the layered decodig ad parallel architecture. We implemeted the proposed fully parallel layered decoder architecture o 0.13 micro techology. We used the stadard cells vsclib013[10].

6 TABLE I: COMPAISON WITH THE EXISTING WOK [] [5] [9] Proposed Decoded Throughput 640 Mbps 1.0 Gbps 1.0 Gbps 4.6 Gbps Area 14.3 mm, 5.5 mm 8.74 mm 5.9 mm Memory 51,680 bits (excludig 34,816 bits 34,816 bits 7046 bits flip-flops ad FIFO s) (scattered flip-flops) (scattered flip-flops) (scattered flip-flops) Iterleaver/outer 3.8 mm -Network 6.5 mm -Network NA 0.89 mm -Network Frequecy 15 MHz 64 MHz 64 MHz 100 MHz LDPC Code AA-LDPC, Structured adom ad irregular Modified Array Code Array Code rate 0.5 ad (3,6) code rate 0.5 code rate 0.5 ad (3,6) code rate 0.5 ad (3,6) code Block Legth Check Node update BCJ SP SP Offset MS Decodig Schedule TDMP TPMP TPMP TDMP CMOS Techology 0.18 µ 0.16 µ 0.16 µ 0.13 µ The area of the chip is.3 mm x.3 mm ad the post routig frequecy is 100 MHz. The estimated gate cout is 787 K -iput NAND gates i 0.13 micro techology. The ASIC implemetatio of the proposed parallel architecture achieves a decoded throughput of 4.6 Gbps for 15 iteratios ad user data throughput of.3 Gbps. The area distributio of the CNU, VNU, storage flip-flops to support layered decodig, sychroizatio flip-flops to support multiple iteratios ad wirig is respectively 3%, 9%, 1%, 10% ad 17%. Figure 6: Net legth distributio of top level message passig ets for code with k=6 ad p=347 The et legth distributio of the message passig wires P is give i Figure 6. Most of the wires are short due to cocetric layout. The et legth distributio of the chael LL message ets(which eed ot be shifted as the first block row of array H matrix have all zero shift coefficiets) ad decoded bit ets has uiform bis at i*0.1 mm, i = 1,,..., 10 assumig that the iputs ad outputs are also arraged i rig fashio aroud the chip. Note that chael LLs are iputs to decoder message processig uits for every ew frame-every 45 clock cycles assumig 15 iteratios ad 45(=15*3) subiteratios. However the additioal IO circuitry (the serial to parallel ad parallel to serial coversio aroud the chip) which is applicatio depedet is ot accouted i the chip area ad is estimated ot to exceed 15% of chip area. Table I gives the performace compariso with the state of the art work. This work offers a syergetic combiatio of array LDPC codes [6], reduced complexity decodig [4], layered decodig [] by providig the ovel micro-architecture structures ad architectures to offer sigificat advatages. 6. Coclusio We preset layout-aware parallel decoder architecture for turbo decodig message passig of array LDPC codes usig the mi-sum algorithm for check ode update. Our work offers several advatages whe compared to the other state of the art LDPC decoders i terms of sigificat reductio i logic ad itercoect. efereces [1] D.J.C. MacKay ad.m. Neal. Near Shao Limit Performace of Low Desity Parity Check codes Electroics Letters, volume 3, pp , Aug [] M. Masour ad N. Shabhag, "A 640-Mb/s 048-bit programmable LDPC decoder chip," IEEE Joural of Solid-State Circuits, vol. 41, o.3, pp , March 006. [3] Hocevar, D.E., "A reduced complexity decoder architecture via layered decodig of LDPC codes," IEEE SiPS 004 pp , Oct. 004 [4] J. Che ad M. Fossorier, `Ǹear Optimum Uiversal Belief Propagatio Based Decodig of Low-Desity Parity Check Codes ', IEEE Trasactios o Commuicatios, vol. COM-50, pp , March 00. [5] Blaksby, A.J.; Howlad,C.J, A 690-mW 1-Gb/s 104-b, rate-1/ low-desity parity-check code decoder, IEEE Joural of Solid-State Circuits, vol. 37, o..3, Mar 00 Pages: [6] S. Olcer, "Decoder architecture for array-code-based LDPC codes," Global Telecommuicatios Coferece, 003. GLOBECOM '03. IEEE, vol.4, o.pp vol.4, 1-5 Dec. 003 [7] E. Kim, G. Choi, "Diagoal low-desity parity-check code for simplified routig i decoder," IEEE SiPS 005, vol., o.pp , -4 Nov. 005 [8] M. Karkooti ad J. Cavallaro, Semi-parallel recofigurable architectures for real-time LDPC decodig, Proceedigs of Iteratioal Coferece o Iformatio Techology, Codig ad Computig, vol. 1, pp , 004. [9] V. Nagaraja, et a "High-throughput VLSI implemetatios of iterative decoders ad related code costructio problems,", GLOBECOM '004. IEEE, vol.1, pp , vol. 1, 9 Nov.-3 Dec [10] Ope source stadard cell library,

Improvement of the Orthogonal Code Convolution Capabilities Using FPGA Implementation

Improvement of the Orthogonal Code Convolution Capabilities Using FPGA Implementation Improvemet of the Orthogoal Code Covolutio Capabilities Usig FPGA Implemetatio Naima Kaabouch, Member, IEEE, Apara Dhirde, Member, IEEE, Saleh Faruque, Member, IEEE Departmet of Electrical Egieerig, Uiversity

More information

Elementary Educational Computer

Elementary Educational Computer Chapter 5 Elemetary Educatioal Computer. Geeral structure of the Elemetary Educatioal Computer (EEC) The EEC coforms to the 5 uits structure defied by vo Neuma's model (.) All uits are preseted i a simplified

More information

DESIGN AND ANALYSIS OF LDPC DECODERS FOR SOFTWARE DEFINED RADIO

DESIGN AND ANALYSIS OF LDPC DECODERS FOR SOFTWARE DEFINED RADIO DESIGN AND ANALYSIS OF LDPC DECODERS FOR SOFTWARE DEFINED RADIO Sagwo Seo, Trevor Mudge Advaced Computer Architecture Laboratory Uiversity of Michiga at A Arbor {swseo, tm}@umich.edu Yumig Zhu, Chaitali

More information

FPGA IMPLEMENTATION OF BASE-N LOGARITHM. Salvador E. Tropea

FPGA IMPLEMENTATION OF BASE-N LOGARITHM. Salvador E. Tropea FPGA IMPLEMENTATION OF BASE-N LOGARITHM Salvador E. Tropea Electróica e Iformática Istituto Nacioal de Tecología Idustrial Bueos Aires, Argetia email: salvador@iti.gov.ar ABSTRACT I this work, we preset

More information

EE260: Digital Design, Spring /16/18. n Example: m 0 (=x 1 x 2 ) is adjacent to m 1 (=x 1 x 2 ) and m 2 (=x 1 x 2 ) but NOT m 3 (=x 1 x 2 )

EE260: Digital Design, Spring /16/18. n Example: m 0 (=x 1 x 2 ) is adjacent to m 1 (=x 1 x 2 ) and m 2 (=x 1 x 2 ) but NOT m 3 (=x 1 x 2 ) EE26: Digital Desig, Sprig 28 3/6/8 EE 26: Itroductio to Digital Desig Combiatioal Datapath Yao Zheg Departmet of Electrical Egieerig Uiversity of Hawaiʻi at Māoa Combiatioal Logic Blocks Multiplexer Ecoders/Decoders

More information

A REDUCED-COMPLEXITY LDPC DECODING ALGORITHM WITH CHEBYSHEV POLYNOMIAL FITTING

A REDUCED-COMPLEXITY LDPC DECODING ALGORITHM WITH CHEBYSHEV POLYNOMIAL FITTING Joural of Theoretical ad Applied Iformatio Techology st March. Vol. 49 No. 5 - JATIT & LLS. All rights reserved. ISSN: 99-8645 www.jatit.org E-ISSN: 87-95 A REDUCED-COMPLEXITY LDPC DECODING ALGORITHM WITH

More information

The Counterchanged Crossed Cube Interconnection Network and Its Topology Properties

The Counterchanged Crossed Cube Interconnection Network and Its Topology Properties WSEAS TRANSACTIONS o COMMUNICATIONS Wag Xiyag The Couterchaged Crossed Cube Itercoectio Network ad Its Topology Properties WANG XINYANG School of Computer Sciece ad Egieerig South Chia Uiversity of Techology

More information

Fully Parallel Window Decoder Architecture for Spatially-Coupled LDPC Codes

Fully Parallel Window Decoder Architecture for Spatially-Coupled LDPC Codes Fully Parallel Widow Decoder Architecture for Spatially-Coupled LDPC Codes Najeeb Ul Hassa, Marti Schlüter, ad Gerhard P. Fettweis Vodafoe Chair Mobile Commuicatios Systems, Dresde Uiversity of Techology

More information

BOOLEAN MATHEMATICS: GENERAL THEORY

BOOLEAN MATHEMATICS: GENERAL THEORY CHAPTER 3 BOOLEAN MATHEMATICS: GENERAL THEORY 3.1 ISOMORPHIC PROPERTIES The ame Boolea Arithmetic was chose because it was discovered that literal Boolea Algebra could have a isomorphic umerical aspect.

More information

COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface. Chapter 4. The Processor. Part A Datapath Design

COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface. Chapter 4. The Processor. Part A Datapath Design COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Iterface 5 th Editio Chapter The Processor Part A path Desig Itroductio CPU performace factors Istructio cout Determied by ISA ad compiler. CPI ad

More information

Behavioral Modeling in Verilog

Behavioral Modeling in Verilog Behavioral Modelig i Verilog COE 202 Digital Logic Desig Dr. Muhamed Mudawar Kig Fahd Uiversity of Petroleum ad Mierals Presetatio Outlie Itroductio to Dataflow ad Behavioral Modelig Verilog Operators

More information

Chapter 3 Classification of FFT Processor Algorithms

Chapter 3 Classification of FFT Processor Algorithms Chapter Classificatio of FFT Processor Algorithms The computatioal complexity of the Discrete Fourier trasform (DFT) is very high. It requires () 2 complex multiplicatios ad () complex additios [5]. As

More information

Load balanced Parallel Prime Number Generator with Sieve of Eratosthenes on Cluster Computers *

Load balanced Parallel Prime Number Generator with Sieve of Eratosthenes on Cluster Computers * Load balaced Parallel Prime umber Geerator with Sieve of Eratosthees o luster omputers * Soowook Hwag*, Kyusik hug**, ad Dogseug Kim* *Departmet of Electrical Egieerig Korea Uiversity Seoul, -, Rep. of

More information

3D Model Retrieval Method Based on Sample Prediction

3D Model Retrieval Method Based on Sample Prediction 20 Iteratioal Coferece o Computer Commuicatio ad Maagemet Proc.of CSIT vol.5 (20) (20) IACSIT Press, Sigapore 3D Model Retrieval Method Based o Sample Predictio Qigche Zhag, Ya Tag* School of Computer

More information

Image Segmentation EEE 508

Image Segmentation EEE 508 Image Segmetatio Objective: to determie (etract) object boudaries. It is a process of partitioig a image ito distict regios by groupig together eighborig piels based o some predefied similarity criterio.

More information

Reversible Realization of Quaternary Decoder, Multiplexer, and Demultiplexer Circuits

Reversible Realization of Quaternary Decoder, Multiplexer, and Demultiplexer Circuits Egieerig Letters, :, EL Reversible Realizatio of Quaterary Decoder, Multiplexer, ad Demultiplexer Circuits Mozammel H.. Kha, Member, ENG bstract quaterary reversible circuit is more compact tha the correspodig

More information

BASED ON ITERATIVE ERROR-CORRECTION

BASED ON ITERATIVE ERROR-CORRECTION A COHPARISO OF CRYPTAALYTIC PRICIPLES BASED O ITERATIVE ERROR-CORRECTIO Miodrag J. MihaljeviC ad Jova Dj. GoliC Istitute of Applied Mathematics ad Electroics. Belgrade School of Electrical Egieerig. Uiversity

More information

Fast Fourier Transform (FFT) Algorithms

Fast Fourier Transform (FFT) Algorithms Fast Fourier Trasform FFT Algorithms Relatio to the z-trasform elsewhere, ozero, z x z X x [ ] 2 ~ elsewhere,, ~ e j x X x x π j e z z X X π 2 ~ The DFS X represets evely spaced samples of the z- trasform

More information

Lecture 1: Introduction and Strassen s Algorithm

Lecture 1: Introduction and Strassen s Algorithm 5-750: Graduate Algorithms Jauary 7, 08 Lecture : Itroductio ad Strasse s Algorithm Lecturer: Gary Miller Scribe: Robert Parker Itroductio Machie models I this class, we will primarily use the Radom Access

More information

Joint Message-Passing Symbol-Decoding of LDPC Coded Signals over Partial-Response Channels

Joint Message-Passing Symbol-Decoding of LDPC Coded Signals over Partial-Response Channels Joit Message-Passig Symbol-Decodig of LDPC Coded Sigals over Partial-Respose Chaels Rathakumar Radhakrisha ad ae Vasić Departmet of Electrical ad Computer Egieerig Uiversity of Arizoa, Tucso, AZ-8572 Email:

More information

CSC 220: Computer Organization Unit 11 Basic Computer Organization and Design

CSC 220: Computer Organization Unit 11 Basic Computer Organization and Design College of Computer ad Iformatio Scieces Departmet of Computer Sciece CSC 220: Computer Orgaizatio Uit 11 Basic Computer Orgaizatio ad Desig 1 For the rest of the semester, we ll focus o computer architecture:

More information

A Study on the Performance of Cholesky-Factorization using MPI

A Study on the Performance of Cholesky-Factorization using MPI A Study o the Performace of Cholesky-Factorizatio usig MPI Ha S. Kim Scott B. Bade Departmet of Computer Sciece ad Egieerig Uiversity of Califoria Sa Diego {hskim, bade}@cs.ucsd.edu Abstract Cholesky-factorizatio

More information

Lecture Notes 6 Introduction to algorithm analysis CSS 501 Data Structures and Object-Oriented Programming

Lecture Notes 6 Introduction to algorithm analysis CSS 501 Data Structures and Object-Oriented Programming Lecture Notes 6 Itroductio to algorithm aalysis CSS 501 Data Structures ad Object-Orieted Programmig Readig for this lecture: Carrao, Chapter 10 To be covered i this lecture: Itroductio to algorithm aalysis

More information

Ones Assignment Method for Solving Traveling Salesman Problem

Ones Assignment Method for Solving Traveling Salesman Problem Joural of mathematics ad computer sciece 0 (0), 58-65 Oes Assigmet Method for Solvig Travelig Salesma Problem Hadi Basirzadeh Departmet of Mathematics, Shahid Chamra Uiversity, Ahvaz, Ira Article history:

More information

Dynamic Programming and Curve Fitting Based Road Boundary Detection

Dynamic Programming and Curve Fitting Based Road Boundary Detection Dyamic Programmig ad Curve Fittig Based Road Boudary Detectio SHYAM PRASAD ADHIKARI, HYONGSUK KIM, Divisio of Electroics ad Iformatio Egieerig Chobuk Natioal Uiversity 664-4 Ga Deokji-Dog Jeoju-City Jeobuk

More information

UNIVERSITY OF MORATUWA

UNIVERSITY OF MORATUWA UNIVERSITY OF MORATUWA FACULTY OF ENGINEERING DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING B.Sc. Egieerig 2014 Itake Semester 2 Examiatio CS2052 COMPUTER ARCHITECTURE Time allowed: 2 Hours Jauary 2016

More information

EE 459/500 HDL Based Digital Design with Programmable Logic. Lecture 13 Control and Sequencing: Hardwired and Microprogrammed Control

EE 459/500 HDL Based Digital Design with Programmable Logic. Lecture 13 Control and Sequencing: Hardwired and Microprogrammed Control EE 459/500 HDL Based Digital Desig with Programmable Logic Lecture 13 Cotrol ad Sequecig: Hardwired ad Microprogrammed Cotrol Refereces: Chapter s 4,5 from textbook Chapter 7 of M.M. Mao ad C.R. Kime,

More information

Computer Systems - HS

Computer Systems - HS What have we leared so far? Computer Systems High Level ENGG1203 2d Semester, 2017-18 Applicatios Sigals Systems & Cotrol Systems Computer & Embedded Systems Digital Logic Combiatioal Logic Sequetial Logic

More information

Parallel Polygon Approximation Algorithm Targeted at Reconfigurable Multi-Ring Hardware

Parallel Polygon Approximation Algorithm Targeted at Reconfigurable Multi-Ring Hardware Parallel Polygo Approximatio Algorithm Targeted at Recofigurable Multi-Rig Hardware M. Arif Wai* ad Hamid R. Arabia** *Califoria State Uiversity Bakersfield, Califoria, USA **Uiversity of Georgia, Georgia,

More information

Appendix D. Controller Implementation

Appendix D. Controller Implementation COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Iterface 5 th Editio Appedix D Cotroller Implemetatio Cotroller Implemetatios Combiatioal logic (sigle-cycle); Fiite state machie (multi-cycle, pipelied);

More information

Improving Template Based Spike Detection

Improving Template Based Spike Detection Improvig Template Based Spike Detectio Kirk Smith, Member - IEEE Portlad State Uiversity petra@ee.pdx.edu Abstract Template matchig algorithms like SSE, Covolutio ad Maximum Likelihood are well kow for

More information

6.854J / J Advanced Algorithms Fall 2008

6.854J / J Advanced Algorithms Fall 2008 MIT OpeCourseWare http://ocw.mit.edu 6.854J / 18.415J Advaced Algorithms Fall 2008 For iformatio about citig these materials or our Terms of Use, visit: http://ocw.mit.edu/terms. 18.415/6.854 Advaced Algorithms

More information

9.1. Sequences and Series. Sequences. What you should learn. Why you should learn it. Definition of Sequence

9.1. Sequences and Series. Sequences. What you should learn. Why you should learn it. Definition of Sequence _9.qxd // : AM Page Chapter 9 Sequeces, Series, ad Probability 9. Sequeces ad Series What you should lear Use sequece otatio to write the terms of sequeces. Use factorial otatio. Use summatio otatio to

More information

A SOFTWARE MODEL FOR THE MULTILAYER PERCEPTRON

A SOFTWARE MODEL FOR THE MULTILAYER PERCEPTRON A SOFTWARE MODEL FOR THE MULTILAYER PERCEPTRON Roberto Lopez ad Eugeio Oñate Iteratioal Ceter for Numerical Methods i Egieerig (CIMNE) Edificio C1, Gra Capitá s/, 08034 Barceloa, Spai ABSTRACT I this work

More information

Performance Plus Software Parameter Definitions

Performance Plus Software Parameter Definitions Performace Plus+ Software Parameter Defiitios/ Performace Plus Software Parameter Defiitios Chapma Techical Note-TG-5 paramete.doc ev-0-03 Performace Plus+ Software Parameter Defiitios/2 Backgroud ad Defiitios

More information

A New Morphological 3D Shape Decomposition: Grayscale Interframe Interpolation Method

A New Morphological 3D Shape Decomposition: Grayscale Interframe Interpolation Method A ew Morphological 3D Shape Decompositio: Grayscale Iterframe Iterpolatio Method D.. Vizireau Politehica Uiversity Bucharest, Romaia ae@comm.pub.ro R. M. Udrea Politehica Uiversity Bucharest, Romaia mihea@comm.pub.ro

More information

GPUMP: a Multiple-Precision Integer Library for GPUs

GPUMP: a Multiple-Precision Integer Library for GPUs GPUMP: a Multiple-Precisio Iteger Library for GPUs Kaiyog Zhao ad Xiaowe Chu Departmet of Computer Sciece, Hog Kog Baptist Uiversity Hog Kog, P. R. Chia Email: {kyzhao, chxw}@comp.hkbu.edu.hk Abstract

More information

. Written in factored form it is easy to see that the roots are 2, 2, i,

. Written in factored form it is easy to see that the roots are 2, 2, i, CMPS A Itroductio to Programmig Programmig Assigmet 4 I this assigmet you will write a java program that determies the real roots of a polyomial that lie withi a specified rage. Recall that the roots (or

More information

Fundamentals of Media Processing. Shin'ichi Satoh Kazuya Kodama Hiroshi Mo Duy-Dinh Le

Fundamentals of Media Processing. Shin'ichi Satoh Kazuya Kodama Hiroshi Mo Duy-Dinh Le Fudametals of Media Processig Shi'ichi Satoh Kazuya Kodama Hiroshi Mo Duy-Dih Le Today's topics Noparametric Methods Parze Widow k-nearest Neighbor Estimatio Clusterig Techiques k-meas Agglomerative Hierarchical

More information

Wavelet Transform. CSE 490 G Introduction to Data Compression Winter Wavelet Transformed Barbara (Enhanced) Wavelet Transformed Barbara (Actual)

Wavelet Transform. CSE 490 G Introduction to Data Compression Winter Wavelet Transformed Barbara (Enhanced) Wavelet Transformed Barbara (Actual) Wavelet Trasform CSE 49 G Itroductio to Data Compressio Witer 6 Wavelet Trasform Codig PACW Wavelet Trasform A family of atios that filters the data ito low resolutio data plus detail data high pass filter

More information

ALU Augmentation for MPEG-4 Repetitive Padding

ALU Augmentation for MPEG-4 Repetitive Padding ALU Augmetatio for MPEG-4 Repetitive Paddig Georgi Kuzmaov Stamatis Vassiliadis Computer Egieerig Lab, Electrical Egieerig Departmet, Faculty of formatio Techology ad Systems, Delft Uiversity of Techology,

More information

Lecture 5. Counting Sort / Radix Sort

Lecture 5. Counting Sort / Radix Sort Lecture 5. Coutig Sort / Radix Sort T. H. Corme, C. E. Leiserso ad R. L. Rivest Itroductio to Algorithms, 3rd Editio, MIT Press, 2009 Sugkyukwa Uiversity Hyuseug Choo choo@skku.edu Copyright 2000-2018

More information

Chapter 3. Floating Point Arithmetic

Chapter 3. Floating Point Arithmetic COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Iterface 5 th Editio Chapter 3 Floatig Poit Arithmetic Review - Multiplicatio 0 1 1 0 = 6 multiplicad 32-bit ALU shift product right multiplier add

More information

( n+1 2 ) , position=(7+1)/2 =4,(median is observation #4) Median=10lb

( n+1 2 ) , position=(7+1)/2 =4,(median is observation #4) Median=10lb Chapter 3 Descriptive Measures Measures of Ceter (Cetral Tedecy) These measures will tell us where is the ceter of our data or where most typical value of a data set lies Mode the value that occurs most

More information

Design of Efficient Pipelined Radix-2 2 Single Path Delay Feedback FFT

Design of Efficient Pipelined Radix-2 2 Single Path Delay Feedback FFT IOSR Joural of VLSI ad Sigal Processig IOSR-JVSP Volume Issue Ver. I May-Ju. 0 PP 88-9 e-iss: 9 00 p-iss o. : 9 97 www.iosrjourals.org Desig of Efficiet Pipelied Radi- Sigle Path Delay Feedbac FFT isha

More information

Cubic Polynomial Curves with a Shape Parameter

Cubic Polynomial Curves with a Shape Parameter roceedigs of the th WSEAS Iteratioal Coferece o Robotics Cotrol ad Maufacturig Techology Hagzhou Chia April -8 00 (pp5-70) Cubic olyomial Curves with a Shape arameter MO GUOLIANG ZHAO YANAN Iformatio ad

More information

Outline. Applications of FFT in Communications. Fundamental FFT Algorithms. FFT Circuit Design Architectures. Conclusions

Outline. Applications of FFT in Communications. Fundamental FFT Algorithms. FFT Circuit Design Architectures. Conclusions FFT Circuit Desig Outlie Applicatios of FFT i Commuicatios Fudametal FFT Algorithms FFT Circuit Desig Architectures Coclusios DAB Receiver Tuer OFDM Demodulator Chael Decoder Mpeg Audio Decoder 56/5/ 4/48

More information

Lower Bounds for Sorting

Lower Bounds for Sorting Liear Sortig Topics Covered: Lower Bouds for Sortig Coutig Sort Radix Sort Bucket Sort Lower Bouds for Sortig Compariso vs. o-compariso sortig Decisio tree model Worst case lower boud Compariso Sortig

More information

IMP: Superposer Integrated Morphometrics Package Superposition Tool

IMP: Superposer Integrated Morphometrics Package Superposition Tool IMP: Superposer Itegrated Morphometrics Package Superpositio Tool Programmig by: David Lieber ( 03) Caisius College 200 Mai St. Buffalo, NY 4208 Cocept by: H. David Sheets, Dept. of Physics, Caisius College

More information

Lecture 2: Spectra of Graphs

Lecture 2: Spectra of Graphs Spectral Graph Theory ad Applicatios WS 20/202 Lecture 2: Spectra of Graphs Lecturer: Thomas Sauerwald & He Su Our goal is to use the properties of the adjacecy/laplacia matrix of graphs to first uderstad

More information

Chapter 4 The Datapath

Chapter 4 The Datapath The Ageda Chapter 4 The Datapath Based o slides McGraw-Hill Additioal material 24/25/26 Lewis/Marti Additioal material 28 Roth Additioal material 2 Taylor Additioal material 2 Farmer Tae the elemets that

More information

Copyright 2016 Ramez Elmasri and Shamkant B. Navathe

Copyright 2016 Ramez Elmasri and Shamkant B. Navathe Copyright 2016 Ramez Elmasri ad Shamkat B. Navathe CHAPTER 19 Query Optimizatio Copyright 2016 Ramez Elmasri ad Shamkat B. Navathe Itroductio Query optimizatio Coducted by a query optimizer i a DBMS Goal:

More information

COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface. Chapter 4. The Processor. Single-Cycle Disadvantages & Advantages

COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface. Chapter 4. The Processor. Single-Cycle Disadvantages & Advantages COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Iterface 5 th Editio Chapter 4 The Processor Pipeliig Sigle-Cycle Disadvatages & Advatages Clk Uses the clock cycle iefficietly the clock cycle must

More information

Pruning and Summarizing the Discovered Time Series Association Rules from Mechanical Sensor Data Qing YANG1,a,*, Shao-Yu WANG1,b, Ting-Ting ZHANG2,c

Pruning and Summarizing the Discovered Time Series Association Rules from Mechanical Sensor Data Qing YANG1,a,*, Shao-Yu WANG1,b, Ting-Ting ZHANG2,c Advaces i Egieerig Research (AER), volume 131 3rd Aual Iteratioal Coferece o Electroics, Electrical Egieerig ad Iformatio Sciece (EEEIS 2017) Pruig ad Summarizig the Discovered Time Series Associatio Rules

More information

Construction of Regular and Irregular QC-LDPC Codes: a Finite Field Approach and Masking

Construction of Regular and Irregular QC-LDPC Codes: a Finite Field Approach and Masking 06 Iteratioal Symposium o Advaces i Electrical, Electroics ad Computer Egieerig (ISAEECE 06 Costructio of egular ad Irregular QC-LDPC Codes: a Fiite Field Approach ad Maskig Xiaopeg Che,a, Li Zhou,,, ui

More information

1. SWITCHING FUNDAMENTALS

1. SWITCHING FUNDAMENTALS . SWITCING FUNDMENTLS Switchig is the provisio of a o-demad coectio betwee two ed poits. Two distict switchig techiques are employed i commuicatio etwors-- circuit switchig ad pacet switchig. Circuit switchig

More information

On the Use of Hard-Decision LDPC Decoders on MLC NAND Flash Memory

On the Use of Hard-Decision LDPC Decoders on MLC NAND Flash Memory O the Use of Hard-Decisio LDPC Decoders o MLC NAND Flash Memory Khoa Le ad Fakhreddie Ghaffari ETIS, UMR-8051, Uiversité Paris Seie, Uiversité de Cergy-Potoise, ENSEA, CNRS, Frace. {khoa.letrug, fakhreddie.ghaffari}@esea.fr

More information

Enhancing Efficiency of Software Fault Tolerance Techniques in Satellite Motion System

Enhancing Efficiency of Software Fault Tolerance Techniques in Satellite Motion System Joural of Iformatio Systems ad Telecommuicatio, Vol. 2, No. 3, July-September 2014 173 Ehacig Efficiecy of Software Fault Tolerace Techiques i Satellite Motio System Hoda Baki Departmet of Electrical ad

More information

A Note on Least-norm Solution of Global WireWarping

A Note on Least-norm Solution of Global WireWarping A Note o Least-orm Solutio of Global WireWarpig Charlie C. L. Wag Departmet of Mechaical ad Automatio Egieerig The Chiese Uiversity of Hog Kog Shati, N.T., Hog Kog E-mail: cwag@mae.cuhk.edu.hk Abstract

More information

Multiprocessors. HPC Prof. Robert van Engelen

Multiprocessors. HPC Prof. Robert van Engelen Multiprocessors Prof. Robert va Egele Overview The PMS model Shared memory multiprocessors Basic shared memory systems SMP, Multicore, ad COMA Distributed memory multicomputers MPP systems Network topologies

More information

Evaluation scheme for Tracking in AMI

Evaluation scheme for Tracking in AMI A M I C o m m u i c a t i o A U G M E N T E D M U L T I - P A R T Y I N T E R A C T I O N http://www.amiproject.org/ Evaluatio scheme for Trackig i AMI S. Schreiber a D. Gatica-Perez b AMI WP4 Trackig:

More information

Sorting in Linear Time. Data Structures and Algorithms Andrei Bulatov

Sorting in Linear Time. Data Structures and Algorithms Andrei Bulatov Sortig i Liear Time Data Structures ad Algorithms Adrei Bulatov Algorithms Sortig i Liear Time 7-2 Compariso Sorts The oly test that all the algorithms we have cosidered so far is compariso The oly iformatio

More information

Properties and Embeddings of Interconnection Networks Based on the Hexcube

Properties and Embeddings of Interconnection Networks Based on the Hexcube JOURNAL OF INFORMATION PROPERTIES SCIENCE AND AND ENGINEERING EMBEDDINGS OF 16, THE 81-95 HEXCUBE (2000) 81 Short Paper Properties ad Embeddigs of Itercoectio Networks Based o the Hexcube JUNG-SING JWO,

More information

The Closest Line to a Data Set in the Plane. David Gurney Southeastern Louisiana University Hammond, Louisiana

The Closest Line to a Data Set in the Plane. David Gurney Southeastern Louisiana University Hammond, Louisiana The Closest Lie to a Data Set i the Plae David Gurey Southeaster Louisiaa Uiversity Hammod, Louisiaa ABSTRACT This paper looks at three differet measures of distace betwee a lie ad a data set i the plae:

More information

APPLICATION NOTE PACE1750AE BUILT-IN FUNCTIONS

APPLICATION NOTE PACE1750AE BUILT-IN FUNCTIONS APPLICATION NOTE PACE175AE BUILT-IN UNCTIONS About This Note This applicatio brief is iteded to explai ad demostrate the use of the special fuctios that are built ito the PACE175AE processor. These powerful

More information

An Efficient Algorithm for Graph Bisection of Triangularizations

An Efficient Algorithm for Graph Bisection of Triangularizations A Efficiet Algorithm for Graph Bisectio of Triagularizatios Gerold Jäger Departmet of Computer Sciece Washigto Uiversity Campus Box 1045 Oe Brookigs Drive St. Louis, Missouri 63130-4899, USA jaegerg@cse.wustl.edu

More information

A General Framework for Accurate Statistical Timing Analysis Considering Correlations

A General Framework for Accurate Statistical Timing Analysis Considering Correlations A Geeral Framework for Accurate Statistical Timig Aalysis Cosiderig Correlatios 7.4 Vishal Khadelwal Departmet of ECE Uiversity of Marylad-College Park vishalk@glue.umd.edu Akur Srivastava Departmet of

More information

Eigenimages. Digital Image Processing: Bernd Girod, 2013 Stanford University -- Eigenimages 1

Eigenimages. Digital Image Processing: Bernd Girod, 2013 Stanford University -- Eigenimages 1 Eigeimages Uitary trasforms Karhue-Loève trasform ad eigeimages Sirovich ad Kirby method Eigefaces for geder recogitio Fisher liear discrimat aalysis Fisherimages ad varyig illumiatio Fisherfaces vs. eigefaces

More information

Homework 1 Solutions MA 522 Fall 2017

Homework 1 Solutions MA 522 Fall 2017 Homework 1 Solutios MA 5 Fall 017 1. Cosider the searchig problem: Iput A sequece of umbers A = [a 1,..., a ] ad a value v. Output A idex i such that v = A[i] or the special value NIL if v does ot appear

More information

Pseudocode ( 1.1) Analysis of Algorithms. Primitive Operations. Pseudocode Details. Running Time ( 1.1) Estimating performance

Pseudocode ( 1.1) Analysis of Algorithms. Primitive Operations. Pseudocode Details. Running Time ( 1.1) Estimating performance Aalysis of Algorithms Iput Algorithm Output A algorithm is a step-by-step procedure for solvig a problem i a fiite amout of time. Pseudocode ( 1.1) High-level descriptio of a algorithm More structured

More information

Low Complexity H.265/HEVC Coding Unit Size Decision for a Videoconferencing System

Low Complexity H.265/HEVC Coding Unit Size Decision for a Videoconferencing System BULGARIAN ACADEMY OF SCIENCES CYBERNETICS AND INFORMATION TECHNOLOGIES Volume 15, No 6 Special Issue o Logistics, Iformatics ad Service Sciece Sofia 2015 Prit ISSN: 1311-9702; Olie ISSN: 1314-4081 DOI:

More information

Chapter 11. Friends, Overloaded Operators, and Arrays in Classes. Copyright 2014 Pearson Addison-Wesley. All rights reserved.

Chapter 11. Friends, Overloaded Operators, and Arrays in Classes. Copyright 2014 Pearson Addison-Wesley. All rights reserved. Chapter 11 Frieds, Overloaded Operators, ad Arrays i Classes Copyright 2014 Pearso Addiso-Wesley. All rights reserved. Overview 11.1 Fried Fuctios 11.2 Overloadig Operators 11.3 Arrays ad Classes 11.4

More information

An Estimation of Distribution Algorithm for solving the Knapsack problem

An Estimation of Distribution Algorithm for solving the Knapsack problem Vol.4,No.5, 214 Published olie: May 25, 214 DOI: 1.7321/jscse.v4.5.1 A Estimatio of Distributio Algorithm for solvig the Kapsack problem 1 Ricardo Pérez, 2 S. Jös, 3 Arturo Herádez, 4 Carlos A. Ochoa *1,

More information

Lecture 6. Lecturer: Ronitt Rubinfeld Scribes: Chen Ziv, Eliav Buchnik, Ophir Arie, Jonathan Gradstein

Lecture 6. Lecturer: Ronitt Rubinfeld Scribes: Chen Ziv, Eliav Buchnik, Ophir Arie, Jonathan Gradstein 068.670 Subliear Time Algorithms November, 0 Lecture 6 Lecturer: Roitt Rubifeld Scribes: Che Ziv, Eliav Buchik, Ophir Arie, Joatha Gradstei Lesso overview. Usig the oracle reductio framework for approximatig

More information

Computing a k-sparse n-length Discrete Fourier Transform using at most 4k samples and O(k log k) complexity

Computing a k-sparse n-length Discrete Fourier Transform using at most 4k samples and O(k log k) complexity 2013 IEEE Iteratioal Symposium o Iformatio Theory Computig a k-sparse -legth Discrete Fourier Trasform usig at most 4k samples ad O(k log k) complexity Sameer Pawar ad Kaa Ramchadra Dept of Electrical

More information

Copyright 2016 Ramez Elmasri and Shamkant B. Navathe

Copyright 2016 Ramez Elmasri and Shamkant B. Navathe Copyright 2016 Ramez Elmasri ad Shamkat B. Navathe CHAPTER 18 Strategies for Query Processig Copyright 2016 Ramez Elmasri ad Shamkat B. Navathe Itroductio DBMS techiques to process a query Scaer idetifies

More information

An Efficient Algorithm for Graph Bisection of Triangularizations

An Efficient Algorithm for Graph Bisection of Triangularizations Applied Mathematical Scieces, Vol. 1, 2007, o. 25, 1203-1215 A Efficiet Algorithm for Graph Bisectio of Triagularizatios Gerold Jäger Departmet of Computer Sciece Washigto Uiversity Campus Box 1045, Oe

More information

Data diverse software fault tolerance techniques

Data diverse software fault tolerance techniques Data diverse software fault tolerace techiques Complemets desig diversity by compesatig for desig diversity s s limitatios Ivolves obtaiig a related set of poits i the program data space, executig the

More information

The Magma Database file formats

The Magma Database file formats The Magma Database file formats Adrew Gaylard, Bret Pikey, ad Mart-Mari Breedt Johaesburg, South Africa 15th May 2006 1 Summary Magma is a ope-source object database created by Chris Muller, of Kasas City,

More information

Stone Images Retrieval Based on Color Histogram

Stone Images Retrieval Based on Color Histogram Stoe Images Retrieval Based o Color Histogram Qiag Zhao, Jie Yag, Jigyi Yag, Hogxig Liu School of Iformatio Egieerig, Wuha Uiversity of Techology Wuha, Chia Abstract Stoe images color features are chose

More information

Algorithm. Counting Sort Analysis of Algorithms

Algorithm. Counting Sort Analysis of Algorithms Algorithm Coutig Sort Aalysis of Algorithms Assumptios: records Coutig sort Each record cotais keys ad data All keys are i the rage of 1 to k Space The usorted list is stored i A, the sorted list will

More information

Bayesian approach to reliability modelling for a probability of failure on demand parameter

Bayesian approach to reliability modelling for a probability of failure on demand parameter Bayesia approach to reliability modellig for a probability of failure o demad parameter BÖRCSÖK J., SCHAEFER S. Departmet of Computer Architecture ad System Programmig Uiversity Kassel, Wilhelmshöher Allee

More information

Xiaozhou (Steve) Li, Atri Rudra, Ram Swaminathan. HP Laboratories HPL Keyword(s): graph coloring; hardness of approximation

Xiaozhou (Steve) Li, Atri Rudra, Ram Swaminathan. HP Laboratories HPL Keyword(s): graph coloring; hardness of approximation Flexible Colorig Xiaozhou (Steve) Li, Atri Rudra, Ram Swamiatha HP Laboratories HPL-2010-177 Keyword(s): graph colorig; hardess of approximatio Abstract: Motivated b y reliability cosideratios i data deduplicatio

More information

EE University of Minnesota. Midterm Exam #1. Prof. Matthew O'Keefe TA: Eric Seppanen. Department of Electrical and Computer Engineering

EE University of Minnesota. Midterm Exam #1. Prof. Matthew O'Keefe TA: Eric Seppanen. Department of Electrical and Computer Engineering EE 4363 1 Uiversity of Miesota Midterm Exam #1 Prof. Matthew O'Keefe TA: Eric Seppae Departmet of Electrical ad Computer Egieerig Uiversity of Miesota Twi Cities Campus EE 4363 Itroductio to Microprocessors

More information

EE123 Digital Signal Processing

EE123 Digital Signal Processing Last Time EE Digital Sigal Processig Lecture 7 Block Covolutio, Overlap ad Add, FFT Discrete Fourier Trasform Properties of the Liear covolutio through circular Today Liear covolutio with Overlap ad add

More information

Eigenimages. Digital Image Processing: Bernd Girod, Stanford University -- Eigenimages 1

Eigenimages. Digital Image Processing: Bernd Girod, Stanford University -- Eigenimages 1 Eigeimages Uitary trasforms Karhue-Loève trasform ad eigeimages Sirovich ad Kirby method Eigefaces for geder recogitio Fisher liear discrimat aalysis Fisherimages ad varyig illumiatio Fisherfaces vs. eigefaces

More information

Math Section 2.2 Polynomial Functions

Math Section 2.2 Polynomial Functions Math 1330 - Sectio. Polyomial Fuctios Our objectives i workig with polyomial fuctios will be, first, to gather iformatio about the graph of the fuctio ad, secod, to use that iformatio to geerate a reasoably

More information

Arithmetic Sequences

Arithmetic Sequences . Arithmetic Sequeces COMMON CORE Learig Stadards HSF-IF.A. HSF-BF.A.1a HSF-BF.A. HSF-LE.A. Essetial Questio How ca you use a arithmetic sequece to describe a patter? A arithmetic sequece is a ordered

More information

Generation of Distributed Arithmetic Designs for Reconfigurable Applications

Generation of Distributed Arithmetic Designs for Reconfigurable Applications Geeratio of Distributed Arithmetic Desigs for Recofigurable Applicatios Christophe Bobda, Ali Ahmadiia, Jürge Teich Uiversity of Erlage-Nuremberg Departmet of computer sciece Am Weichselgarte 3, 91058

More information

New HSL Distance Based Colour Clustering Algorithm

New HSL Distance Based Colour Clustering Algorithm The 4th Midwest Artificial Itelligece ad Cogitive Scieces Coferece (MAICS 03 pp 85-9 New Albay Idiaa USA April 3-4 03 New HSL Distace Based Colour Clusterig Algorithm Vasile Patrascu Departemet of Iformatics

More information

Bezier curves. Figure 2 shows cubic Bezier curves for various control points. In a Bezier curve, only

Bezier curves. Figure 2 shows cubic Bezier curves for various control points. In a Bezier curve, only Edited: Yeh-Liag Hsu (998--; recommeded: Yeh-Liag Hsu (--9; last updated: Yeh-Liag Hsu (9--7. Note: This is the course material for ME55 Geometric modelig ad computer graphics, Yua Ze Uiversity. art of

More information

MOST of the advanced signal processing algorithms are

MOST of the advanced signal processing algorithms are A edited versio of this work was publiched i IEEE TRANS. ON CIRCUITS AND SYSTEMS II, VOL. 6, NO. 9, SEPT 05 DOI:0.09/TCSII.05.35753 High-Throughput FPGA Implemetatio of QR Decompositio Sergio D. Muñoz

More information

Using a Dynamic Interval Type-2 Fuzzy Interpolation Method to Improve Modeless Robots Calibrations

Using a Dynamic Interval Type-2 Fuzzy Interpolation Method to Improve Modeless Robots Calibrations Joural of Cotrol Sciece ad Egieerig 3 (25) 9-7 doi:.7265/2328-223/25.3. D DAVID PUBLISHING Usig a Dyamic Iterval Type-2 Fuzzy Iterpolatio Method to Improve Modeless Robots Calibratios Yig Bai ad Dali Wag

More information

Neural Networks A Model of Boolean Functions

Neural Networks A Model of Boolean Functions Neural Networks A Model of Boolea Fuctios Berd Steibach, Roma Kohut Freiberg Uiversity of Miig ad Techology Istitute of Computer Sciece D-09596 Freiberg, Germay e-mails: steib@iformatik.tu-freiberg.de

More information

THIN LAYER ORIENTED MAGNETOSTATIC CALCULATION MODULE FOR ELMER FEM, BASED ON THE METHOD OF THE MOMENTS. Roman Szewczyk

THIN LAYER ORIENTED MAGNETOSTATIC CALCULATION MODULE FOR ELMER FEM, BASED ON THE METHOD OF THE MOMENTS. Roman Szewczyk THIN LAYER ORIENTED MAGNETOSTATIC CALCULATION MODULE FOR ELMER FEM, BASED ON THE METHOD OF THE MOMENTS Roma Szewczyk Istitute of Metrology ad Biomedical Egieerig, Warsaw Uiversity of Techology E-mail:

More information

Recursive Procedures. How can you model the relationship between consecutive terms of a sequence?

Recursive Procedures. How can you model the relationship between consecutive terms of a sequence? 6. Recursive Procedures I Sectio 6.1, you used fuctio otatio to write a explicit formula to determie the value of ay term i a Sometimes it is easier to calculate oe term i a sequece usig the previous terms.

More information

Toward Realtime Side Information Decoding On Multi-Core Processors

Toward Realtime Side Information Decoding On Multi-Core Processors MITSUBISHI ELECTRIC RESEARCH LABORATORIES http://www.merl.com Toward Realtime Side Iformatio Decodig O Multi-Core Processors Svetislav Momcilovic, Yige Wag, Shatau Rae, Athoy Vetro TR21-1 December 21 Abstract

More information

The isoperimetric problem on the hypercube

The isoperimetric problem on the hypercube The isoperimetric problem o the hypercube Prepared by: Steve Butler November 2, 2005 1 The isoperimetric problem We will cosider the -dimesioal hypercube Q Recall that the hypercube Q is a graph whose

More information

Analysis Metrics. Intro to Algorithm Analysis. Slides. 12. Alg Analysis. 12. Alg Analysis

Analysis Metrics. Intro to Algorithm Analysis. Slides. 12. Alg Analysis. 12. Alg Analysis Itro to Algorithm Aalysis Aalysis Metrics Slides. Table of Cotets. Aalysis Metrics 3. Exact Aalysis Rules 4. Simple Summatio 5. Summatio Formulas 6. Order of Magitude 7. Big-O otatio 8. Big-O Theorems

More information

How do we evaluate algorithms?

How do we evaluate algorithms? F2 Readig referece: chapter 2 + slides Algorithm complexity Big O ad big Ω To calculate ruig time Aalysis of recursive Algorithms Next time: Litterature: slides mostly The first Algorithm desig methods:

More information