Single Cycle Data Path

Transcription

1 Single ycle ata Path S 365 Lecture 6 Prof. Yih Huang S365 1 MIPS Lite We're ready to look at an implementation of the MIPS Simplified to support only: memory-reference instructions: lw, sw arithmetic-logical instructions: add, sub, and, or, slt, nor control flow instructions: beq, j S

2 Generic Implementation: use the program counter (P) to supply instruction address get the instruction from memory read registers use the instruction to decide exactly what to do All instructions use the ALU after reading the registers. Why? memory-reference? arithmetic? control flow? S365 3 State Elements locks used in synchronous logic when should an element that contains state be updated? Falling Edge Raising Edge lock Pulse lock Time S

3 Latches and Flip-flops hange of state (value) is based on the clock Latch: whenever the inputs change, and the clock is asserted Flip-flop: state changes only on a clock edge (edge-triggered methodology) S latch _ S

4 flip-flop latch latch S365 7 Register Similar to the Flip Flop: N-bit input and output Write Enable input Write Enable: negated (0): ata Out will not change asserted (1): ata Out will become ata In ata In N Write Enable lock ata Out N Notice that clock input is inversed. Value changes occur on raising edges S

5 Register File Built using flip-flops Two read ports One write port Write effects seen in the next cycle Read Reg # 1 Read Reg # 2 RegWrite Write Reg # Write ata Register File 32 Read ata 1 32 Read ata 2 S365 9 Implementing Two Read Ports Read register number 1 Register 0 Register 1 Register n 1 Register n M u x Read data 1 Read register number 2 M u x Read data 2 S

6 Writing Register File The clock determines when to write Write Register number 0 1 n-to-1 decoder n 1 n Register 0 Register 1 Register data Register n 1 Register n S Add ALU result M u x 1 Add Regst Shift left 2 PSrc 4 Branch MemRead Instruction [31 26] ontrol MemtoReg ALUOp MemWrite ALUSrc RegWrite P Read address Instruction [31 0] Instruction memory Instruction [25 21] Instruction [20 16] Instruction [15 11] 0 M u x 1 Read register 1 Read data 1 Read register 2 Registers Read Write data 2 register Write data 0 M u x 1 Zero ALU ALU result Address Write data Read data ata memory 1 M u x 0 Single ycle atapath Instruction [15 0] Sign extend Instruction [5 0] ALU control S

7 ontrol Signals ALU Operation (ALUOp3:ALUOp0) 0000 and 0001 or 0010 add 0110 sub 0111 set-on-less-than 1100 nor S ALUsrc: determine the 2 nd operand to ALU 0: from the 2 nd register read port 1: sign-extended immediate Psrc: determines the input to P 0: P+4 1: P+Offset MemRead/MemWrite: enable/disable memory read/write S

8 RegWrite: determined whether a write is performed on the register file. MemToReg: determine the input to register write port 1: memory read port 0: ALU output Regst: determine the register # to be written 0: rt 1: rd S A: rd = rs + rt Instruction Executions ALU Op S R Regst Mem2Reg MemWrite MemRead Psrc RegWrite LW: $rt = Memory[$rs + Offset] ALU Op S R Regst Mem2Reg MemWrite MemRead Psrc RegWrite S

9 Instruction Executions SW: Memory[$rs + Offset] = $rt ALU Op S R Regst Mem2Reg MemWrite MemRead Psrc RegWrite BE: P = P+Offset, if rs==rt ALU Op S R Regst Mem2Reg MemWrite MemRead Psrc RegWrite S Generating ontrol Signals ALUOp0 = ALUOp1 = ALUOp2 = ALUOp3 = S

10 ALUsrc = Psrc = MemRead = MemWrite = RegWrite = Mem2Reg = S iscussions an the datapath support addi? j? jr? S

11 lock ycle Times A clock cycle must accommodate the slowest operation in the data path onsider load word Fetch instruction Read register file ALU Read memory Write register file lock cycle 2 Regelay + ALU-elay + 2 Memelay S Problems elays are NOT born equal. Memory delays far longer than others Things get even worse when complicated operations (e.g., floating point arithmetic) are introduced. onclusion: one should not expect each instruction to use exactly one cycle time. S

12 Solution Allow some instructions to take longer to complete than others. A multi-cycle data path needed More sophisticated control strategy needed. S