Computer Architecture Chapter 5. Fall 2005 Department of Computer Science Kent State University

Transcription

1 Compter Architectre Chapter 5 Fall 25 Department of Compter Science Kent State University

2 The Processor: Datapath & Control Or implementation of the MIPS is simplified memory-reference instrctions: lw, sw arithmetic-logical instrctions: add, sb, and, or, slt control flow instrctions: beq, j Generic implementation se the program conter (PC) to spply the instrction address and fetch the instrction from memory (and pdate the PC) decode the instrction (and read registers) eecte the instrction Eec Fetch PC = PC+4 All instrctions (ecept j) se the ALU after reading the registers Decode How? memory-reference? arithmetic? control flow?

3 Abstract / Simplified View 4 Add Add Data PC Address memory Register # Registers ALU Address Register # Register # Data memory Data Two types of fnctional nits: elements that operate on vales (combinational) elements that contain state (seqential)

4 More Implementation Details

5 Fetching s Fetching instrctions involves reading the instrction from the Memory pdating the PC to hold the address of the net instrction 4 Add Memory PC Address PC is pdated every cycle, so it does not need an eplicit write control signal Memory is read every cycle, so it doesn t need an eplicit read control signal

6 Fetch-Decode-Eecte In order to eecte an instrction we mst Fetch the instrction from memory Determine what the instrction is (decode) Eecte it Fetch and decode are the same for all instrctions Eecte depends on the type of instrction

7 Formats op rs rt rd shamt fnct 3:26 25:2 2:6 5: :6 5: op rs rt immed 3:26 25:2 2:6 5: op addr 3:26 25:

8 Decoding s Decoding instrctions involves sending the fetched instrction s opcode and fnction field bits to the control nit Control Unit Addr Register Addr 2 File Write Addr Write Data Data Data 2 reading two vales from the Register File Register File addresses are contained in the instrction

9 Eecting Load and Store Load Fetch operand (base address) from register Compte effective address from memory Write reslt back to register Store Fetch operands from registers Compte effective address Write to memory

10 Eecting Arithmetic/Logic Arithmetic/logic (add, sb, and, or, slt) Fetch operands from registers Perform operation Write reslt back to register

11 Eecting Branch and Jmp Conditional branch (beq) Fetch operands from registers Compare operands If eqal add displacement to PC Jmp (j) Write new vale to PC

12 ALU s Components Register File ALU Operation Use instrction fields to select registers sorce registers and send them to ALU Send ALU reslt to destination register

13 Components for ALU Instrs Register nmbers Data 5 3 register 5 5 register 2 Registers Write register Write 2 Data ALU control Zero ALU ALU reslt RegWrite a. Registers b. ALU

14 ALU Datapath register register 2 Registers Write register Write RegWrite 2 3 ALU operation Zero ALU ALU reslt

15 Memory Access Components Register File ALU Data Memory Sign-Etension Unit Operation ALU adds base register and sign-etended immediate Send ALU reslt to memory as the address the vale from memory into the destination register (lw) or write the vale from the sorce register into memory (sw)

16 Components for Mem Access MemWrite Address Write Data memory 6 Sign 32 etend Mem a. Data memory nit b. Sign-etension nit

17 Memory Access Datapath register register 2 Registers Write register Write RegWrite 2 3 ALU operation Zero ALU ALU reslt Address Write MemWrite Data memory 6 Sign 32 etend Mem

18 Branches Components Register File ALU Program Conter (PC) Adder Sign-Etension Unit Operation Send sorce register vales to ALU for comparison Adder comptes branch target address Control logic decides whether branch is taken or not

19 Branch Datapath PC + 4 from instrction path Add Sm Branch target Shift left 2 register register 2 Registers Write register Write RegWrite 2 6 Sign 32 etend 3 ALU ALU operation Zero To branch control logic

20 Ptting It All Together PCSrc 4 Add RegWrite Shift left 2 Add ALU reslt M PC address [3 ] memory [25 2] [2 6] M [5 ] RegDst [5 ] register register 2 Write register Write 2 Registers 6 Sign 32 etend ALUSrc M ALU control ALU Zero ALU reslt MemWrite Address Write Data memory Mem MemtoReg M [5 ] ALUOp

21 Control Unit Control nit takes an instrction as inpt and prodces control signals as otpt Types of control signals Mltipleor selector signals Write enables for state elements Control signals for other blocks (ALU, etc.) In a single-cycle path the control nit is simple, jst look p instrction in a table

22 Control Signals RegDst: Selects either rd or rt as the destination register RegWrite: The vale on the write port will be written into the register specified by the write register inpt when asserted ALUOp: Selects ALU operation ALUSrc: Selects the second ALU inpt to be either the second register otpt or the sign-etended immediate vale

23 Control Signals (cont'd) PCSrc: Selects new PC as either PC + 4 or the otpt of the branch target adder This signal is derived from the Branch control signal and the ALU's Zero otpt Mem/MemWrite: Cases memory to perform a read/write operation when asserted MemToReg: Selects either the ALU otpt or the memory otpt as the inpt into the register file

24 ALU Control In order to simplify design of the control nit we give the ALU its own control logic The ALU control block takes a 2-bit inpt from the control nit (ALUOp) and the fnct field from the instrction and prodces the ALU control signals

25 ALU Control Signals ALUOp fnct Field ALU Fnction ALU Inpts lw Add sw Add beq Sbtract add Add sb Sbtract and AND or OR slt Set on less than

26 Operation of Control Unit ALU lw sw beq ALUOp ALUSrc Branch Mem MemWrite MemToReg RegDst RegWrite

27 Datapath with Control Unit 4 Add [3 26] Control RegDst Branch Mem MemtoReg ALUOp MemWrite ALUSrc RegWrite Shift left 2 Add reslt ALU M PCSrc PC address memory [3 ] [25 2] [2 6] [5 ] M register Write register 2 Registers Write 2 register M Zero ALU ALU reslt Address Write Data memory M [5 ] 6 Sign 32 etend ALU control [5 ]

28 Jmp s The nconditional branch instrction (j) comptes its branch target differently from the conditional branch instrction (beq) Branch target address is: Top 4 bits of PC bit immediate vale Two zero bits

29 Datapath with Jmp [25 ] Shift Jmp address [3 ] left Add PC+4 [3 28] [3 26] Control RegDst Jmp Branch Mem MemtoReg ALUOp MemWrite ALUSrc RegWrite Shift left 2 Add reslt ALU M M PC address memory [3 ] [25 2] [2 6] [5 ] M register Write register 2 Registers Write 2 register M Zero ALU ALU reslt Address Write Data memory M [5 ] 6 Sign 32 etend ALU control [5 ]

30 Performance The single-cycle path eectes each instrction in jst one cycle CPI is., which is optimal However, minimm clock cycle time is determined by slowest instrction In practice the eection time can vary considerably between instrctions making a single-cycle implementation a poor choice

31 Using Mltiple Cycles A mlti-cycle path splits instrction eection into mltiple steps, where each step take one cycle If an instrction doesn't need a step it skips it, so different instrctions rn for different nmbers of cycles Slow instrctions don't slow down the entire processor Control nit becomes more complicated Hardware can be shared between steps

32 Mlticycle Datapath () PC Address Memory Data or register Memory register Data Register # Registers Register # Register # A B ALU ALUOt

33 Mlticycle Differences A fnctional nit can be sed more than once in the eection of an instrction, so long as those ses occr in different steps memory and memory are combined into a single nit ALU takes over for the two separate adders Additional registers are needed to save information between steps

34 Mlticycle Registers register (IR): hold the instrction dring its eection Memory register (MDR): hold the read from memory for one cycle A: hold sorce register for one cycle B: hold sorce register for one cycle ALUOt: hold ALU otpt for one cycle

35 Mlticycle Datapath (2) PC M Address Write Memory MemData [25 2] [2 6] [5 ] register [5 ] Memory register M [5 ] M 6 register register 2 Registers Write register Write Sign etend 2 32 Shift left 2 A B 4 M M 2 3 Zero ALU ALU reslt ALUOt

36 Mlticycle Datapath (3) IorD Mem MemWrite IRWrite RegDst RegWrite ALUSrcA PC M Address Write Memory MemData [25 2] [2 6] [5 ] register [5 ] Memory register [5 ] M M 6 register register 2 Registers Write register Write Sign etend 2 32 Shift left 2 A B 4 M M 2 3 ALU control Zero ALU ALU reslt ALUOt [5 ] MemtoReg ALUSrcB ALUOp

37 New Control Signals ALUSrcA: selects first ALU operand to be either the PC or the A register ALUSrcB: selects second ALU operand from: B register, constant 4, sign-etended immediate, sign-etended and shifted immediate MemtoReg: selects register file write as coming from either ALUOt or MDR IorD: selects the memory address as coming from either PC or ALUOt

38 New Control Signals (cont'd) IRWrite: If asserted the memory otpt is written to IR PCSorce: Selects the new vale for the PC from: ALU, ALUOt, jmp target address PCWrite: If asserted the PC is written PCWriteCond: If asserted and the zero otpt from the ALU is then the PC is written

39 Eection Steps fetch decode and register fetch Eection, memory address comptation, or branch completion Memory access or R-type completion Memory read completion

40 Fetch Fetch instrction from memory IR Memory[PC] Increment the PC PC PC + 4

41 Decode Fetch operands from register file A Reg[IR[25:2]] B Reg[IR[2:6]] Compte branch target address ALUOt PC + (sign-etend(ir[5:]) << 2)

42 Eecte Load/store: Compte memory address ALUOt A + sign-etend(ir[5:]) R-type: Perform operation specified by instrction ALUOt A op B Branch: Compare registers and set PC if eqal if (A == B) PC ALUOt Jmp: Set PC to jmp target address PC {PC[3:28], (IR[25:] << 2)}

43 Memory Access Load: memory word into MDR MDR Memory[ALUOt] Store: Write B into memory Memory[ALUOt] B R-type: Write reslt to destination register Reg[IR[5:]] ALUOt

44 Memory Completion Load: Write reslt to destination register Reg[IR[2:6]] MDR

45 Mlticycle Datapath (4) PC M Address Write Memory MemData [25 2] [2 6] [5 ] register [5 ] Memory register PCWriteCond PCWrite IorD Otpts Mem MemWrite MemtoReg IRWrite Control Op [5 ] M [5 ] M PCSorce ALUOp ALUSrcB 6 ALUSrcA RegWrite RegDst [25 ] Shift left 2 [3-26] PC [3-28] register register 2 Registers Write register Write Sign etend 2 32 Shift left 2 A B 4 M M 2 3 ALU control Zero ALU ALU reslt Jmp address [3-] ALUOt 2 M [5 ]

46 State Machine A state machine is a seqential logic device with: Set of states Net-state fnction which determines the net state from the crrent state and the inpts Otpt fnction which determines the otpts from the crrent state and possibly the inpts In a Moore machine the otpt depends only on the state; in a Mealy machine the otpt depends on the state and the inpts

47 Control with a State Machine The control nit for or mlticycle path will be a state machine The only inpt is the op field of the instrction; the otpts are the control signals Each step may have mltiple states if control signals depend on the instrction

48 Fetch and Decode States Start (Op = 'LW') or (Op = 'SW') fetch Mem ALUSrcA = IorD = IRWrite ALUSrcB = ALUOp = PCWrite PCSorce = (Op = R-type) (Op = 'BEQ') decode/ Register fetch ALUSrcA = ALUSrcB = ALUOp = (Op = 'JMP') Memory reference FSM (Figre 5.38) R-type FSM (Figre 5.39) Branch FSM (Figre 5.4) Jmp FSM (Figre 5.4)

49 Load and Store States 2 From state (Op = 'LW') or (Op = 'SW') Memory address comptation ALUSrcA = ALUSrcB = ALUOp = (Op = 'SW') 3 (Op = 'LW') Memory access 5 Memory access Mem IorD = MemWrite IorD = 4 Write-back step RegWrite MemtoReg = RegDst = To state (Figre 5.37)

50 R-Type States From state (Op = R-type) 6 Eection ALUSrcA = ALUSrcB = ALUOp = R-type completion 7 RegDst = RegWrite MemtoReg = To state (Figre 5.37)

51 Branch State From state (Op = 'BEQ') 8 ALUSrcA = ALUSrcB = ALUOp = PCWriteCond PCSorce = Branch completion To state (Figre 5.37)

52 Jmp State From state (Op = 'J') 9 Jmp completion PCWrite PCSorce = To state (Figre 5.37)

53 Complete State Machine 2 Memory address comptation ALUSrcA = ALUSrcB = ALUOp = Start fetch Mem ALUSrcA = IorD = IRWrite ALUSrcB = ALUOp = PCWrite PCSorce = 6 (Op = 'LW') or (Op = 'SW') Eection ALUSrcA = ALUSrcB = ALUOp= 8 (Op = R-type) Branch completion ALUSrcA = ALUSrcB = ALUOp = PCWriteCond PCSorce = decode/ register fetch (Op = 'BEQ') 9 ALUSrcA = ALUSrcB = ALUOp = (Op = 'J') Jmp completion PCWrite PCSorce = 3 (Op = 'LW') Memory access (Op = 'SW') 5 Memory access 7 R-type completion Mem IorD = MemWrite IorD = RegDst = RegWrite MemtoReg = 4 Write-back step RegDst = RegWrite MemtoReg =