CS250 Section 4. 9/21/10 Yunsup Lee. Image Courtesy: Tilera

Transcription

1 CS250 Section 4 9/21/10 Yunsup Lee Image Courtesy: Tilera

2 Any questions on lab 2 & lab 3? Doing okay with gate-level simulations?

3 Announcements I m still working to get physical libraries for lab 3 work probably a day or more RTL simulation is working, in the mean time you can get your circuit to work RISC-V Specification is taking a little bit more time We are still changing the ISA You should get lab 2 done during this week Lab 3 is also a lot of work

4 Lab 2: RISC-V Processor riscvtestharness testrig_tohost imemreq_bits_addr testrig_fromhost riscvproc imemreq_val imemresp_bits_data Instruction Memory clk dmemreq_rw dmemreq_bits_addr clk reset dmemreq_bits_data dmemreq_val dmemresp_bits_data Data Memory clk

5 Lab 3: RISC-V Core riscvcore riscvtestharness riscvproc testrig_fromhost imemreq_bits_addr imemreq_rdy testrig_tohost clk reset Instruction Cache Data Cache imemresp_bits_data dmemreq_rw dmemreq_bits_addr dmemreq_bits_data dmemresp_val dmemresp_bits_data log_control imemreq_val imemresp_val dmemreq_rdy dmemreq_val clk reset ic_mem_req_addr ic_mem_req_rdy mem_resp_data ic_mem_req_val ic_mem_resp_val dc_mem_req_rw dc_mem_req_addr mem_req_data dc_mem_resp_val mem_resp_data dc_mem_req_rdy dc_mem_req_val Arbiter mem_req_rw mem_req_addr mem_req_data dc_mem_resp_val mem_resp_data mem_req_rdy mem_req_val clk reset mem_req_tag mem_resp_tag clk reset_ext clk reset

6 Lab 3: Note on the arbiter

7 Lab 3: Things you need to do Clean up your RISC-V v2 3-stage pipeline with a BTB Now change pipeline structure (add stall signals) to deal with the cache memory interface You can t always put a memory request (when [i d]memreq_rdy is deasserted) Memory response may take some time (when [i d]memresp_val is deasserted) Start with the Instruction cache first Run RISC-V v2 assembly test programs and benchmarks Globally installed programs ~cs250/install/{riscv-tests, riscv-bmarks} Local programs in your lab harness

8 Lab 3: Things you need to do Push your design all the way through the flow Count instruction mix for all assembly tests and benchmarks Measure energy consumption Generate analytic energy model A: instruction mix matrix x: energy/instruction b: energy consumption Ax = b holds. Use MATLAB regression to get a best guess to x Use your energy model and measure the error

9 Area Breakdown

10 ALU If you make your ALU using behavioral Verilog, this is what you get It s always good to start with behavioral Verilog to get things working, but after you get things working, you might optimize your ALU

11 ALU operations Here s the ALU operations you need to support ADD, SUB, SLT, SLTU, SLTI, SLTIU SL, SR, SRA AND, OR, XOR, NOR

12 ALU Operations: ADD/SUB ADDW xc,xa,xb xc = xa + xb SUBW xc,xa,xb xc = xa - xb Simple arithemetic for SUBW xc = xa + (~xb + 1) two inputs: xa and ~xb carry input: 1

13 ALU Operations: SLTU/SLTIU Did you notice the operands of SLTU and SLTIU are flipped? SLTU xc, xa, xb: xc = (xa < xb)? 32 d1 : 32 d0 SLTIU xa, xb, imm: xa = (xb < imm)? 32 d1 : 32 d0 You can t use the same adder, since the inputs are in a different place The natural alignment is imm - xb since we use xa - xb. We can now know whether imm - xb < 0, or imm - xb >= 0 imm < xb, imm >= xb. We re almost there. If we can do imm >= xb+1, we know imm > xb imm - (xb+1) = imm + (~xb) Add with no carry Think about the signed case

14 Suggested Datapath +4 Instruction Mem Reg File Sign Extend Decoder Data Mem ir[24:20] branch pc+4 pc_sel ir[11:0] ir[11:0] rd1 ALU Control Signals wb_sel Reg File rf_wen val rw PC tohost testrig_tohost tohost_en val addr wdata rdata nop killf IR Jump TargGen Branch TargGen Zero Extend ir[19:15] ir[26:0] ir[11:0] PC+4 jalr 0 rd0 Branch CondGen eq? lt? testrig_fromhost ir[24:20] ir[4:0] jump ir[4:0] ir[19:0] wa_sel Fetch Stage Execute Stage ltu? 31

15 ALU Operations: SL/SR/SRA Use one right signed shifter How would you do a shift left with a right shifter? Reverse bits! How would you do logical right shift? Control the MSB of your operand

16 Optimize ALU You can make an ALU with one adder, shifter, and a logic unit Let s form groups of three (First letter of your name s ASCII) % 4