Engineer-to-Engineer Note

Transcription

1 Engineer-to-Engineer Note EE-204 Technicl notes on using Anlog Devices DSPs, processors nd development tools Visit our Web resources nd or e-mil or for technicl support. Blckfin Processor SCCB Softwre Interfce for Configuring I2C Slve Devices Contributed by Thorsten Lorenzen Rev 2 Mrch 13, 2007 Introduction This EE-Note describes the implementtion of the Seril Cmer Control Bus (SCCB) interfce using softwre nd generl-purpose pins on Blckfin processors. Becuse of its rchitecture nd video processing cpbilities, Blckfin processors re well-suited to interfce with video devices. Mny of these video devices in the signl chin must be configured by n I2C comptible hrdwre interfce. For those Blckfin derivtives not equipped with this twowire interfce (TWI), the softwre described in this document cn be used to emulte the function of I2C with the help of two generlpurpose pins. The protocol is complint with the I2C protocol nd supports slve devices only. The Blckfin processor is lwys cting s the mster. No multi-mster bus network cn be ccessed. Bsics The SCCB interfce cn be relized with the use of two generl-purpose pins. In this exmple, PF0 is used to generte the clock line, nd PF1 is used to trnsmit nd receive dt. This functionlity is most common in configuring video devices. The ssocited softwre for this EE-Note includes the protocol stck (I2C_BF5xx_revXX.sm, I2C_BF5xx_revXX.h) nd the C/ASM API (I2C_BF5xx_ASM_C_API.c, I2C_BF5xx_ASM_C_API.h) to cll the protocol within C progrm. One progrmmble timer (timer0) is used to run the two-wire stte mchine. The timer genertes n interrupt fter its counter hs expired. All ctivities of the SCCB interfce re performed during the timer interrupt. The rte of the SCCB clock is determined by the interrupt intervl of the timer. For exmple, the time between these interrupts cn be used to process video dt s it is received. The ssocited softwre contins two projects, ADSP-BF533_I2C_ASM.dpj nd ADSP- BF561_I2C_ASM.dpj, to implement the softwre SCCB protocol for the ASDP-BF533 nd the ADSP-BF561 processors, respectively. I2C Softwre Protocol Common video devices re fitted with n I2Ccomptible interfce tht is dedicted to set up ll the registers in the devices. Becuse n ddressing scheme is used, multiple devices cn be connected on the sme lines. Figure 1 shows n exmple connection. Figure 1. Device connection Copyright , Anlog Devices, Inc. All rights reserved. Anlog Devices ssumes no responsibility for customer product design or the use or ppliction of customers products or for ny infringements of ptents or rights of others which my result from Anlog Devices ssistnce. All trdemrks nd logos re property of their respective holders. Informtion furnished by Anlog Devices pplictions nd development tools engineers is believed to be ccurte nd relible, however no responsibility is ssumed by Anlog Devices regrding technicl ccurcy nd topiclity of the content provided in Anlog Devices Engineer-to-Engineer Notes.

2 In order to generte write to device s register, the dt line must first send the device ddress, followed by the register s word ddress. At this point, the ctul dt cn be trnsferred. Ech bit must be ligned to clock cycle generted by the clock line. As long s the clock is continuous, dt words will be sent to the slve. The ddress will be incremented internlly by the slve. After every 8 th bit trnsferred, n cknowledge bit (9 th bit) is tested by the mster (Blckfin processor). The SCCB interfce will set the dt line high nd reconfigure PF1 s n input. If the slve (video device) does not pull down the dt line, the code will end in n error routine indicting filed ccess. Figure 2 shows write ccess. As cn be seen, the 8th bit of the device ddress indictes tht the following dt will be written in the device. bove. This time, if the mster does not pull down the dt line, the slve will go into power down mode nd keep the dt line high. Finlly, the red sequence will end in no cknowledge bit (9 th bit is driven high by the mster). This is required to grcefully complete the ccess. If the no cknowledge bit is missed, some devices my remin in red mode, regrdless whether stop condition follows. Figure 3. I2C red ccess Figure 4 shows the strt condition, stop condition, nd the dt nd clock lignment. After the strt condition, the dt bit must be vilble before the rising edge of the clock. In ddition, it must not be relesed before the flling edge. Figure 2. I2C write ccess Red ccesses strt in the sme fshion, writing the device ddress nd the register s word ddress to the device. After this is done, n extr strt condition must be inserted, s shown in Figure 4. The device ddress will be written to the device gin, but the 8 th -bit is set to high, indicting tht red ccess follows. If second device ddress is received, s shown in Figure 3, the device strts sending the contents of the loction tht the internl ddress pointer points to. Multiple dt words cn be sent from the slve device to the processor (mster). Similr to the write sequence, sending the device ddress, word ddress nd device ddress gin ends with n cknowledge test, s described Figure 4. I2C strt, stop condition The SCCB softwre interfce meets ll these requirements. More detils bout the I2C timing cn be found in dedicted literture or on the World-Wide Web. Functionl Support As explined in the I2C Softwre Protocol section bove, mny devices function on n 8-bit bsis. However, more nd more devices cn be found tody with either 16-bit ddress cpbility or even 16-bit register width (e.g., Micron, Atmel). This hs been dpted by the protocol. Blckfin Processor SCCB Softwre Interfce for Configuring I2C Slve Devices (EE-204) Pge 2 of 8

3 The list below summrizes the four different ddress nd dt widths supported within the ASM/C API. 8-bit ddress, 8-bit register width support 8-bit ddress, 16-bit register width support 16-bit ddress, 8-bit register width support 16-bit ddress, 16-bit register width support The protocol stck itself is cpble of expnding ddress width or dt width to higher degree, s explined below. Assembly Progrm Use The SCCB interfce is defined nd used in the I2C_BF5xx_revXX.sm / I2C_BF5xx_revXX.h files. Before clling the trnsfer strtup routine (SCCB_Interfce()), some configurtion is required. To understnd the usge of the interfce, the following steps re provided. 1. Open the I2C_BF5xx_revXX.h file to select the register ddresses nd bit settings for dedicted Blckfin derivtive. For exmple, configurtions for the ADSP-BF561 nd ADSP-BF533 processors cn be found, long with explntory comments. Both hrdwre description blocks (for ADSP-BF533 nd ADSP-BF561 processors) re selected utomticlly vi preprocessor definition ( ADSPBF533 or ADSPBF561 ). This must be tken into ccount when mking modifictions to it. 2. Review some vribles defined in I2C_BF5xx_rev_XX.sm to configure the interfce before clling it. Trnsmission or reception is chosen using _SCCB_Control. Setting this vrible to one (1) will trigger red sequence. Setting this vrible to two (2) triggers write sequence. _SCCB_Word_Count holds the number of generl trnsfers to be performed. Device ddresses nd word ddresses re included. This generic form llows expnding ddress nd dt widths, if required. The trnsmission dt (including device nd word ddress) is held in the _SCCB_DtIn[x] rry. The receive dt from red sequence is held in the _SCCB_DtOut[x] rry. _SCCB_In_Progress cn be polled for notifiction of when trnsmission hs completed. Therefore, before clling _SCCB_Interfce(), this vrible must be set to non-zero vlue by the user ppliction. The finl step of the protocol will be to cler this vrible (set it to zero). Missing cknowledges during trnsmission will trigger n error messge. To be notified of errors, _SCCB_Error cn be used. The user ppliction must cler this vrible before clling the SCCB interfce. In the event of n error, _SCCB_Error is set to one nd the trnsfer is borted by execution of the I2C stop condition. 3. After these settings re estblished, the _SCCB_Interfce() subroutine (defined in the I2C_BF5xx_rev_XX.sm file) must be clled to strt the trnsfer. _SCCB_Interfce() stores nd restores ll registers used by the I2C protocol. It strts the timer nd sets up the interrupt nd PF pins on user-defined bsis. User-defined interrupt priority cnnot be selected within the protocol becuse the SIC_IARx registers re not modified. The defult vlues re: - ADSP-BF533: Timer0 = IVG11 - ADSP-BF561. Timer0 = IVG10 If chnge is required, it must be mde by the user ppliction. 4. When the initiliztion process is completed, the core returns to the user ppliction code. A timer interrupt is rised fter certin Blckfin Processor SCCB Softwre Interfce for Configuring I2C Slve Devices (EE-204) Pge 3 of 8

4 time, following its genertion in the initiliztion process. Ech timer interrupt will be tken to drive signl chnge or insert n extr dely. 5. During the SCCB trnsfer, ll used PF pins nd the selected timer must not be used for ny other purposes. The registers nd pointers my be used becuse they will be stored nd restored before nd fter the end of ech interrupt. Avoid strting the SCCB interfce second time before the pending trnsfer hs been completed. For multiple device setups, use conditionl loops or plce code between ech cll tht gurntees the dely required to finish the process. 6. The finl timer interrupt will turn off the timer nd disble ll I2C resources. C Progrm Use (ASM Interfce) In order to mke the protocol functionl in C, C/ASM API ws creted. This section explins how to use the protocol stck in this cse. As discussed in the previous section, open the I2C_BF5xx_revXX.h file nd select the register ddresses nd bit settings for specific Blckfin derivtive. Both hrdwre description blocks (for ADSP-BF533 nd ADSP-BF561 processors) re selected utomticlly vi preprocessor definition ( ADSPBF533 or ADSPBF561 ). This must be tken into ccount when mking modifictions to it. In ddition to the I2C_BF5xx_revXX.sm nd 2C_BF5xx_revXX.h source files, the I2C_BF5xx_ASM_C_API.c nd I2C_BF5xx_ASM_C_API.h files must be dded to the project. The API sources include two types of ccesses: blocking nd non-blocking. A blocking ccess mens tht, for the durtion of n I2C trnsfer, the processor will stll (i.e., it polls SCCB_In_Progress internlly in the subroutine). In contrst, the non-blocking ccess just triggers the trnsmission nd immeditely returns to the ppliction code. The dvntge is tht ppliction code cn be executed in prllel to the I2C trnsfer. However, SCCB_In_Progress must be polled externlly (i.e., in the user ppliction) to detect completion of pending trnsmission. It is left to the user to determine which type of ccess to use. The I2C_NonBlocked_Write() nd I2C_Blocked_Write() functions cn be found in the I2C_BF5xx_ASM_C_API.c file. They re the entry points to the write functions. The Boolen ddr_size_16 nd dt_size_16 elements configure the interfce to either send/receive 16-bit or 8-bit ddresses or dt vlues. TWIBse_Addr will hold the device ddress to identify the trget externl device. The strt_ddress prmeter cn either include 16 or 8 bits nd identifies the register/memory ddress within the identified device. The vlues pointer requires the ddress to n rry where the dt is locted to be sent. Num_Trnsctions indictes the number of trnsfers to be executed. It includes the number of dt trnsfers only! For blocking ccesses, n integer return vlue returns the number of successful trnsfers. For nonblocking ccesses, _SCCB_Error must be polled in order to recognize whether the trnsfer completed grcefully. For non-blocking ccesses, void strting the SCCB interfce second time before the pending trnsction hs completed. For multiple device setups, use conditionl loops (e.g., while(sccb_in_progress)) or plce code between ech cll tht gurntees the dely required to finish the process. Similrly, the I2C_NonBlocked_Red() nd I2C_Blocked_Red() red functions use the sme vribles. For blocking ccesses, the received dt cn be obtined directly from the Blckfin Processor SCCB Softwre Interfce for Configuring I2C Slve Devices (EE-204) Pge 4 of 8

5 vlues vrible. For non-blocking ccesses, the dt cnnot be obtined before the trnsfer hs been completed. Therefore, it is left to the user ppliction to get the vlues. The Listings below show how to use the C interfce in the user ppliction. unsigned int I2C_Blocked_Write(bool ddr_size_16, // Addr width select 8/16 bool dt_size_16, // Dt width select 8/16 unsigned chr TWIBse_Addr, // I2C device ddr unsigned short strt_ddress,// I2C register ddr unsigned short* vlues, // Vlues to send int Num_Trnsctions); // Number of trnsfers Listing 1. I2C blocked write prototype void I2C_NonBlocked_Write (bool ddr_size_16, // Addr width select 8/16 bool dt_size_16, // Dt width select 8/16 unsigned chr TWIBse_Addr, // I2C device ddr unsigned short strt_ddress,// I2C register ddr unsigned short* vlues, // Vlues to send int Num_Trnsctions); // Number of trnsfers Listing 2. I2C non-blocked write prototype unsigned int I2C_Blocked_Red(bool ddr_size_16, // Addr width select 8/16 bool dt_size_16, // Dt width select 8/16 unsigned chr TWIBse_Addr, // I2C device ddr unsigned short strt_ddress,// I2C register ddr unsigned short* vlues, // Vlues to send int Num_Trnsctions); // Number of trnsfers Listing 3. I2C blocked red prototype void I2C_NonBlocked_Red (bool ddr_size_16, // Addr width select 8/16 bool dt_size_16, // Dt width select 8/16 unsigned chr TWIBse_Addr, // I2C device ddr unsigned short strt_ddress,// I2C register ddr int Num_Trnsctions); // Number of trnsfers Listing 4. I2C non-blocked red prototype ErrorIdent = I2C_Blocked_Write(flse, flse, DeviceAddr, RegAddr, &TxArry[i], CN); // Appliction code cn be executed s trnsfer hs been completed Listing 5. I2C blocked write function cll I2C_NonBlocked_Write(flse, flse, DeviceAddr, RegAddr, &TxArry[i], CN); // Appliction code cn be executed while I2C trnsfer is in progress while(sccb_in_progress); // Before kick off subsequent I2C ccess check progress if(sccb_error == 1) while(1); // Check for errors fter trnsfer complete Listing 6. I2C non-blocked write function cll Blckfin Processor SCCB Softwre Interfce for Configuring I2C Slve Devices (EE-204) Pge 5 of 8

6 ErrorIdent = I2C_Blocked_Red(flse, flse, DeviceAddr, RegAddr, &RxArry[i], CN); // Appliction code cn be executed s trnsfer hs been completed Listing 7. I2C blocked red function cll I2C_NonBlocked_Red(flse, flse, DeviceAddr, RegAddr, CN); // Appliction code cn be executed while I2C trnsfer is in progress while(sccb_in_progress); // Before kick off subsequent I2C ccess check progress if(sccb_error == 1) while(1); // Check for errors fter trnsfer complete for (i=0; i<1; i++) RxArry[j++] = SCCB_DtOut[i]; // Get vlues received Listing 8. I2C non-blocked red function cll Performnce The following exmple shows the mesured performnce. The core clock (CCLK) is running t 432 MHz. The peripherl clock (SCLK) is running t 108 MHz. The timer0 is set to run the SCCB t 70 KHz (see Figure 5). Looking t Figure 5 gin, the time between the signl chnges of the dt line nd the clock line cn be used by the core to execute other instructions. Figure 6 zooms in on the write trnsfer displyed in Figure 5 nd shows some dditionl pins. Chnnel 1 shows the timer0 pin (TMR0), chnnel 2 shows PF4, which is progrmmed to toggle outside the timer interrupt. Chnnel 3 represents the SDA line, nd chnnel 4 is the SCL line. As cn be seen, ech positive edge of the timer0 pin (chnnel 1) will trigger n interrupt. The interrupt will cuse the PF4 pin to stop nd to strt toggling. Figure 5. Write ccess timing Figure 5 shows register write. Three bytes re sent (chnnel 1 is SDA, chnnel 2 is SCL). The first 8 bits include the device ddress. In this cse, it is 0xC0. The 9 th bit is held low by the slve (cknowledge). The following 8 bits hold the word ddress, 0x13, within the identified device, followed by the second cknowledge. Finlly, the lst 8 bits crry the register s content, 0x21, followed by the third cknowledge. Figure 6. Performnce test timing Blckfin Processor SCCB Softwre Interfce for Configuring I2C Slve Devices (EE-204) Pge 6 of 8

7 For this test, the core is running in loop outside of interrupt events. The loop executes the following instructions: P0 = 0x02FF(Z); LSETUP(Loop_Strt,performnce_test) LC0=P0; Loop_Strt: p0.h = hi(fio_flag_c); p0.l = lo(fio_flag_c); r0.l = 0x10; w[p0] = r0; p0.l = lo(fio_flag_s); r0.l = 0x10; performnce_test: w[p0] = r0; Listing 9. Performnce test instructions These instructions just toggle the PF4 pin continuously, s shown in Figure 6. PF4 does not toggle when the core is executing SCCB instructions during the timer interrupt. Ech positive edge of the TMR0 pin cuses the timer interrupt. Figure 7 illustrtes the processor lod. At the beginning, PF4 is toggling. The positive edge of TMR0 genertes the timer interrupt, which cuses PF4 to stop toggling. The first interrupt (Figure 6) forces the clock line (SCL) to cler its pin. After the interrupt is completed, PF4 toggles gin until the next positive edge of the TMR0 pin ppers. The next interrupt cused by TMR0 gin forces the dt line to cler. Figure 7 shows the clernce of SCL zooming into Figure 6. The frequency of PF4 (chnnel 2) is not relted to only the core frequency. Ech instruction in the loop (Listing 9) will be executed in one or two cycles, but toggling the ctul pin implies use of the system bus, which runs t 108 MHz. The frequency of PF4 is combintion of the core speed (CCLK) nd the system speed (SCLK). Conclusion If the CCLK is running t 432 MHz, the SCLK is running t 108 MHz, nd the SCCB interfce is running t 70 KHz during the SCCB ction, the entire trnsfer (shown in Figure 5) will tke 404 µs. After the trnsfer completes, the core processes dt t 100% gin. As cn be seen during the trnsfer, 5% of the timer period is used by the SCCB interrupt, leving 95% of the timer period vilble to the core to process dt. Additionlly, the core performnce cn be incresed by slowing down the timer. This results in higher percentge of dt processing performnce, but it extends the SCCB trnsfer time. This exmple ws developed to emulte n I2Ccomptible hrdwre interfce for ADSP-BF53x nd ADSP-BF561 Blckfin processors. Further performnce optimiztions my be relized vi restructuring of the provided code. Figure 7. Performnce test timing Blckfin Processor SCCB Softwre Interfce for Configuring I2C Slve Devices (EE-204) Pge 7 of 8

8 References [1] ADSP-BF561 Blckfin Processor Hrdwre Reference. Revision 1.1, Februry Anlog Devices, Inc. [2] ADSP-BF53 Blckfin Processor Hrdwre Reference. Revision 3.2, July Anlog Devices, Inc. [3] ADSP-BF53x/BF56x Blckfin Processor Progrmming Reference. Revision 1.1, Februry Anlog Devices, Inc. [4] ADSP-BF561 Blckfin Embedded Symmetric Multi-Processor Dt Sheet. Revision A, My Anlog Devices, Inc. [5] ADSP-BF533 Blckfin Embedded Processor Dt Sheet. Revision D, September Anlog Devices, Inc. Document History Revision Rev 2 Mrch 13, 2007 by Thorsten Lorenzen Rev 1 July 30, 2003 by Thorsten Lorenzen Description Initil public relese. Mintined internlly. Blckfin Processor SCCB Softwre Interfce for Configuring I2C Slve Devices (EE-204) Pge 8 of 8