NH-67, TRICHY MAIN ROAD, PULIYUR, C.F , KARUR DT. DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING COURSE MATERIAL

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1 NH-67, TRICHY MAIN ROAD, PULIYUR, C.F , KARUR DT. DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING COURSE MATERIAL Subject Name : Embedded System Class/Sem : BE (ECE) / VII Subject Code : Staff Name : Ms.D.Kavitha & Ms.G. Vijayakumari UNIT III : HARDWARE PLATFORM PIC microcontroller - Architecture of PIC 16c6x/7x FSR - Reset action - Oscillatory connection - Memory organization Instructions - Addressing modes - I/O ports Interrupts Timers ADC - Assembly language programming. Objective: To understand the RISC architecture with an example of PIC microcontroller. To understand the architecture of PIC16C6X/7X family To learn the concepts like File Selection Register, Reset action, oscillatory connection and memory organization. To learn the instructions and Addressing modes. To learn the features like I/O ports and interrupts. To learn the concepts of timers, ADC. To learn the basics of assembly language programming and writing few simple programs. Keywords: Watchdog timer, Harvard architecture, PCLATH, FSR, INDF, MCLR, BROWN- OUT-RESET(BOR), OPTION register, TRISA and TRISB register. Page 1 of 41

2 Overview: PIC Microcontroller: Peripheral Interface Controllers (PIC) is a family of microcontrollers by Microchip Technology. PIC microcontrollers have attractive features and they are suitable for a wide range of applications. The data memory of PIC is 8-bit wide, whereas the PIC program memory is 12-, 14- or 16-bit wide. The instruction holds immediate data, if any, along with the instruction code. Therefore, the PIC program memory size is something like 14-bit wide. Because of this, it is difficult to use an external program memory. PIC is an embedded controller in real sense. PIC executes most of its instructions within 0.2 µs, when operated at its maximum clock rate. Functions supported by PIC devices include analog-to-digital converter (ADC) function. Built-in power-on-reset and Brown-out-reset features. Note: brown-out-reset means that when the power supply drops below a certain voltage (4 V in case of PIC), it causes PIC to reset. Features of PIC: 1.SLEEP MODE: PIC supports a power saving SLEEP mode. The clock may be frozen with all the data preserved in the processor memory. A software command allows entering into this mode. It will be in SLEEP mode till PIC is reset again. 2.WATCHDOG TIMER: PIC has a watchdog timer with on-chip RC oscillator. A watchdog timer prevents the processor from endless loop hanging condition. Watchdog timer is a simple timer circuit, which looks after the continuous functioning of the system with respect to time. Page 2 of 41

3 The processor periodically resets the watchdog timer. This also indicates that the processor functioning is going on. However, if the watchdog timer is not reset before it expires, it is a faulty condition and the watchdog timer now resets the processor. Watch dog timer thus increases the system reliability. 3.INTERRUPT SOURCES: Maximum 12 independent interrupt sources are supported by PIC. The operating range typically for 16C7X is V. Power consumption is very low. ARCHITECTURE OF PIC 16C6X/7X: PIC microcontrollers have Harvard architecture. The program memory and data memory use separate buses. Instruction pipelining allows the instruction to get executed in a single cycle. The execution cycle of one instruction overlaps with the fetch cycle of the next instruction. The PIC architecture consists of an ALU, CPU registers, a program counter, an instruction register, on-chip program memory, on-chip RAM, an 8-level stack, timers, oscillator circuitry, etc. The block diagram is given in the figure 1. Page 3 of 41

4 Arithmetic and Logic Unit: PIC 16CXX are 8-bit microcontrollers. The arithmetic and logic unit (ALU) of these devices is 8-bit wide. It can perform operations on temporary working register (W register) and any register file. One of the operands is normally in W register and the other one is either a file register or an immediate constant. Depending upon the instruction executed, the ALU may affect various flags, namely, Carry (C), Digit Carry (DC), Zero (Z) in STATUS register. Page 4 of 41

5 CPU registers: W or Working Registers (8 bits) STATUS Register (8 bits) FSR (File Selection Register) (8 bits) : Indirect Memory Address Pointer INDF (8 bits) PCLATH (Program Counter Latch) ( 5 bits) PCL (Program Counter Low Byte) (8 bits) W register : W, the working register is bit wide. It contains one of the source operands during the execution on instructions and may serve as the destination for the result of the operation. This has similar function as that of accumulator in other microcontrollers. W register is only used for ALU operations and is not an addressable register. Thus, to load W register with some immediate data 05, the instruction is movlw 05. Similarly, to load any other register, it is required to use this movlw instruction first to load the working register and then transfer the contents of the working register to the respective destination register. Thus, to write to PORT B, the instructions would be: Page 5 of 41

6 Carry bit (C): When two 8-bit operands are added, a 9-bit result can occur, because the result of addition may exceed 256 (FFH). The 9th bit is copied in the Carry bit. During subtraction, if the borrow occurs, the Carry bit is cleared and otherwise it is set. A borrow will not occur if the result of subtraction is greater than or equal to zero. Digits Carry (DC): This bit indicates a carry from the lower 4-bits, during 8-bit addition. If set, it means there is a Carry from the 3rd bit to the 4th bit position. This is useful in binary coded decimal (BCD) addition. In subtraction of BCD numbers, if there is a borrow from 3rd bit to 4th bit position then DC is cleared, otherwise DC is set. Zero (Z): Many arithmetic and logic instructions affect the zero flag. For example, decf instruction can be used to decrement a variable in RAM and if the result is zero, Z bit is set, otherwise cleared. Note: all the instructions do not affect the Z flag. TO and PD : These bits are used along with the SLEEP mode of PIC. During the SLEEP mode, the micro-controller can save a lot of power. After coming out of this mode, the CPU can check these two status bits to determine which kind of event is responsible to bring it out of the SLEEP mode. RP0: This is the register bank select bit. RP is used to calculate the effective address in direct addressing mode. To select register bank 0, this bit is cleared, and if set, it selects bank 1. To set this bit, the PIC instruction bsf STATUS, 5 may be used. Similarly, bcf STATUS, 5 will clear the RP0 bit. Page 6 of 41

7 FSR (FILE SELECTION REGISTER) INDIRECT DATA MEMORY ADDRESS POINTER: FSR is the pointer used for indirect memory addressing in the whole register file. Every instruction that can be used for direct addressing may also be used in a different way for indirect addressing. The only difference in indirect addressing mode is that one has to write the address byte in FSR and then use INDF in the instruction. Thus, FSR points to the desired memory location. INDF (INDirect through FSR): INDF stands for indirect through FSR. This is not a physical register. Addressing INDF register will cause indirect addressing. Thus, the meaning of INDF can be thought as (FSR) or indirect through FSR, where the brackets indicate indirect addressing. Any instruction using INDF register actually accesses the register pointed by the FSR. For example, to clear the RAM location 20H, the program would be as follows: movlw x2h movwf FSR clrf INDF ; Initialize pointer to RAM ; ; Clear INDF register In an instruction indirectly addressing the register the register file, the lower 7 bits of the instruction are zeros, indicating the use of FSR as a pointer. Now, 7 bits from FSR and an 8th bit coming from the STATUS register bit RP0, forms the 8-bit indirect address. This 8-bit address has to be written in FSR using direct addressing prior to its use for indirect addressing. Further, it must be done independent of the STATUS register bit RP0. Several registers including INDF, namely STATUS, PCL, FSR, PCLATH, INTCON are addressable from either bank 0 or bank 1. All these registers have their addresses reachable within 7 bits of address independent of bit RP0. PCLATH ( Program Counter Latch ) Page 7 of 41

8 PCLATH can be independently read or written like any other registers. PCLATH is different from the program counter and is a separate entity. Use of PCLATH is shown in figure 3. PCL: PCL is the lower byte of the program counter. The PIC program counter is 13-bit wide as shown in the figure 4. A write to PCL causes PCLATH contents to be transferred to program counter higher bit locations, automatically. The program counter of 16C6X is associated with an 8-level stack. The operation of stack is similar to any other microcontroller. The program counter always points to the next instruction to be executed. In case of call to subroutines, the returned address is pushed onto the stack and after the return from called subroutines, this return address is retrieved. If there are nested calls, then many such addresses including return addressed from interrupt service subroutines. Page 8 of 41

9 PIN DIAGRAM: PIC 1C7X parts are almost same as 16C6X parts, except with an additional feature of an analogto-digital converter ADC) in PIC 16C7X. The pin diagrams of 16C61 and 1C71 are sown in the figure 5. Figure 5: PIN diagram of 16C61 and 16C71 The pin functional description is shown in the figure 6. Page 9 of 41

10 PIC RESET ACTIONS: PIC reset action takes place due to different mechanisms. Those are Power-on-Reset (POR). MCLR reset during the normal operation, Master Clear MCLR reset during SLEEP mode. Watchdog timer reset during normal operation, Brown-out-Reset (BOR). Brown- out-reset is not available in PIC 16C61/62/64/65. Power-On-Reset (POR): PIC reset function is very simple. MCLR is the master clear pin, which when made low causes PIC to reset. A Power-On-Reset pulse is generated when VDD rise is detected. The range of VDD through which it should rise is from 1.5 to 2.1 V. A very simple reset circuit can be a pull-up resistor through which the MCLR is tied to VDD. A power-up timer operating on the internal RC oscillator generates 72ms fixed delay on power-up. This time delay allows VDD to rise to the required level. Power-up timer may be enabled or disabled by writing a configuration bit. In case of XT, LP and HS oscillator modes, immediately after the power-up delay, the oscillator start-up timer starts. The oscillator start up timer provides 1024 cycles delay. This oscillator start-up timer is to make sure that the oscillator has started and stabilized properly. The PIC reset circuit is shown in the figure 7. Page 10 of 41

11 The reset function will set the program counter to the starting address of the program. This starting address for PIC 16C71 is 00H, whereas for PIC 16C57, it is 7FFH. The first instruction to be executed will appear at the reset vector. When powered, most of the hardware registers are initialized, however, the RAM locations are not initialized. A reset cycle will initialize the RAM locations and some more bits. Therefore, reset and power-on are different operations in PIC. Normally, an RC circuit is not necessarily needed, but it is recommended by Microcip to have a reset circuit using external RC components as sown in the figure 8. Figure 8 : PIC Reset Circuit This circuit is required only if VDD power-up slope is not sufficient. Page 11 of 41

12 The value of R must than 40 KΩ to make sure tat te voltage drop across R does not exceed the electrical specifications. 1K resistor again limits the current into the MCLR pin. BROWN-OUT-RESET(BOR): 16C61 and 16C71 does not support this feature. However, there are many PIC devices like 16C66 and 16C74, where the brown-out-reset is possible. PIC can be reset automatically in running condition due to the brown-out, which is not possible in many other microcontrollers, Brown-out-reset takes place when the supply voltage falls below 4 V. The device remains in the brown-out-reset condition till the power supply voltage is restored. However, there will be a power-up timer killing 72ms more again. It is recommended that the power-up timer should be enabled when the brown-out-reset is enabled. In case, during the power-up timer delay of 72ms, if the supply voltage falls below 4.0V, the CPU will have brown-out-reset once again. PIC OSCILLATOR CONNECTIONS PIC can have four different methods of clock, namely, external RC, internal RC, crystal and external clock. A simple RC oscillator using only internal/external RC components is the simplest way of oscillator connections. This is shown in the figure 9. Page 12 of 41

13 The values of resistor and capacitor in case of external RC components are specified in the data sheets for a given oscillator frequency. Note that the OSC2 pin outputs one-fourth OSC1 frequency, this may help in syncronising the peripherals with PIC microcontroller. RC circuit is used only in applications where the clock requirements are not very precise. There are other methods of clocking PIC microcontrollers. The figure 10 shows the various clocking methods supported by PIC microcontrollers. Figure 11 shows the crystal connections with a PIC microcontroller C1 and C2 are the capacitors to be connected externally along with the crystal. Page 13 of 41

14 Instead of a crystal, one may prefer a cermic resonator as a cheaper alternative, wherein external capacitors are not required. However, a crystal as better accuracy and for timing generation and real time applications, one should prefer crystals. PIC MEMORY ORGANISATION: Program Memory: PIC 16C6X/7X program memory is 2K or 4K. to address 2K program memory, 11-bit address is sufficient. The figure 12 shows how a 2K program memory is accessed along with the program counter. For 4K program memory, 12-bit address is needed. The PIC 16C6X/7X parts have 13-bit program counter. In case of 2K program memory, the upper 2 bits are ignored; similarly, in case of 4K program memory, the uppermost bit of the program counter is ignored. 13-bit program counter allows to access total 8K-program memory. After RESET the program counter is cleared. At location 000H in the program memory, is a goto Mainline instruction. There is one more special address 004H, which automatically loaded into the program counter when an interrupt occurs. At 004H, a goto interrupt service subroutine can be written. Page 14 of 41

15 The interrupt service subroutine may be somewhere else in the program memory space. The locations 005H to 03FFH are for tables, Main program and interrupt service routines. This is shown in the figure 12. DATA MEMORY: REGISTER FILE STRUCTURE: Register is a term for memory locations that are addressed by an instruction. There is a general purpose register file and a special purpose register file. The general purpose register file is analogous to the processor s on-chip RAM. These are 8-bit RAM locations. The special purpose register file consists of input/output ports and control registers. The figure 13 shows the register file structure of 16C6X and 16C7X. The addresses in register file are from 00 through FFH. This requires 8-bit address. The instructions that use direct addressing mode in PIC to address these register files use 7 bits of instruction only. Therefore, the register bank select (RP0) bit in the STATUS register is used to select one of the register banks. Page 15 of 41

16 With this 8-bit direct address, total 256 locations are possible. The lower bytes of the register bank are identified as special function registers (SFRs). These registers have special functions, as shown in the figure 14. The CPU and peripheral modules use SFRs for controlling the operation of the device. NOTE: Only PORTA and PORTB are applicable for 16C61/71; therefore, location 07H that is for PORTC in some other PIC parts is not entered in the table. But, it is available for generalpurpose use. Page 16 of 41

17 OPTION Register: The option register is shown in the figure 15. Various bits in OPTION register are explained in the figure 16. Option register bits are required and must be set or cleared in various applications. Bit RPBU allows enabling the internal pull-ups for PORTB. Next, bit INTEDG is used to decide the falling edge or rising edge sensitivity for the external interrupt INT. Bits RTS and RTE decide the RTCC signal source and RTCC edge, respectively. Prescalar assignments may be applied to RTCC or watchdog timer using PSA bit. Prescalar values can be decided as per figure 16. Page 17 of 41

18 INTCON register: It is the interrupt control register. There are interrupt enabling bits INTE, TOIE, RBIE and ADIE; which corresponds to the external interrupt, timer interrupt, PORTB change interrupt and analog-to-digital conversion interrupt, respectively. The global enable bit GIE allows to either enable (if set) or disable (if cleared) all the interrupts. The associated interrupt flags with external interrupt (INTF), timer interrupt flag (TOIF), PORTB change interrupt flag (RBIF) are set when the corresponding interrupt occurs. INTCON register is explained in the figure 17 and figure 18. The analog-to-digital converter interrupt flag is not in INTCON, but it is located in ADCONO register. Page 18 of 41

19 INSTRUCTIONS: In PIC microcontrollers, the operations are with W register and any of the RAM file registers. For example, to load the working register and then add with the file register one may write the following instruction. Movlw B Addwf H 12,W Note that the instruction has two operands. The first one is the source operand (H 12) and the W register is the destination. Thus, the result of addition will be in W. As per microchip Technology guidelines, mnemonics are written in lowercase letters, RAM variables and special register names are written in lowercase letters. The subroutine names and labels are written in upper as well as lower case letters. Bitwise operations setting or clearing a bit: Instruction bcf f, b can clear the bit b of register f, where f stands for a file register and b can be any number in the range 0 to 7. For example, to clear the bit 0 of PORTB, the instruction will be written as bcf PORTB,0; Clear PORTB bit0 Similarly, to set any bit, one can use instruction bsf f,b. Again note that PORTB is a special register and it is written in uppercase letter. bsf PORTB,0; set PORTB bit0 To set the carry bit in STATUS register, the instruction is bsf STATUS, C; set carry bit Note that bsf as well as bcf instructions execute in a single cycle and no status its(flags) are affected. Increment, Decrement operations: PIC instructions incf and decf allow to increment or decrement a special-purpose register and store the result in either F or W. For incrementing the PORTA register, one may use the instruction. F stands for the destination to be the source register itself. In other cases, W can also be a destination. Incf PORTA, F; increment PORTA by 1 Page 19 of 41

20 Increment and decrement instructions are single-cycle instructions and affect only Z flag in STATUS register. A simply delay routine can be implemented very easily as shown in the program given below. The main program calls the delay subroutine. The register 12H has been used as a counter and it is initialized to F0H. this count is decremented by 1 and tested for 0. If count becomes 0, then the next instruction goto loop will be executed. This will allow the count to decrement further. The Delay.hex file generated using MPLAB is also given at the bottom. Input and outputs: There are I/O control registers namely, TRISA/TRISB/TRISC that are loaded with the contents of the working register W using movlw and movwf instructions. If a 1 is written in the I/O control register, the respective pin is configured as input(high-impedance mode). PORTA is 6-bit wide for most of the PIC 16C6X devices, except in 16C61 it is 5-bit wide. PORTB is 8-bit wide. Page 20 of 41

21 After RESET, these I/O control registers are set to 1 and the default state of the I/O pins is input. These I/O registers can only be written. Example program: Now let us configure PORTB as output port and output some data byte. TRISB is the data direction register corresponding to PORTB. TRISCB resides in bank 1, whereas PORTB is in bank 0. Therefore bank selection is required. If a bit in TRISB is cleared, it puts the contents of the output latch on the corresponding pin. To write TRISB, bank 1 is selected. All 0 are written into TRISB to make all the PORTB pins as outputs. PORTB register has to be written now. For this purpose, bank 0 is selected using bcf instruction. The byte to be sent to PORTB pins is then loaded into the W register and transferred to PORTB register. This program is given in the figure below. Page 21 of 41

22 The instructions are given in the figure 19. ADDRESSING MODES: Direct addressing: Direct addressing mode uses 7 bits of the instruction and the 8th bit from RP0 bit. If RP0 bit is 0, then accessed location is from bank 0, otherwise the location from bank 1 is accessed. Direct addressing is shown in the figure 20. The lower 7 bits of instruction code along with RP0 bit forms the 8-bit address. Indirect addressing: In indirect addressing, the 8-bit address of the location in register file to be accessed is written in File Selection Register (FSR) and the instruction that uses 00H as the direct address, which is INDF, results into indirect addressing. The figure 21 shows the indirect addressing mode. Page 22 of 41

23 Figure 20: Direct Addressing Mode Figure 21: Indirect addressing mode Page 23 of 41

24 In fact, the location pointed by FSR is actually accessed. For making the access indirect addressing independent of bank selection procedure, the FSR is loaded with 8-bit address directly. I/O PORTS: PIC 16C61 and 16C71 has 13 I/O lines. PORTA pins are RA0, RA1, RA2, RA3 and RA4, whereas PORTB is an 8-bit port with corresponding I/O lines RB0 to RB7. PORTA (address 05H) is thus 5-bit wide in case of 16C61. In case of other 16CXX devices like 16C62, 66, 67 etc., PORTA has 6 I/O lines. Pin RA4/TOCK1 of PORTA is a Schmitt trigger input and open drain output. Other PORTA pins RA0 through RAA3 have TTL input levels and CMOS output drivers. TRISA (address 85H) is the SFR used to configure the corresponding pin as an input, and clearing TRISA bit will put the contents of the output latch on the corresponding pin. If an attempt is made to read PORTA, it will read pin status, whereas any write operation will write to the port latch. Thus, all write operations are read-modify-write operations. That is, the port pin is read, it is then modified and written again. To configure PORTA, it is necessary to select proper register bank. The below program shows how to initialize PORTA. Page 24 of 41

25 PORTB of PIC 16C61/71 is b-bit wide and can be configured in the similar manner as seen above for PORTA. The only difference is that now TRISCB is the data direction register for PORTB. The below program shows how to initialize PORTB. All PORTB pins have weak internal pull-ups. To turn on internal pull-ups, it is necessary to clear bit RPBU in OPTION (SFR) register. When the PORTB is configured as an output, the internal pull-ups are turned off automatically. Power-On-Reset also disables the internal pull-ups. A distinguished feature of PORTB pins RB7 to RB4 is that there is an interrupt on change. This is only possible is these pins RB4 to RB7 are configured as inputs. Any pin out of these four pins configures as an output will not support this feature of interrupt on change. The operation of interrupt on change function compares the current pin status with the last one, and if there is any mismatch, the RB port change interrupt is generated setting the flag bit RBIF (INTCON0). This interrupt can wake the device from SLEEP. Mismatching condition will continue to set bit RBIF. Reading PORTB will end the mismatching condition and then user can clear RBIF bit. This feature may be useful in keyboard interfacing. Page 25 of 41

26 INTERRUPTS IN PIC 16C61/71: PIC16C61 supports 3 interrupts, namely, an external interrupt INT at pin RB0, timer 0 interrupt, and PORTB change interrupt. PIC16C61 has one more interrupt associated with the ADC operation. Two different bits from INTCON are required for any interrupt operation, one for enabling the interrupt and one for its detection of occurrence. Apart from these two bits there is a common bit in INTCON called GIE to enable or disable all interrupts simultaneously. For any one of these interrupts to be detected, the GIE bit must be set in INTCON along with the corresponding interrupts enable bit. The GIE bit can be set or cleared by the programmer. However, GIE is cleared by hardware when an interrupt occurs, which will also prevent the CPU from interrupts coming further till the time the interrupt service routine is being executed. Once the instruction retfie (return from interrupt service routine) at the end of interrupt service routine is executed, GIE bit is set automatically. After RESET, GIE bit is cleared and all interrupts are disabled. Therefore, the programmer has to initialize the INTCON register before using any interrupt. The interrupt logic in PIC 16C61 is shown in the figure 22. Figure 22: Interrupt logic in PIC 16C61 Page 26 of 41

27 EXTERNAL INTERRUPT: INT is the interrupt due to external source. A transition at pin RB0/INT causes this interrupt. This is an edge-sensitive interrupt. Note that pin RB0 is also belonging to PORTB, hence it must be initialized before using INT interrupt function. There is a bit in OPTION register (bit INTEDG) to configure this interrupt as either rising edge-triggered or a falling edge-triggered. When a valid interrupt signal appears at INT pin, INTF bit is set in INTCON. INTF bit then must be reset in interrupt service routine. Further, this interrupt can wake the processor from SLEEP mode. This will happen if it is enabled before going into the SLEEP mode, that means the bit INTE must be set before entering the SLEEP MODE. Consider the example shown in the figure 23. Page 27 of 41

28 Here the external interrupt is initialized. Further, in this example, whenever an interrupt occurs, PORTB pins RB1 to RB7 alter their status. It is necessary to initialize the bits in INTCON. Further, OPTION register bit INTEDG is cleared to make the external interrupt sensitive to a falling edge. When an interrupt occurs, GIE bit is cleared to avoid any further interrupts, the return address is pushed onto the stack and the program counter is located with H 004. Normally at location 04 in the program memory, a goto instruction is written which then directs the program control to the interrupt service subroutine (ISR). The interrupt service subroutine just complements the PORTB output pins RB1 to RB7. The intf flag that was set because of the occurrence of INT interrupt is cleared before the return from interrupt instruction retfie. In addition to the return function, the instruction retfie also sets bit GIE in INTCON. Timer 0 Interrupt: Timer 0 overflow interrupt is generated when counter/timer 0 overflows from 0FFH to 00H. This will set the TOIF flag in INTCON. For this purpose, TOIE bit in INTCON must be set along with GIE bit. This interrupt has importance in the sense that many real problems can be solved using timer interrupt. The program handling the timer interrupt can be written easily in the similar manner as that of external interrupt. The only difference will be in the INTCON bits to be used, namely, TOIF and TOIE. PORTB Change Interrupt: A change from high to low or low to high on PORTB pins RB4 to RB7 causes this interrupt. It is possible to have PORTB change interrupt, if pins RB4 to RB7 are configured as inputs. Page 28 of 41

29 Interrupt on change function compares the current pin status with the last one, and if there is any mismatch, the PORTB change interrupt is generated setting the flag bit RBIF (INTCON0). For this purpose, again the bits RBIE and GIE in INTCON must be set to enable this interrupt. This interrupt can wake the device from SLEEP mode. The mismatch outputs are OD ed together to generate a single output RB port change output, which causes this interrupt. ADC Interrupt: This interrupt is generated when the analog-to-digital conversion ends. This is only applicable to 16C71 or 16C7X parts in general. ADIE is the bit that enables this interrupt in INTCON register. Apart from this, the master control bit GIE must be enabled. The end of the conversion interrupt flag (ADIF) bit is in ADCON0 register. PIC 1C61/71 TIMERS: There are three timers in PIC 6C6X, 16C1 has only one timer 0. In addition to Timer0, the operation of watchdog timer is also given. Timer0: Timer 0 is a simple counter, 8-bit wide. The clocking source for timer 0 can either be the internal system clock (Fosc/4) or an external clock. External clock to timer 0 can be given at pin RA4/TOCKI as sown in the figure 24. Timer 0 overflow from 0FFH to 00H sets a flag TOIF in INTCON. Page 29 of 41

30 Further, is causes an interrupt if the timer 0 interrupt is enabled, i.e. is TOIE bit along wit GIE bit in INTCON are set. Figure 9.21 explains the interrupt generation because of timer overflow. A 2-cycle delay synchronizes the external clock at TOCKI (in case it is used) to the internal clock. The mechanism of this delay synchronism is that when an attempt is made to write timer, it resets the delay circuit, which also takes 2 cycles. Therefore, these 2 cycles are not counted. Figure 25 explains the interrupt generation because of timer 0 overflow. For example, if count loaded in timer 0 register is 256, it will cause overflow within 8 cycles and not within 6 cycles as expected. In case of external clock at RA4/TOCKI pin, timer 0 module can be configured to increment on either rising or falling edge. Timer 0 has programmable prescalar options. Page 30 of 41

31 Bit PSA in OPTION register decides the assignment of prescaling to either the watchdog timer or to timer 0. Bits PS2, PS1, PS determines the prescalar value. Programmable prescaling of timer 0 allows handling longer interval events, with the help of only 8-bit maximum value of timer count. Further, the external clock frequency can be higher than the device frequency. A maximum frequency that can be used as a clocking source for timer 0 is limited to 50 MHz maximum. The clocking source frequency, either the internal (Fosc/4) or the external clocking frequency at TOCKI, is divided by 2 in spite of the use of prescaling or not. For example, after 1 ms from the starting time and initial value 00H, the count in timer will be 125, with the internal clock at 1 MHz oscillator frequency. In this case, the timer 0 count does not exceed 256. However, the use of prescaling is needed if the timer 0 count exceeds 256 at given oscillator frequency. The formula to calculate the delay can be written as below, when the use of prescaling is made. Timer 0_Delay = [Timer 0_count] * Prescalar value * {4/Fosc]} As is needed in many cases, the timer overflow is detected or an interrupt bit TOIF is observed to make sure that the appropriate delay is generated after starting the timer. Using the initial timer count (equal to the overflow value) minus the actual count does this. Thus, timer 0 preload count is given by the following equation. Timer 0_Preload Count 256 [Timer 0_Delay * Fosc ]/[Prescalar value * 4] In the example of generating 1.6 s delay, the timer preload count will be If this is rounded of to the nearest integer, it becomes 1 (or 64H). Note: Rounding error can be taken care of to a certain extent in the program that uses timer 0 dely. One way to do so is to put some nop instructions and adjust the preload count accordingly. Page 31 of 41

32 Watchdog Timer (WDT): Watchdog timer is used to prevent the processor from endless loop. The watchdog timer will reset PIC microcontroller if the instruction CLRWDT is not executed periodically. The CLRDWT instruction sets the timeout bit ( TO ) in the status register. This ( TO ) bit is also set during the power-up procedure. The WDT timer can reset this ( TO ) bit. This possibly happens, when the CLRDWT instruction is not executed periodically. The normal timeout period of PIC watchdog timer is around 18 ms. The operation of WDT is shown in the figure 26. The internal RC oscillator drives the watchdog timer. The watchdog timer cannot be turned off. Similarly, if disabled at the time of device programming, the watchdog timer cannot be turned on by any means. There is a programmable prescaling possible again with the elp of the OPTION register bits PSA, PS0, PS1, PS2. The maximum timeout period for te watchdog will be corresponding to PS2, PS1, PS0 set to 1,1,1, respectively, in OPTION register, with PSA = 1. This results into a timeout period of 128*18 ms s. The operation of WDT also affects the PIC power-down mode. Page 32 of 41

33 The execution of the SLEEP command leads to entering the power-down mode. This also clears the WDT is enabled, but keeps it in running condition. Upon power-on-reset or execution of CLRDWT instruction, the power-down flag ( PD ) in STTUS register is set. The processor then continues to execute the instruction following the SLEEP command. Note: Only the SLEEP command can clear the PD bit in STATUS register. Thus, PD and TO bits give the information about the cause of the system wake up. PIC16C71 ANALOG-TO-DIGITAL CONVERTER (ADC): Analog inputs re supported by PIC 16C71 device or by 16C7X in general. PIC 16C71 as four analog channels of 8-bit ADC, with 20 µs of conversion time per channel. Four analog channels AIN, AIN1, AIN2, AAIN3 are the alternate functions of PORTA pins RA0, RA1, RA2, RA3, respectively. AD port configuration control bits PCFG1 AND PCFG0 in ADON1 decide the functions of pins RA0-RA3. This allows configuring pins RA0-RA3 as analog or digital inputs. Further, the reference voltage for ADC may be either the supply voltage or pin AR3 may also be used for this purpose. External reference voltage may be connected to pin RA3. In case some or all of the pins RA0-RA3 are not used for ADC purpose, those may be used as general-purpose I/Os. Clearing bit ADON in ADCON0, one may shut off the AD module, which also saves the power. Clock source for ADC may be selected from ADCON0 register; bits ADSC1 nd ADSC decide the clock source. Figure 27 shows the AD status register. Bits CHS0 and CHS1 allow selecting the analog channels. GO/!DONE bit in ADCON must be set to start the AD conversion. After AD conversion bit GO/!DONE is clered automatically by te hardware to indicate the completion of conversion. Page 33 of 41

34 8-bit ADC result is stored in register ADRES. INTCON (0BH), ADCON0 (08H) and ADCON1 (88H), TRISA (85) and ADRES (09H) are the SFRs associated with ADC operation. For enabling the ADC interrupt, bit IDIE must be set along with GIE bit in INTCON. ADCON0 is explained by figure 27, 28, 29 and 30. ADCON1 is the ADC control register and it configures the functions of pins RA0-RA3. Figure 31 shows the ADCON1 and figure 32 shows the use of ADCON1. Page 34 of 41

35 Example of ADC configuration: Let us now configure the 16C71 ADC with external reference of 3 V and input channels. It is not always a need to use all the ADC channels. In this case, the remaining pins of PORTA may be used as digital I/Os. For programming this configuration, it is necessary to initialize ADCON1, TRISA. This is shown in the figure 33. Thus, from figure 32, ADCON1 bits PCFG1 aand PCFG0 will be and 1, respectively. Therefore, the control word for DCON1 will be B This allows the external voltage reference for ADC to be connected to pin RA3 and other AIN0 to AIN2 as the analog inputs. Even though these are analog inputs to ADC, it is possible to use any pin out of AIN0 to AIN2 as digital input if read. Figure 33 shows AIN0 and AIN1 as two analog inputs and a digital input is connected to pin RA2. TRISA is the control register for port A. The bits in ADCON0 are selected as B Page 35 of 41

36 This will select RC oscillator and turn on power to ADC. GO/!DONE bit is now set to 1 to start the AD conversion. The channel AIN2 will be selected because CHS1 and CHS0 bits are 1 and 0, respectively. ASSEMBLY LANGUAGE PROGRAMMING: The instruction of PIC 16C6X are listed below. Page 36 of 41

37 1. Write a assembly language program for creating a delay. 2. Write a assembly language program to configure PORTB as output port and to output some data byte. Page 37 of 41

38 3.Write a program to initialize PORTA. 4. Write a program to initialize PORTB. Page 38 of 41

39 5. Write a program for Analog-to-digital conversion: SUMMARY: Peripheral Interface Controllers (PIC) is a family of microcontrollers by Microchip Technology. PIC microcontrollers have attractive features and they are suitable for a wide range of applications. The data memory of PIC is 8-bit wide, whereas the PIC program memory is 12-, 14- or 16-bit wide. PIC executes most of its instructions within 0.2 µs, when operated at its maximum clock rate. The PIC has the following features: Sleep mode Watchdog timer Interrupt sources PIC microcontrollers have Harvard architecture. The program memory and data memory use separate buses. Instruction pipelining allows the instruction to get executed in a single cycle. Page 39 of 41

40 The execution cycle of one instruction overlaps with the fetch cycle of the next instruction. The PIC architecture consists of an ALU, CPU registers, a program counter, an instruction register, on-chip program memory, on-chip RAM, an 8-level stack, timers, oscillator circuitry, etc. FSR is the pointer used for indirect memory addressing in the whole register file. Every instruction that can be used for direct addressing may also be used in a different way for indirect addressing. The only difference in indirect addressing mode is that one has to write the address byte in FSR and then use INDF in the instruction. PIC can have four different methods of clock, namely, external RC, internal RC, crystal and external clock. A simple RC oscillator using only internal/external RC components is the simplest way of oscillator connections. PIC 16C6X/7X program memory is 2K or 4K. to address 2K program memory, 11-bit address is sufficient. For 4K program memory, 12-bit address is needed. The PIC 16C6X/7X parts have 13-bit program counter. PIC can have four different methods of clock, namely, external RC, internal RC, crystal and external clock. A simple RC oscillator using only internal/external RC components is the simplest way of oscillator connections. PIC can be reset automatically in running condition due to the brown-out, which is not possible in many other microcontrollers, Brown-out-reset takes place when the supply voltage falls below 4 V. The addressing mode is of two types. Direct addressing mode and Indirect addressing mode. PIC 16C61 and 16C71 has 13 I/O lines. PORTA pins are RA0, RA1, RA2, RA3 and RA4, whereas PORTB is an 8-bit port with corresponding I/O lines RB0 to RB7. PORTA (address 05H) is thus 5-bit wide in case of 16C61. Page 40 of 41

41 TRISA (address 85H) is the SFR used to configure the corresponding pin as an input, and clearing TRISA bit will put the contents of the output latch on the corresponding pin. PIC16C61 supports 3 interrupts, namely, an external interrupt INT at pin RB0, timer 0 interrupt, and PORTB change interrupt. INT is the interrupt due to external source. A transition at pin RB0/INT causes this interrupt. Watchdog timer is used to prevent the processor from endless loop. The watchdog timer will reset PIC microcontroller if the instruction CLRWDT is not executed periodically. Analog inputs re supported by PIC 16C71 device or by 16C7X in general. PIC 16C71 as four analog channels of 8-bit ADC, with 20 µs of conversion time per channel. Four analog channels AIN, AIN1, AIN2, AAIN3 are the alternate functions of PORTA pins RA0, RA1, RA2, RA3, respectively. AD port configuration control bits PCFG1 AND PCFG0 in ADON1 decide the functions of pins RA0-RA3. This allows configuring pins RA0-RA3 as analog or digital inputs. QUESTIONS: 1) To load W register with some immediate data 05, the instruction is. 2) If a 1 is written in the I/O control register, the respective pin is configured as. 3) What is watchdog timer? 4) Explain the PIC oscillator connections:- 5) Explain FSR. 6) Explain POR and BOR. 7) Explain the operation of ADC in PIC with a example program. Page 41 of 41

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