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1 Politecnico i Torino Porto Institutional Repository [Proceeing] Automatic March tests generation for multi-port SRAMs Original Citation: Benso A., Bosio A., i Carlo S., i Natale G., Prinetto P. (26). Automatic March tests generation for multi-port SRAMs. In: IEEE 3r International Workshop on Electronic esign, Test an Applications (ELTA), Kuala Lumpur, MY, 7-9 Jan. 26. pp Availability: This version is available at : since: January 27 Publisher: IEEE Publishe version: OI:.9/ELTA.26.7 Terms of use: This article is mae available uner terms an conitions applicable to Open Access Policy Article ("Public - All rights reserve"), as escribe at html Porto, the institutional repository of the Politecnico i Torino, is provie by the University Library an the IT-Services. The aim is to enable open access to all the worl. Please share with us how this access benefits you. Your story matters. (Article begins on net page)

2 Automatic March Tests Generation for Multi-Port SRAMs A. Benso, A. Bosio, S. i Carlo, G. i Natale, P. Prinetto Politecnico i Torino ipartimento i Automatica e Informatica Torino, Italy {benso, bosio, icarlo, inatale, prinetto}@polito.it Abstract Testing of Multi-Port (MP) SRAMs requires special tests since the multiple an simultaneous access can sensitize faults that are ifferent from the conventional single-port memory faults. In spite of their growing use, few works have been publishe on testing MP memories. In aition, most of the publishe work concentrate only on two ports memories (i.e., 2P memories). This paper presents a methoology to automatically generate march tests for MP memories. It is base on generations of single port memory march test firstly, then etening it to test a generic MP SRAMs. A set of eperimental results shows the effectiveness of the propose solution.. Introuction Multi-Port memories (MP) peculiarity is their capability of performing more than one operation simultaneously. Semiconuctor MPs are compose of a unique array of memory cell an a p-port to access it (p 2). Each port has an inepenent set of aress, control, an ata buses, making possible writing a value on a cell while another cell is being rea. Multi-port SRAMs are nowaays wiely use as embee memories in a plenty of igital systems, like telecommunications ASICs an multiprocessor systems []. The problem of testing multi-port memories has been face using an a-hoc technique, without targeting specific functional fault moels, In [2] [3] the authors assume that Single Port (SP) test algorithms provie a high fault coverage when applie to MP memories. The test methoology performs SP test algorithms on each port, but the eep fall of the effectiveness of the applie tests shows that a-hoc fault moels for MP must be aopte. In [4] a new theoretical fault moel (comple coupling fault) an its test solution are presente. Unfortunately the fault moel is not valiate by eperimental analysis (i.e., it isn t a realistic fault moel), an the test compleity (i.e., the length of the test algorithm) is eponential w.r.t. the number of port: O(n p ). In [5] the authors present realistic fault moels valiate by inustrial analysis. Taking into account the simultaneous access in memories, march tests were evelope. All the publishe tests solutions have been manually generate, a task that always requires a lot of time, epertise, an that sometimes oes not succees in covering particularly comple memory faults. Although several methoologies to automatize the march tests generations have been propose [6] [7] [8] [9] [], none of them faces the problem of the MP test. In this paper, we present a systematic approach to automatically generate March Tests for MP SRAMs base on the tests generator engine presente in []. Moreover taonomy of realistic fault moels for generic p-port memories will be presente. The paper is structure as follows: section 2 presents the propose test generation methoology. In Section 3 a complete escription of memory faults moeling will be eploit. Section 4 etails the notation use to represent march tests for both single an multi port memories. In section 5 a etaile analysis of the methoology is presente, while section 6 provies eperimental results that proof the efficiency of our approach. Section 7 summarizes the main contributions an future evelopments of this research. 2. The Propose Test Generation Methoology The aopte methoology relies on a formal moel representing the fault behaviour (see Section 3). Proceeings of the Thir IEEE International Workshop on Electronic esign, Test an Applications (ELTA 6)

3 To automatize the test generation phase we first generate the single port march test by resorting the march test generation tool publishe in []. The main steps of the methoology are: (i) automatically translate the FPs to an operational representation of the faulty behaviour, referre to as Aresses FP, or AFP. (ii) The original memory graph moel is then automatically moifie accoring to the AFP, to buil the fault graph that is then traverse to generate the test. An efficient implementation has been one, profitably eploiting pruning conitions impose by the goal of primarily generating March Test. (iii) After the generation of Single Port (SP) March test, we apply the Multi Port translation able to eten the SP March in to MP march. Each generate march test has been valiate by simulation performe by memory fault simulator tool [] The overall generation methoology is summarize in Figure. Fault Graph Generation March Test Generator Valiation Fault Moels MP March Test SP March Tests Multi Port Transaltion Fault Simulator Figure : Automatic MP march tests generation flow 3. Fault moeling A Functional Fault Moel (FFM) is a eviation of the memory behavior from the epecte one uner a set of performe operations. A FFM involves one or more Faulty Memory Cells (FC) classifie in two categories: Aggressor cells (a-cells), i.e., the memory cells that sensitize a given FFM an Victim cells (v-cells), i.e., the memory cells that show the effect of a FFM. Each faulty behavior is sensitize by a sequence of stimuli applie on the FCs. In testing SRAMs, the stimuli to be applie are memory operations. When ealing with MP SRAMs, each stimulus coul be applie on a ifferent port. MP faults can thus be ranke into two main classes: Strong fault: a memory fault that can be fully sensitize by an operation; e.g., a single-port write P or rea operations fails, two simultaneous rea operations fail, etc. Weak fault: a fault which is partially sensitize by an operation; e.g., ue to a efect that creates a small isturbance of the voltage of the true noe of the cell. However, a fault can be fully sensitize (i.e., become strong) when two or more weak faults are sensitize simultaneously, since their faults effect can be aitive. This may occur when a MP operation is applie. Fault moeling requires a rigorous formalism; first of all we have to specify the initial conitions of the cell, i.e., the value (state) of the memory cell, where we are going to apply the operations. Hereinafter we use n as the size of the memory (i.e., the number of memory cells) efinition : C is the set of the memory states (values), formalize as C = { [i], [i], - [i] i n-} () where ape ientifies the aress of the cell. If the aress is omitte, it means that the state coul be applie on every memory cell inifferently. The - enotes a on t care conition. efinition 2: X is the set of the memory operations, formalize as X = {r [i] [], w [i] i n-; (,)} {t} (2) where: w i : a write operation of the value performe in the cell i; r i : a rea operation performe in the cell i. The value it is not strictly neee in case of a rea operation. If use, it means the epecte value that shoul be re from the i-th memory cell; t : a wait operation for a efine perio of time. This aitional element is neee to eal with ata Retention Faults [6]. If the aress is omitte, it means that the operation coul be applie on every memory cell, inifferently. Each FFM can be escribe by a set of Fault Primitives (FPs) [2]. efinition 3: A Sequence of conitions/operations (S) is the minimum sequence of stimuli an conitions of length m neee to sensitize the fault. The j-th conition/operation is represente as c[], where c C, an X. Proceeings of the Thir IEEE International Workshop on Electronic esign, Test an Applications (ELTA 6)

4 efinition 4: A Fault Primitive FP represents the ifference between an epecte (fault-free) an the observe (faulty) memory behavior, enote by: < SA ; SV / F / R > (3) Where SA an SV are the set of S respectively applie to a-cell an v-cell, neee to sensitize the given fault. Since S coul be applie via several ports in parallel, SA an SV are represente as: (S ) : (S 2 ) : : (S p ) p- (4) The : enotes the fact that the sequences of operations (from to p-) are applie simultaneously via the p ports. The ape enotes the target port. F = {(f) n f C } is the faulty behavior, i.e., the value (state) store in the victim cells after applying S. R = { (r) n r C } is the sequence of values rea on the aggressor cell when applying S. As an eample FP = < w : r ; / / - > means that the operations w an r performe on the a-cell, trough the two ports, when the initial state is for both a an v cells, causes the victim to flip. No aresses are specifie; therefore this fault can affect each couple of memory cell. The terminology of weak an strong faults is use in representing the MP FFMs as follow: FP enotes a strong fault represente by its FP, while wfp enotes the weak fault FP. For eample, RF enotes a strong Rea estructive Fault, while wrf enotes a weak Rea estructive Fault. wfp&wfp2 &wfpp: enotes a ppf consisting of p weak faults; & enotes the fact that the p faults in parallel (i.e., simultaneously) form the p- port fault (ppf). For eample the wrf&wrf&wrf enote a 3PF base on three weak RFs [] Several FPs classification rules can be aopte, base on the number of memory operations (m) neee to sensitize the FP (e.g., static when m = or ynamic fault elsewhere); or base on the number of memory cells (#FC) involve by the FP (e.g., single-cell where #FC = or n-cells fault, elsewhere) [2]. 3.. Multi Port Constraints As iscusse in the previous section, a MP FFM requires the use of the ports to perform the sensitizing operations in parallel. Physical constraints impose some limitations on the set of allowe concurrent memory operations: simultaneous write operations are not allowe; simultaneous rea operations are allowe; simultaneous rea an write are allowe. In this case the write operation has the highest priority an therefore the rea ata will be iscare; simultaneous operations are symmetric: (w :r ) sensitize the same fault as (r :w ); All the above constraints have been valiate by simulation eperiments in []. 4. March Test notation As pointe out in [3] a so calle March Test is compose of a sequence of March Elments (MEs). A March Element is a sequence of memory operations applie on every cell of the memory. The way one moves from a certain aress to the net one is calle aress orer (AO) an it characterizes each ME. The aress orer can be specifie resorting to the following symbols: : Increasing Aress Orer (Up AO) : ecreasing Aress Orer (own AO) : on t care aress orer : it is possible to use either the up or own AO Not necessarily an up/own AO means that the ME starts from the lowest/highest memory aress to the highest/lowest aress. One can choose an arbitrary AO an labeling it as up, without reucing the fault coverage of a given March Test [4]. The only constraint is that the own AO must be eactly the reverse of the Up AO. Hereinafter we enote a March Test by a { } bracket, an a ME by a ( ) bracket. The i-th operation is efine as op i X, where the aress of the target cell is not inicate since alreay specifie by the aress orer. The compleity of a March Test is efine as the number of memory operations it inclues. We can formalize the above efinitions resorting to the following contet free grammar [5]: efinition 5: A SP March Test is efine as: MTGsp = (N,, S, P) (5) where: N = {MT, ME, AO, OP,}is the collection of the nonterminal symbols; = {,, w, r,,, (, ), {, },,, }is the set of terminal symbols (i.e., the alphabet) ; S = MT is the start symbol. S N; P N (N ) * is the set of prouctions etaile as follows: Proceeings of the Thir IEEE International Workshop on Electronic esign, Test an Applications (ELTA 6)

5 ) MT '{' ME '}' 2) ME AO '(' OP ')' AO ' 3) OP ' w' ' r' ' w' ', ' OP ' r' 4) AO ' ' ' ' ' ' 5) '' ' ' (' OP ')' ME ', ' OP As an eample consier the follow March Test: { (w ) (r,w ) (r )} (6) Starting from (5) we can etene it to apply the operation simultaneously. efinition 6: A MP March Test is efine as: MTGmp = (N p, p, S p, P p ) (7) where: N p = N {OPs} is the set of the nonterminal symbols; p = { :, -, n } is the set of terminal symbols (i.e., the alphabet). on t care - enotes that any operation is allowe on the selecte port, an n enotes that no operations are allowe on the selecte port; S p = S is the start symbol. S p N p ; P p N p (N p p ) * is the set of prouctions etaile as follows: ) MT '{' ME '}' 2) ME AO '(' OP ')' AO '(' OP ' )' ME 3) OP OPs OPs', ' OP 4) OPs ' w' ':' OPs ' r' ':' OPs ' w' 5)OPs ' w' ' r' ' ' ' n' 5) AO ' ' ' ' ' ' 6) '' ' ' ':' OPs' r' ':' OPs The march test (6) coul be etene to MP test purpose as: { (w : n) (r : -, w : r ) (r : -)} (8) This march test has been translate for two port memories (i.e., only two operations at each time are applie in parallel). 5. Multi Port Translation The translation of a single port march test to a generic p Port march test is feasible uner the constraints presente in Section 2..This phase requires as input the single port march test previously generate, an the number p of port (Figure ) The input march test has to be formatte by the march test generator phase in orer to evience the nature of the memory operations (i.e., by labeling each operations of the march test), that can be clustere in three categories: ) Initializing operations : their can be only write operations; 2) Sensitizing operations : their coul be either write or rea operations; 3) Observing operations : their can be only rea operations; Note that an operation coul be, at the same time, sensitize an observe the fault (i.e., rea fault [3]) or initialize an sensitize the fault (i.e., state fault [3]) This labeling proceure is one by the SP march test generator, where the information about each operations (i.e., if an operation is a sensitizing or initializing or observing) irectly from the fault moel (Section 3). This phase correspons to a set of rewrite rules, since the single port march test can be consier as a string accepte by the grammar efine in (5) where each symbol is a memory operation. Each rewrite rules is represente by the regular epression formalism [5]. Table shows the rewrite rules, as an eample if an operation is tagge Sensitizing, then rule # will be aopte. In case of multiple labelling (i.e. the operation is labelle both Sensitizing an Observing ); the operator preceence has been implemente by the orer of rewrite rules. Table : rewrite rules # Operation Rewrite Rules Sensitizing w w : r : : r r r : r : : r 2 Initializing w w : n : : n 3 Observing r r : - : : - The rule having the highest preceence (# table ) is that relate to sensitizing operations, since we must a p- ifferent operations to apply in parallel to fully sensitize the fault. The problem of what kin of ae operations (write or rea) is solve by constraints etaile in Section 2.. Only simultaneous p rea operations are supporte or one write an p- rea operations are supporte. Therefore rule # inserts p- rea operations. The epecte value to rea from the memory cell () epens from the previous memory state. Proceeings of the Thir IEEE International Workshop on Electronic esign, Test an Applications (ELTA 6)

6 6. Eperimental results This section reports some eperimental results obtaine applying the propose algorithm to automatically generate March Tests to cover ifferent sets of faults. We first generate march tests able to cover 3 port FFMs etaile in [5] an here summarize for sake of reaability. FFMs involving one cell are: wrf&wrf&wrf : applying three simultaneous rea operations to the v-cell causes the cell to flip, but returning the correct values. (eceptive Rea estructive Fault, RF); wrf&wrf&wrf : applying three simultaneous rea operations to the v-cell causes the cell to flip, returning the incorrect value. (Rea estructive Fault, RF) FFMs involving two cells are: wcfs&wcfs&wcfs : applying three simultaneous operations to the a-cell causes the cell to flip. (isturb Coupling Fault, CFs ) wcfs&wrf&wrf : applying three simultaneous rea operations to the v-cell causes the cell to flip if the a-cell is in a specific state, but returning the correct values. wcfs&wrf&wrf : applying three simultaneous rea operations to the v-cell causes the cell to flip if the a-cell is in a specific state, returning the incorrect values. Consier as an eample the wcfs&wcfs&wcfs that is escribe by 8 FPs in Figure 2. w : r : r ;/ /, w : r : r ;/ /, w : r : r ;/ /, w : r : r ;/ /, r : r : r ;/ /, r : r : r ;/ /. Figure 2 : {,}, = on t care The FFM is fully sensitize by the applications of the three weak faults on the ifferent memory port. We generate first the SP march test covering the first FPs an summarize in Figure 3 w ; / /, w ;/ /, w ; / /, w ;/ /, r ; / /, r ;/ /. Figure 3 : single port FPs, {,} The generate SP march test is { (w ) (r,w ) (r,w ) (r,w ) (r,w ) (r )} (9) After MP translation (i.e., applying the rewrite rules Table ) we obtain: { (w -:-) (r :r :r,w :r :r ) (r :r :r,w :r :r ) () (r :r :r,w :r :r ) (r :r :r,w :r :r ) (r : -:-)} That is able to cover wcfs&wcfs&wcfs [5]. Table 3 shows the resulting March Tests. For each march test we report its compleity (length of march test) an the equivalent march test foun in literature, an the targete fault list, the last column shows the cpu time (in secon). The algorithm has been implemente in about 9 lines of C++ coe, compile with gcc compiler. All the eperiments are performe on an ASUS, AM 5Mhz base Laptop with 52 MB of RAM. Table 2 reports the fault list covere by each march test. The first four generate march tests have been alreay publishe [5], the last three are unknown, an #7 (whose compleity is 22n) has the same structure of march SS [6]. It is able to etect all the static faults (one an two-cells) etensions for multiple-port memories. All generate March Tests have been verifie using an a hoc memory fault simulator [] able to valiate their correctness w.r.t. the target FP list. The fault simulator is also use to check the nonreunancy of each generate March Test. 7. Conclusion This paper presente a methoology to automatically generate March Tests for multiple-port memories. A general moel has been use to represent known memory static faults, an to possibly a new userefine faults. The generation process stems from the generation of SP march tests, then properly translate into MP march tests by applying a set of rewrite rules. Eperimental results have been presente to prove the applicability an the efficiency of the propose approach. On going activities are focuse on the automatic generation of MP march tests targeting aitional classes of memory fault, incluing ynamic an Linke Faults. Table 2 : fault list # Fault List # wrf&wrf&wrf wrf&wrf&wrf #2 wcfs&wcfs&wcfs #3 wcfs&wrf&wrf wcfs&wrf&wrf #4 All the 3port FFM #5 All the single cell Static Fault #6 All the CFs #7 All static FFMs Proceeings of the Thir IEEE International Workshop on Electronic esign, Test an Applications (ELTA 6)

7 8. References Table 3 : eperimental results # Algorithm # #2 #3 #4 #5 #6 #7 {(w :-:-) (r :r :r,r :-:-) (w :-:-) (r :r :r,r :-:-)} {(w -:-) (r :r :r,w :r :r ) (r :r :r,w :r :r ) (r :r :r,w :r :r ) (r :r :r,w :r :r ) (r : -:-)} {(w :-:-) (r :r :r, r :-:-,w :-:-) (r :r :r, r :-:-,w :-:-) (r :r :r, r :-:-,w :-:-) (r :r :r, r :-:-,w :-:-)} {(w :-:-) (r :r :r,r :-:-,w :r :r ) (r :r :r,r :-:-,w :r :r ) (r :r :r,r :-:-,w :r :r ) (r :r :r,r :-:-,w :r :r ) (r :-:-)} {(w :-:-) (w :r :r ) (r :r :r, w :r :r, r :-:-) (w :r :r ) (r :r :r, w :r :r,r :-:-)} {(w -:-) (r :r :r,w :r :r,w :r :r ) (r :r :r,w :r :r,w :r :r ) (r :r :r,w :r :r,w :r :r ) (r :r :r,w :r :r,w :r :r ) (r -:-)} {(w -:-) (r :r :r,r :-:-,w :r :r,r :-:-,w :r :r ) (r :r :r,r :-:-,w :r :r,r :-:-,w :r :r ) (r :r :r,r :-:-,w :r :r,r :-:-,w :r :r ) (r :r :r,r :-:-,w :r :r,r :-:-,w :r :r ) (r :-:-)} O (n) Known March Test CPU time (s) 6n 3PF.3 n 3PF2a.28 3n 3PF2v.2 4n 3PF.24 9n n -,2 22n -.22 [] S.Hamioui, Testing Multi-Port Memories: Theory an Practice [2] M.J. Raposa, ual-port Static Ram Testing ITC 988, IEEE International Test Conference, 988, pp [3] T. Matsumara, An Efficient Test Metho for Embee Multi-Port RAM with BIST Circuitry MTT 995: IEEE International Workshop on Memory Technology, esign an Testing, 995, pp [4] K. Chakrabortry P. Mazumer, New March Test for Multi-Port RAM evices, Journal of Electronic Testing: Theory an Application, vol 6, 2, pp [5] S. Hamioui; A.J. Van e Goor;. Eastwick, M. Rogers, etecting unique faultsi in multi-port SRAMs ATS 2, th IEEE Asian Test Symposium, 2, pp [6] A. J. van e Goor, B. Smit, Generating March Tests Automatically, ITC 994, IEEE International Test Conference, 994, pp [7] K. Zarrineh, S. J. Upahyaya, S. Chakravarty, A New Framework for Generating Optimal March Tests for Memory Arrays, ITC 998, IEEE International Test Conference, 998, pp [8]. Niggemeyer, E.M. Runick, Automatic Generation of iagnostic Memory Tests Base on Fault ecomposition an Output Tracing, IEEE Transactions on Computers, Volume: 53, Issue: 9, Sept. 24 pp [9] A. Benso, S. i Carlo, G. i Natale,P. Prinetto, An optimal algorithm for the automatic generation of March tests ATE 22, IEEE esign, Automation an Test in Europe Conference an Ehibition, 22 pp [] A. Benso, A. Bosio, S. i Carlo, G. i Natale, P. Prinetto, Automatic March Tests Generation for Static an ynamic Faults in SRAMs, ETS 25, th IEEE European Test Symposium, 25. [] A. Benso, S. i Carlo, G. i Natale, P. Prinetto, Specification an esign of a new memory fault simulator, ATS 22, th IEEE Asian Test Symposium, 22. pp [2] A. J. van e Goor, Z. Al-Ars, Functional Memory Faults: A Formal Notation an a Taonomy, VTS 2, 8th IEEE VLSI Test Symposium, 2, pp [3] A. J. van e Goor, Testing Semiconuctor Memories: theory an practice, Wiley, Chichester (UK), 99 [4]. Niggemeyer, M. Reeker, J. Otterstet, Integration of non-classical faults in stanar March tests, MTT 998, IEEE International Workshop on Memory Technology, esign an Testing, 998, pp [5] A.V. Aho, R. Sethi, J.. Ullman, Compilers: Principles, Techniques an Tools, AisonWesley, 986. [6] S. Hamioui, A J. van e Goor, M. Rogers, March SS: A Test for All Static Simple RAM Faults, MTT 22: IEEE International Workshop on Memory Technology, esign an Testing, 22 pp. 95 Proceeings of the Thir IEEE International Workshop on Electronic esign, Test an Applications (ELTA 6)