# CSCI 402: Computer Architectures. Arithmetic for Computers (4) Fengguang Song Department of Computer & Information Science IUPUI.

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1 CSCI 402: Computer Architectures Arithmetic for Computers (4) Fengguang Song Department of Computer & Information Science IUPUI Homework 4 Assigned on Feb 22, Thursday Due Time: 11:59pm, March 5 on Monday night You have 1.5 weeks (not 2 weeks!) TA will post the solution on March 6 or 7 Your Midterm Exam is on March 8 so you can prepare for it , 3.18 (assuming both inputs are two-digit octal numbers consisting of 6 binary bits) 3.20, 3.22, 3.23, 3.24, , 3.42,

2 IEEE Floating-Point Format single: 8 bits double: 11 bits S Exponent single: 23 bits double: 52 bits Fraction x = ( 1) S (1+Fraction) 2 [0, 255] (stored Exponent Bias) S: sign bit (0 Þ non-negative, 1 Þ negative) Normalized significand: 1.0 significand < 2.0 Always has a leading (pre-binary-point) 1, so no need to represent it explicitly ( hidden bit ) Significand = Fraction with the 1. restored Stored exponent = actual exponent + Bias Actual exponent = stored exponent - Bias Stored exponent is unsigned: e.g., 0 to 255, or 0 to 2047 Single: Bias = 127; Double: Bias = Floating-Point Example (1/2) Q: How to represent (= ) 0.75 = ( ) //normalized number S = 1 Fraction = Stored exponent = 1 + Bias Single: = 126 = Double: = 1022 = Single: Double:

3 Floating-Point Example (2/2) Q: What decimal value is represented by the following single-precision floating-point number? S = 1 Stored exponent = = 129 Fraction = x = ( 1) 1 ( ) 2 ( ) = ( 1) = Floating-Point Addition (base 10) First, consider a decimal example (suppose 4 digits of significand and 2 digits of exponent) Align decimal points (equal exponent) 4 Steps Shift the number with smaller exponent Now, exponents are equal 2. Add significands = Normalize result & check for over/underflow Round and renormalize the output if necessary

4 Floating-Point Addition (binary) Similarly, consider a 4-digit binary example (i.e., ) Step 1. Align binary points (s.t. equal exponent) Shift the number with smaller exponent Step 2. Add significands = Step 3. Normalize result & check for over/underflow , //-4 is between -127 and 128. Step 4. Round and renormalize if necessary (no change) = FP Adder Hardware Step 1 Larger exp Smaller frac Larger frac Step 2 New faction Step 3 Step

5 FP Adder Hardware It is more complex than integer adder Doing it in one cycle would make the clock cycle too long! Note that a slower clock would penalize all instructions So, FP Adder takes several cycles Can be pipelined 12 Next: Floating Point Multiplication Given two Operands (2 normalized inputs) as follows: (-1) S1 m1 2 E1 // m1 is the significand: 1.xxxxx (-1) S2 m2 2 E2 Exact Result? Suppose it is: (-1) S m 2 E Sign s: s = 1 if s1 ¹ s2; s = 0 otherwise Significand m: m1 * m2 //just multiply two significands Exponent E: E1 + E2 Fixing result: Round output m to fit the significand precision Overflow if E out of range Implementation: The most complex part is multiplying 2 significands 13 5

6 Floating-Point Multiplication Again, first consider a decimal example (suppose 4 digits of significand and 2 digits of exponent) Add exponents New exponent = = 5 2. Multiply the two significands = Þ Normalize result & check for over/underflow Round and renormalize if necessary Determine sign of result from signs of operands Floating-Point Multiplication Now, let s consider a 4-digit binary example ( ) 1. Add exponents Unbiased: = 3 2. Multiply significands = Þ Normalize result & check for over/underflow // no over/underflow 4. Round and renormalize if necessary // (no change) 5. Determine sign: +ve ve Þ ve =

7 1.000 x FP MIPS Instructions Floating point hardware is an adjunct processor that extends the existing MIPS ISA Called coprocessor 1 (c1) There are 32 separate FP registers 32 single-precision: \$f0, \$f1, \$f31 Can be paired for storing double-precision: \$f0/\$f1, \$f2/\$f3, i.e., 16 double-precision registers FP Instructions can operate only on FP registers Also, special load and store instructions lwc1, swc1 ldc1, sdc1 e.g., lwc1 \$f8, 32(\$sp) 17 7

8 CPU (central processing unit) FPU (floating point unit) "coprocessor 1" mfc1 register \$0,..,\$31 integer arithmetic division multiplication logical ops mtc1 register \$f0,.. \$f31 floating point arithmetic divison multiplication int float convert sw lwc1 lw swc1 Memory (2^32 bytes) 18 FP MIPS Instructions Single-precision arithmetic add.s, sub.s, mul.s, div.s e.g., add.s \$f0, \$f1, \$f6 //F0=F1+F6 Double-precision arithmetic add.d, sub.d, mul.d, div.d e.g., mul.d \$f4, \$f4, \$f6 //F4=F4*F6 Comparison c.xx.s, c.xx.d (xx is eq, lt, le, ) will set FP condition-code bit e.g. c.lt.s \$f3, \$f4 Branch on FP condition code true or false bc1t ( branch C1 true ), bc1f ( branch C1 false ) e.g., bc1t TargetLabel 19 8

9 FP MIPS Example: F to C C code: float f2c (float fahr) { return ((5.0/9.0)*(fahr )); } fahr in \$f12, result in \$f0, literals stored in Global memory Compiled MIPS code: f2c: lwc1 \$f16, const5(\$gp) lwc1 \$f18, const9(\$gp) div.s \$f16, \$f16, \$f18 lwc1 \$f18, const32(\$gp) sub.s \$f18, \$f12, \$f18 mul.s \$f0, \$f16, \$f18 jr \$ra //F16 = 5.0/9.0 //product result 20 FP Example: Array Multiplication X = X + Y Z All matrices, 64-bit double-precision elements C code: void mm (double x[][], double y[][], double z[][]) { int i, j, k; } for (i = 0; i! = 32; i = i + 1) for (j = 0; j! = 32; j = j + 1) for (k = 0; k! = 32; k = k + 1) x[i][j] = x[i][j] + y[i][k] * z[k][j]; Addresses of x, y, z in \$a0, \$a1, \$a2, and i, j, k in \$s0, \$s1, \$s2 21 9

10 n FP Example: Array Multiplication MIPS code: li \$t1, 32 # \$t1 = 32 (row size/loop end) li \$s0, 0 # i = 0; initialize 1st for loop L1: li \$s1, 0 # j = 0; restart 2nd for loop L2: li \$s2, 0 # k = 0; restart 3rd for loop sll \$t2, \$s0, 5 # \$t2 = i * 32, i-th row addu \$t2, \$t2, \$s1 # \$t2 = i * 32 + j, j-th column sll \$t2, \$t2, 3 # \$t2 = byte offset of [i][j] addu \$t2, \$a0, \$t2 # \$t2 = byte address of x[i][j] l.d \$f4, 0(\$t2) # \$f4 = 8 bytes of x[i][j] L3: sll \$t0, \$s2, 5 # \$t0 = k * 32, k-th row addu \$t0, \$t0, \$s1 # \$t0 = k * 32 + j, j-th column sll \$t0, \$t0, 3 # \$t0 = byte offset of [k][j] addu \$t0, \$a2, \$t0 # \$t0 = byte address of z[k][j] l.d \$f16, 0(\$t0) # \$f16 = 8 bytes of z[k][j] 22 Accuracy of Floating Point Numbers Only a subset of real numbers can be represented by computer! 24 10

11 Accurate Arithmetic NOTE: Floating-point numbers are approximations of real numbers 53 bits vs infinite number of real numbers (consider [0.0, 1.0]) IEEE Std 754 offers a rounding control Allow programmer to fine-tune numerical behavior of a computation HW always keeps two extra bits of precision (guard, round) Will be used during intermediate computations But not all FP hardware implement all options Most programming languages and FP libraries just use defaults 25 Accurate Arithmetic Guard & Round bits IEEE 754 standard specifies the use of 2 extra bits on the right during intermediate calculations Guard bit and Round bit Example: Add and assuming 3 significant digits and without guard and round bits = With guard and round bits ROUND

12 IEEE Std 754 has 4 different rounding modes 1st is the default; Others are called directed rounding. Round to Nearest round to the nearest value And Ties to Even : If the number falls midway, it is rounded to the nearest even number Round toward 0 directed rounding towards zero (or truncation) Round toward + directed rounding towards positive infinity (ceiling) Round toward directed rounding towards negative infinity (floor) \$1.40 \$1.60 \$1.50 \$2.50 -\$1.50 Nearest even \$1.00 \$2.00 \$2.00 \$2.00 -\$ Accurate Arithmetic A conceptual view: First compute exact result Then make it fit into the desired precision Possibly overflow if exponent too large Possibly round to fit into significand Rounding modes (illustrate with \$ rounding) \$1.40 \$1.60 \$1.50 \$2.50 -\$1.50 Zero \$1.00 \$1.00 \$1.00 \$2.00 -\$ \$1.00 \$1.00 \$1.00 \$2.00 -\$ \$2.00 \$2.00 \$2.00 \$3.00 -\$1.00 Nearest even \$1.00 \$2.00 \$2.00 \$2.00 -\$2.00 Rounding methods in case of tie cases (fraction = 0.5) No problems in case of fraction 0.5 However, IRS always round up 0.5! Fused Multiply Add: a = a + (b x c). //round only once at the end! 28 12

13 Interpretation of Data The BIG Picture Bits have no inherent meaning! Could be anything E.g., 32 bits, what does it mean? Interpretation depends on the instruction applied Computer representations of numbers have limited range and limited precision You must know they are approximations (have rounding errors)

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