CSE 260 Digital Computers: Organization and Logical Design. Exam 2. Jon Turner 3/28/2012

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1 CSE 260 Digital Computers: Organization and Logical Design Exam 2 Jon Turner 3/28/ (15 points). Draw a diagram for a circuit that implements the VHDL module shown below. Your diagram may include gates, muxes and one or more 8 bit subtractors (that is, a circuit with two 8-bit inputs x and y and an 8 bit output equal to the difference x y). Assume that the type of word is an 8 bit std_logic_vector. entity foo is port(a, B: in word; U, V: out word); end foo; architecture bar of foo is function negate(en: std_logic; x: word) return word is begin if en = '0' then return x; else return (x'range => '0') - x; end function negate; function absval(x: word) return word is begin return negate(x(x'high),x); end function absval; function absdiff(x, y: word) return word is begin return absval(x-y); end function absdiff; begin U <= absval(a); V <= absdiff(absval(a),b); end bar; - 1 -

2 2. (10 points) An abbreviated testbench for the priority queue circuit that we discussed in class is shown below. Recall, the circuit can store eight (key,value) pairs. The testbench applies a sequence of test inputs to the circuit and checks the circuit output using assertions. Fill in the blanks in the test data. architecture a1 of testpriqueue type testvector is record key,val: std_logic_vector(3 downto 0); insert,delete: std_logic; smallval: std_logic_vector(3 downto 0); empty, full: std_logic; end record invec; type testdata is array(natural range <>) of testvector; constant td: testdata := ( -- key val insert delete smallval empty full (x"4", x"f", 1, 0, x f, 0, 0 ), (x"3", x"e", 1, 0, x e, 0, 0 ), (x"5", x"d", 1, 0,,, ), -- fill blanks (x"6", x"c", 1, 0,,, ), -- fill blanks (x"2", x"b", 1, 0,,, ), -- fill blanks (x"1", x"a", 1, 0,,, ), -- fill blanks (x"7", x"d", 1, 0,,, ), -- fill blanks (x"8", x"9", 1, 0,,, ), -- fill blanks (x"0", x"0", 0, 1,,, )); -- fill blanks... begin priq: priqueue port map(clk, reset, insert, delete, key, value, smallval, busy, empty, full); process begin wait for pause; reset <= '1'; wait for clkperiod; reset <= 0 ; wait for clkperiod; for i in td'low to td'high loop key <= td(i).key; value <= td(i).value; insert <= td(i).insert; delete <= td(i).delete; wait for clkperiod; assert (busy = 1 ) report... wait for clkperiod; assert (smallval = td(i).smallval and empty = td(i).empty and full = td(i).full and busy = 0 ) report... end loop; end process; end a1; - 2 -

3 3. (20 points) Complete the block diagram on the next page so that it implements the VHDL specification shown below. You may add gates or multiplexors to the diagram. The body of the architecture is reproduced on the next page for your convenience. entity tripleupcount is port clk, reset: std_logic; A: std_logic_vector(7 downto 0); event: out std_logic; eventcount: out std_logic_vector(7 downto 0) end tripleupcount; architecture a1 of tripleupcount begin type statetype is (s0, s1, s2); signal state: statetype; signal ev: std_logic; signal preva, count: std_logic_vector(7 downto 0); begin process(clk) begin if rising_edge(clk) then preva <= A; if reset = 1 then state <= s0; count <= (others => 0 ); else case state is when s0 => if A > preva then state <= s1; when s1 => if A < preva then state <= s0; elsif A > preva then state <= s2; when s2 => if A > preva then count <= count + 1; elsif A < preva then state <= s0; when others => end case; end process; event <= 1 when state = s2 and A > preva else 0 ; eventcount <= count; end a1; - 3 -

4 s bit reg (state) D >C compare =s2 =s1 =s0 0 1 A 8 bit reg (preva) D >C compare X > Y < 8 bit reg (count) D >C increment A A+1 reset event clk eventcount begin process(clk) begin if rising_edge(clk) then preva <= A; if reset = 1 then state <= s0; count <= (others => 0 ); else case state is when s0 => if A > preva then state <= s1; when s1 => if A < preva then state <= s0; elsif A > preva then state <= s2; when s2 => if A > preva then count <= count + 1; elsif A < preva then state <= s0; when others => end case; end process; event <= 1 when state = s2 and A > preva else 0 ; eventcount <= count; end a1; - 4 -

5 - 5 -

6 4. (20 points) A partial implementation of the binary input module that we ve been using in our labs is shown below. Fill in the missing parts of the implementation. Your VHDL should be complete and syntactically correct. You may continue on the next page. Make note of the provided comments. Be sure to specify all the output signals of binaryinmod. entity binaryinmod is port( -- inputs from S3 board clk: in std_logic; btn: in buttons; knob: in knobsigs; -- signals provided to internal circuit resetout: out std_logic; dbtn: out std_logic_vector(3 downto 1); -- debounced buttons 1-3 pulse: out std_logic_vector(3 downto 1);-- pulse version of 1-3 inbits: out word); -- value controlled by knob end binaryinmod; architecture a1 of binaryinmod is component debouncer generic (width: integer := 8); port( clk: in std_logic; din: in std_logic_vector(width-1 downto 0); dout: out std_logic_vector(width-1 downto 0) ); end component; component knobintf port( -- interface to knob clk, reset: in std_logic; knob: in knobsigs; -- input signals from knob tick: out std_logic; -- goes high each time knob turns clockwise: out std_logic; -- high if knob is turning clockwise delta: out word); -- equal to 1, 16, 16^2 or 16^3 -- each press on knob changes value end component; signal dbb: buttons; signal reset: std_logic; signal tick, clockwise: std_logic; signal bits, delta: word; signal prevdbb: buttons; signal knobbits: word; - 6 -

7 begin db: debouncer generic map(width => 4) port map(clk, btn, dbb); ki: knobintf port map(clk, reset, knob, tick, clockwise, delta); reset <= resetout <= dbtn <= process (clk) begin if rising_edge(clk) then end a1; - 7 -

8 5. (12 points). Convert the expression shown below to sum-of-products form, then use the K- map to get the simplest sum-of-products expression you can find. AB C + (A + B (C + D )) + BC 00 CD AB Use the K-map below to simplify the specified expression (the first summation lists the minterms, the second lists the don t cares). Σ m(1,2,4,5,8,13) Σ d(0,6,9,10,12,15) 00 CD AB

9 6. (8 points) Consider the circuit shown below. What is the minimum delay through this circuit, assuming that every gate has a delay of 1 ns? A B C X Y What is the maximum delay? Suppose every gate has a delay that can vary between 1 and 3 ns. What is the minimum delay in this case? What is the maximum delay? - 9 -

10 7. (12 points) The diagram shows a generic state machine labeled with various timing parameters (for example, the minimum delay from an input to a flip flop input is 2 ns and the maximum delay from a flip flop output to a flip flop input is 5 ns. next state logic inputs 3-5 ns 2-7 ns next state D >C synchronous output logic 1-4 ns synchronous outputs current state Is this circuit subject to hold time violations? Justify your answer. clk flip flop prop delay: 2-5 ns setup time: 1 ns hold time: 0.5 ns clock skew: 1 ns What is the smallest safe clock period for this circuit? If the clock goes from low to high at time t 0, during what time interval must the input signals be stable? If the clock goes from low to high at time t 0, during what time interval is it possible for the outputs to be changing?

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