Pollard s Tutorial on Clocked Stuff in VHDL

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1 Pollard s Tutorial on Clocked Stuff in VHDL Welcome to a biased view of how to do register type of stuff in VHDL. The object of this short note is to identify one way to easily handle registered logic in VHDL, and make it work in various situations. First of all, let s tackle the simplest, and yet a fairly complicated element, the flip-flop. That is, how does a simple (7474 D-type) flip-flop work, and how do we describe that in VHDL. First of all, remember that I am going for simplicity and functionality, not minute correct behavior. That will become evident as we go along. First of all, let s review what the D-type flip flop does. If we look at a schematic that utilizes a simple D-type flip-flop, especially one that is a little older, we will see a symbol something like: Okay, there are four inputs and two outputs on this symbol. The inputs are: D, CLK, CLR, and SET. The outputs are Q and QN; the latter is really Qbar or Qnot. The set and the clear are asynchronous they do not have anything to do with the system clock. So, for the purposes of starting this note, let s ignore them and have just the remaining inputs and outputs: The basic function of the D-type flip-flop is to remember (on the Q output) the value at the D input when the active edge of the clock happens. Hence, the D input is the data input, and it is this value that will be remembered. The clock line is then used to identify an instant in time. In this case, the instant in time is when there is a rising edge on the clock when it goes from a low logic value to a high logic value. This function the causing of some action when there is a rising edge on the clock happens so often and is so important that there is a special symbol for it. This is what looks like a greater-than symbol just before the CLK input on the device. Whenever you see this symbol, the action of that device (register, counter, shifter, etc.) occurs on a low-to-high transition on the clock. So, looking at the symbol, its inputs and outputs, it is possible to state in words the function of the D-type flip-flop: whenever there is a low-to-high transition on the clock line, the logic level of the D input will be transferred to the Q output. And, at the same time, the inverse of the logic level of the D input will be transferred to the QN output. The next thing we want to do, at least for this note, is to create a VHDL design unit that describes this system as we understand it. It will need an entity part for the interface, and an architecture part for the functionality.

2 VHDL code which implement the function described above is: library IEEE; use IEEE.STD_LOGIC_1164.all; entity DFF is port ( D : in STD_LOGIC; CLK : in STD_LOGIC; Q : out STD_LOGIC; QN : out STD_LOGIC ); end entity DFF; -- the data input -- the clock line -- the Q output -- the Q bar output architecture BEHAVIORAL of DFF is signal QVAL : STD_LOGIC; -- internal val D_PROC: -- name is optional process ( CLK ) is -- work when CLK changes if RISING_EDGE ( CLK ) then -- low-to-hi trans QVAL <= D; -- transfer D to Q (internal) -- end of edge check end process; -- end of flip-flop process Q <= QVAL; QN <= not QVAL; -- hook up asserted-high out -- hook up asserted-low out end architecture BEHAVIORAL; Now for the comments about what this code describes. In the entity part we specify the two inputs and outputs all as STD_LOGIC elements. This identifies how the rest of the world is to interact with this unit. The names are then visible to be used (or generated) in the architecture part of the design unit. Next, in the declaration area of the architecture we call out the element QVAL as an STD_LOGIC signal. This is basically an internal storage element for the system, and we will create the function with the statements in the architecture (which in this case are simply a register function) then have a statement that hooks up this internal value to the output of the design unit. The work of the architecture is handled by the process. And the hard work in the process we delegate to a function in the library. This is the function RISING_EDGE, which looks ford a low-to-high transition on the clock line. The function accepts a single argument, which must be a signal of type STD_LOGIC, and returns a boolean TRUE when there is a low-to-high transition on the input, or a boolean FALSE at all other times. Hence, placing the QVAL <= D signal assignment statement in an IF statement enabled by the RISING_EDGE function, the only time that the D value will be copied to the QVAL signal is when there is a rising edge on the clock. The QVAL signal then holds the value until the next low-to-high transition on the clock line, when the QVAL value is updated (which may be with the same logic value). This internal flip-flop is then connected to the outputs identified in the entity part by the last two statements in the architecture, which are both signal assignment statements. Note that any change in QVAL is immediately reflected in both the Q and the QN outputs.

3 The above explanation of the functionality of the D-type flip-flop describes the action of most of the action of a flip-flop. However, sometimes there is a need to have a flipflop be set to a certain value, either to force a 1 value or a 0 value as needed by the system. This is accomplished by including the set and clear inputs, as shown in the first symbol shown above. Expanding the VHDL to include these inputs results in: library IEEE; use IEEE.STD_LOGIC_1164.all; entity DFF is port ( D : in STD_LOGIC; CLK : in STD_LOGIC; SET : in STD_LOGIC; CLR : in STD_LOGIC; Q : out STD_LOGIC; QN : out STD_LOGIC ); end entity DFF; -- the data input -- the clock line -- force Q to '1' -- force Q to '0' -- the Q output -- the Q bar output architecture BEHAVIORAL of DFF is signal QVAL : STD_LOGIC; -- internal val D_PROC: -- name is optional process ( SET, CLR, CLK ) is -- work when any of SET, -- CLR, CLK change if SET = '0' then -- if SET asserted, then QVAL <= '1'; -- force '1' in flip-flop elsif CLR = '0' then -- if CLR asserted, then QVAL <= '0'; -- force '0' in flip-flop elsif RISING_EDGE ( CLK ) then -- else check on low-to-hi QVAL <= D; -- trans transfer D to Q (internal) -- end of action check end process; -- end of flip-flop process Q <= QVAL; QN <= not QVAL; -- hook up asserted-high out -- hook up asserted-low out end architecture BEHAVIORAL; Note that there are basically two changes. The first is in the entity part, where the port statement has been expanded to include both the set and the clear lines. The second change is seen in the architecture, where the if statement has been expanded to check for the set and clear conditions. The work of the process is going to happen whenever there is a change in any of the three signals set, clear, or clock. In the above process, the first thing that is checked is the SET line. Note that this may not be what the user wants to do. Question is, what happens if both SET and CLR are asserted simultaneously? In real life, that causes problems. In this code, the implication is that the SET prevails over the CLEAR. So, one of the things that a user must do is weigh the cost of a more accurate VHDL description versus using a description like that shown above. The decision is probably to be made based on some criteria outside the range of considerations for this short note. Hence we will let the above description stand and not try to modify it further.

4 Another note should be made concerning the assertion levels shown in the description above. In the symbol for the flip-flop, both the set and the clear inputs have logical state indicators associated with them (the little bubble on the input line). This indicates that the inputs are asserted low the action (the set or the clear) occurs when the corresponding input is low. This is historically accurate, as most of the asynchronous stuff (set or clear) for older logic is asserted low. However, in the case of the stuff going on inside of FPGAs, the assertion level can be specified by the user, so much of what we will describe will actually be asserted high. Next, let s consider the activity of putting several of these flip-flops together in order to make a register. As the name suggests, a register is an element meant to store or register a value. And generally registers of this type are little more than a collection of individual flip-flops. For example, the one being considered here is the 74xx273, where the xx could be any of a number of different technology specifiers. All have the same function, and a diagram taken from one of the data sheets is: The diagram shows eight flip-flops connected together. Well, the flip-flops all share a common clock line and a common reset line (MR, or Master Reset). Note that the reset line of this unit is asserted low. Another interesting note is the presence of the buffers on the clock and reset lines. These buffers are their to reduce the electrical load on the elements supplying the clock and reset functions. Hence, the function of this device is: if the reset line is low, force outputs to zero. Otherwise, on the rising edge of the clock, store the 8 bit input value into the flip-flops and present these bits at the 8 output bits. The VHDL for this activity is almost identical to that already seen for the flip-flop. The main differences are to leave out the set function and to make the data paths 8 bits wide: library IEEE; use IEEE.STD_LOGIC_1164.all; entity SN74273 is port ( RST : in STD_LOGIC; -- force Q to '0' CLK : in STD_LOGIC; -- the clock line -- the data input DIN : in STD_LOGIC_VECTOR ( 7 downto 0 ); -- the 8 bit output DOUT : out STD_LOGIC_VECTOR ( 7 downto 0 ) ); end entity SN74273; architecture BEHAVIORAL of SN74273 is

5 signal REG : STD_LOGIC_VECTOR ( 7 downto 0 ); -- internal val REG_PROC: -- name is optional process ( RST, CLK ) is -- work when RST or CLK change if RST = '0' then -- if CLR asserted, then REG <= X"00"; -- force zeros to register elsif RISING_EDGE ( CLK ) then -- else check on low-to-hi REG <= DIN; -- trans transfer DIN to REG -- end of action check end process; -- end of flip-flop process DOUT <= REG; -- hook up output end architecture BEHAVIORAL; The port statement contains the reset and clock, as before, both as STD_LOGIC values. However, the port statement also identifies the input data (DIN) and output data (DOUT) as STD_LOGIC_VECTORs, each with a range from 7 down to 0. Hence, the data values are both 8 bits wide. Other than that, the code for the register is basically identical to the code for the flip-flop. The 8 bit data width is the product of two different aspects of real systems. Obviously many data paths are some multiple of 8 bits wide, since an 8 bit byte is a basic element of many systems. The other aspect is physical: how many bits can you fit into a package. The 273 shown above has 8 data inputs and 8 data outputs that s 16 pins plus clock and reset that makes 18 pins and finally power and ground that makes 20 pins. The 20 pin device has been a very useful form factor for many of the devices that have appeared over the years, so this modular approach has been utilized by many in the creation of digital systems. Note that for stuff that you make within an FPGA, the 8 bit limit is artificial. That is, there is no physical thing like trying to fit into a 20 pin package that restricts the number of bits in the register. Hence, a register as wide as needed can be created by using the code above and simply changing the range of the input and output elements in order to make the width of the register fit the desired system. Oh, another thing demonstrated by the above code, and that is the use of strings to represent hexadecimal values. The 8 bits of zero for clearing the register is specified by the construct X 00. The X in front specifies that the value in the string will be a hexadecimal value, and the characters between the double-quotes specify the actual value. In this case, the value is 8 bits of zero. Note that this technique for identifying binary values only works for bit strings that have a length that is a multiple of four. The above examples identify a technique for making simple registers: identify the inputs and outputs in the entity part, then specify when to fill the register and how to hook it up in the architecture body. By using the RISING_EDGE function to check for the edge of the clock, the user can specify when the action is to take place. In this case, the action is simply, accept the input value into the register. The style demonstrated here is to have the register represented by an internal signal, then drive the output values from that internal signal. The reasons for this will become apparent as we proceed.

6 The next part of this is to add some other functionality along with simply filling the register. That is, the examples above simply take an input value and place it someplace where it can be made available to a user. However, other functions can be implemented in much the same way. We will start with a very simple function, which is a counter. At this point, we pause in the specifics to look at the general. That is, we know that basic logic systems can be built to produce specific outputs given specific inputs. One basic mechanism for this is what we refer to as combinational systems, which can be represented simply as: Note that here the Outputs are functions only of the Inputs, or Outputs = fn( Inputs ) The contents of the Logic block can be determined by any of a number of different methods. Traditionally, this has been done with truth tables, Boolean algebra, K-Maps, etc. But note that there is nothing else involved an input changes, and after the characteristic delay of the Logic block, an output may change. The next step in the general picture is to move from the combinational realm to the sequential realm. The block diagram view is: In this case, there is a lot more involved. First of all, there is a register, made in the same manner that has been described above. In the figure, this register is called the PSR the Present State Register, since the bits in the register identify the state of the system. Now the outputs are no longer a function of the inputs only, but also the history of the system: Outputs = fn( Inputs, History ) And the history of the system, at least as much history as is needed for the system under consideration, is identified by the bits in the PSR. Hence, the first logic block utilizes the current inputs (available on the Inputs lines) and the Present State (also available as feedback signals) to determine the Next State. Note that in the diagram there is also a set of outputs (Outputs (A)) that are functions of both the Present State and the Inputs. Systems that utilize this technique are called Mealy Machines, and extreme care and caution should be taken when developing systems of this nature, since there can be glitches and other bad things on the outputs because the inputs are not necessarily

7 synchronous with the system clock. The diagram also shows a set of outputs (Outputs (B)) that are functions only of the present state. Systems that utilize this technique are called Moore Machines. For the stuff that we are doing in ECE 338, this is the preferred method of creating sequential logic systems. Of course, a counter is an example of a system in which the Present State Register bits are also the outputs, so the decode logic is non-existent. One classical way to represent the desired behavior of the system is to use a state diagram, in which each state of the system is identified as well as the transitions from state to state and the combinations of inputs that cause the system to transfer from one state to another. We start this activity with a simple decade counter a system that counts from 0 to 9 and then returns to 0. In the simplest case, that is all that this system does. Hence, there are no inputs to cause any other activity. A simple state diagram for this is: Note that, as mentioned above, there is no decision based on external inputs. All state transitions require only the current state to determine what the next state will be. And since the register will only change on the active edge of the clock, the counter proceeds from state to state in the count sequence whenever there is an active edge on the system clock. The gate level design for this system then starts with a Present State Next State table: A B C D A B C D X X X X X X X X X X X X X X X X X X X X X X X X Next step is to put this into a K-Map and reduce. This is a tedious process, but must be done at some time. The alternative is to practice all sorts of Boolean algebra stuff on

8 the equations that result, and come up with something that can be implemented. Anyway, there are four output signals identified in the truth table, and a K-map for each is: The classical way to deal with this is to have each of the state bits reside in a flip-flop and label the flip-flops A, B, C, and D. Then, convert the equations above into gates and have the outputs of the gates directed to the inputs of the flip-flops. But, we are trying to do this with VHDL, so we will do the same thing in the language representation. First of all, we should mention that a structural approach is possible with the above equations that it is possible to have VHDL components for the gates and connect them together as specified by the Boolean equations. However, we will do the same thing with the logic specified by the VHDL itself. First, let s look at the VHDL and then add appropriate comments. library IEEE; use IEEE.STD_LOGIC_1164.all; entity BCDCNTR is port ( RST : in STD_LOGIC; -- Force counter to zero CLK : in STD_LOGIC; -- the clock line A : out STD_LOGIC; -- The MSB of the counter B : out STD_LOGIC; -- The second MSB C : out STD_LOGIC; -- The second LSB D : out STD_LOGIC -- The LSB of the counter ); end entity BCDCNTR; architecture EQUATIONS of BCDCNTR is

9 signal AA : STD_LOGIC; -- internal version of A signal BB : STD_LOGIC; -- internal version of B signal CC : STD_LOGIC; -- internal version of C signal DD : STD_LOGIC; -- internal version of D COUNTER_PROC: -- name is optional process ( RST, CLK ) is -- work when RST or CLK change if RST = '1' then -- if CLR asserted, then AA <= '0'; -- set all BB <= '0'; -- four bits CC <= '0'; -- to logic zero DD <= '0'; elsif RISING_EDGE ( CLK ) then -- else check on low-to-hi -- the four equations below -- are derived directly from the -- equations of the BCD counter AA <= ( BB and CC and DD ) or ( AA and not DD ); BB <= ( not BB and CC and DD ) or ( BB and not DD ) or ( BB and not CC ) ; CC <= ( not AA and not CC and DD ) or ( CC and not DD ); DD <= not DD; end process; A <= AA; B <= BB; C <= CC; D <= DD; -- end of action check -- end of counter-register process -- hook internal A to external A -- hook internal B to external B -- hook internal C to external C -- hook internal D to external D end architecture EQUATIONS; The design unit has both the entity part and the architecture body. The entity part has the two inputs clock and reset and the four output bits: A, B, C, and D. Once again, the style being suggested here is to have an internal bit for each of the four bits of the counter, and these are set up as AA, BB, CC, and DD. And just like the previous register design units, the register action, which in this case is a count action, is described by a process. And the process has a sensitivity list with the reset line and the clock line. If the reset condition exists ( RST = 1 ) then the four internal bits are all set to zero. Otherwise, the RISING_EDGE ( CLK ) function checks for a rising edge on the clock line. If that is detected, then the count activity is implemented by the logic equations contained in the architecture body. A waveform for this system (minus reset) is: Note that the bits count exactly through the BCD count sequence, one count per clock cycle. And the changes are made on the rising edge of the clock, just as the register activity of the system would suggest it should.

10 The logic equations shown above are not by any means the only way to present the count sequence. Another obvious way is to have the system check for each pattern, and based on the pattern, to select the next pattern. In this case, the work statements of the process are nothing more than a case construct that looks for all of the patterns. The process then becomes: CASE_EXAMPLE_PROC: -- name is optional process ( RST, CLK ) is -- work when RST or CLK change if RST = '1' then -- if CLR asserted, then COUNT <= "0000"; -- set count to zero elsif RISING_EDGE ( CLK ) then -- else check on low-to-hi case COUNT is when "0000" => COUNT <= "0001"; -- case statement when "0001" => COUNT <= "0010"; -- specifies all when "0010" => COUNT <= "0011"; -- patterns and when "0011" => COUNT <= "0100"; -- the expected when "0100" => COUNT <= "0101"; -- behavior for when "0101" => COUNT <= "0110"; -- each of the when "0110" => COUNT <= "0111"; -- patterns when "0111" => COUNT <= "1000"; when "1000" => COUNT <= "1001"; when "1001" => COUNT <= "0000"; when others => COUNT <= "0000"; end case; -- end of action check end process; -- end of counter-register process The first explanation that needs to be made concerning this method is that we have changed the name of the internal bits so that all of the bits can be referred to jointly. That is, the bits are grouped as a single digit. So, there is a statement in the declaration area of the architecture that identifies COUNT as a signal of four bits. In this way, the four bits can jointly be considered as the target of the case construct. The case construct is then used to uniquely specify the expected patterns and the desired response for each pattern. Since there are four bits possible there are sixteen allowable combinations. However, with a decade counter, only ten of the sixteen are used. For that reason, the others case is also included, to handle any situations that may arise because the when clauses do not handle all possible situations. Another scheme that is an obvious choice for this system is to recognize that the patterns for the count are simply one more than the previous, except for the nine-to-zero change. Therefore, the work of the system can also be represented utilizing this fact. The architecture body can then be changed to something like: COUNT_PROC: process ( RST, CLK ) is -- work when RST or CLK change if RST = '1' then -- when reset, then COUNT <= "0000"; -- set count to zero elsif RISING_EDGE ( CLK ) then -- else check on low-to-high if COUNT = "1001" then -- check limiting case. if 9, COUNT <= "0000"; -- next value is zero else -- otherwise COUNT <= COUNT + "0001"; -- increment count by 1 -- end of what-to-do IF -- end of check-edge If end process; -- end of the process

11 This process uses the addition operator to add one to the current count, except in the case when the count is already nine. That condition is tested for, and if it exists, then the count is forced to zero. The above VHDL descriptions provide three different techniques for describing the same behavior logical equations, a case construct, and an addition operator. And if we tried we could find even more ways to create VHDL descriptions that result in the same behavior. It is the responsibility of the user to create descriptions that fulfill the requirements of the system and utilize the available resources of the system in reasonable ways. If adders are cheap and available, then the addition method might look good. If comparators are cheap and available, then the case construct might be the answer. Or, if logic gates are the fundamental building blocks, then the equation implementations are attractive. The user has the language to utilize as a tool to represent the system in a reasonable way. In all of the representations above, either for a register or for a counter, the same basic paradigm was used. That is, the thing that the descriptions have in common is the use of the process construct to describe register behavior. And that construct is: process ( RST, CLK ) is -- Sensitivity list if RST = '1' then -- when reset, then -- action when reset asserted elsif RISING_EDGE ( CLK ) then -- else check on low-to-high end process; -- action when active edge happens -- end of check-edge If -- end of the process In the sensitivity list, the signals that should appear are the reset and the clock. Any control line that causes the register to change should be listed here. Note that that does not include load lines, or synchronous clears, or any other enable type of signal. It only includes things like asynchronous clears or sets, or asynchronous loads, and especially clocks. The above explanation of registers and counters outlines a basic approach to clocked sequential logic use the RISING_EDGE function to look for an active edge, and use logic to determine what the new values in the register should be. In the examples above, the logic element has been determined by equations, by a case construct to enumerate the possibilities, and by arithmetic elements. However, there is another very important mechanism that can be brought into play at this point. We by noting that in the three examples for the BCD counter, the action always occurs on the clock edge. That is, every time that there is a clock edge, the counter advances to the next count. But, what if for some reason we didn t want to do that? For example, how could we take the BCD digit logic above and put it into a system with several BCD digits to make a counter capable of numbers much greater than the 0-9 range shown here. In that case, we may want to expand the entity to include two more signals: an enable input and an enable output. The enable output will be asserted when one digit position is ready to tell the next digit position to increment by one. That is, when the lesser significant digit is at 9 then the more significant digit should increment by one at the next edge, while the lesser significant digit rolls over from 9 to 0. Similarly, the enable in identifies the clock cycles in which the digit should change from one value to the next if the enable is

12 asserted then the digit increments, but if the enable is not asserted, then the current value is unchanged. Going back to the state machine approach, the state diagram changes to include the enable: The addition of another signal to determine when to move on to the next count does indeed uniquely define the sequence. And the implementation could follow the schemes introduced above. Note, however, that the addition of the single input bit doubles the size of the K-Maps used for the logic of the system. And the other methods are also complicated by this additional information. There is, however, a better way to approach this system. And that is to make the registers out of flip-flops that have an additional input: This flip-flop looks virtually identical to the other flip-flops shown above. Except that there is an additional input: E. The E signal is an enable. Hence, the paradigm involved here is slightly different. In words it is: when the enable signal is asserted and the active edge of the clock occurs, then Q receives a copy of D. However, when the enable signal is not asserted, then when the clock happens the contents of the flip-flop are not changed. This device can be used to build enabled registers or counters or anything that requires clocked sequential behavior. To continue with the examples demonstrated here, we expand the BCD counter to utilize the flip-flop type just described and incorporate the enables as well. The VHDL for the counter (using the addition method) is then: library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity BCDCNTR_WITH_ENB is port ( RST : in STD_LOGIC; -- Force counter to zero CLK : in STD_LOGIC; -- the clock line CNTR : out STD_LOGIC_VECTOR ( 3 downto 0 ); -- count out

13 ENB_IN : in STD_LOGIC; -- enable input ENB_OUT : out STD_LOGIC -- enable output ); end entity BCDCNTR_WITH_ENB; architecture ADDITION of BCDCNTR_WITH_ENB is signal COUNT : STD_LOGIC_VECTOR ( 3 downto 0 ); -- internal val CNT_ENB_PROC: process ( RST, CLK ) is -- work when RST or CLK change if RST = '1' then -- when reset, then COUNT <= "0000"; -- set count to zero elsif RISING_EDGE ( CLK ) then -- else check on low-to-high if ENB_IN = '1' then -- first check enable input then if COUNT = "1001" then -- check limiting case. If 9, COUNT <= "0000"; -- next value is zero else -- otherwise COUNT <= COUNT + "0001"; -- increment count by 1 -- end of what-to-do IF -- end of enable IF -- end of check-edge IF end process; -- end of the process -- the enable output is asserted if and only if the system -- is enabled to count (ENB_IN is asserted) and the current -- count of the is 4 bit digit is 1001 ENB_OUT <= '1' when ENB_IN = '1' and COUNT = "1001" else '0'; -- also, need to hook up external val from internal val CNTR <= COUNT; end architecture ADDITION; This demonstrates the method described above. That is, the process construct is used to implement a register, with the basic framework consisting of the test for the reset condition followed by the test for the active edge. If the active edge is encountered (without the reset asserted) then further conditions can be identified and checked in that part of the if construct. A comment should also be added here about the modularity and connectivity of the techniques being demonstrated here. In the design unit above, all of the work is done in the architecture body and all of the communication is handled in the entity portion, as expected in design units in VHDL. Hence, to make use of this module it is necessary to declare it as a component and instantiate it as many times as needed to implement a BCD counter of several digits. Note that in many cases the work can be done in a process and the results made visible to many different elements by simply declaring the signals in the declaration area of an architecture, then implementing the work with various processes in that same architecture. We will now further demonstrate this basic technique (the division of labor in the process itself) by creating a component patterned after the 74xx198 an 8 bit bidirectional shift register. This device will have an 8 bit input, an 8 bit output, two serial inputs (one for shifting left, the other for shifting right), a master reset, and two control lines. The code for this module is:

14 library IEEE; use IEEE.STD_LOGIC_1164.all; -- This design unit is modeled after the SN74F198, although -- it is not exactly the same. The difference is (in addition -- to using names that are different) reset is asserted high, not -- low The basic function is: -- When SYS_RST_H is high, force all outputs to zero -- On rising edge of clock, do something based on CNTRL -- CNTRL = 00 Do nothing (retain old value in register) -- CNTRL = 01 Shift right (toward smaller index) -- CNTRL = 10 Shift left (toward higher index) -- CNTRL = 11 Parallel load (from DIN lines) entity EIGHT_BI_DIR is port ( SYS_RST_H : in STD_LOGIC; -- Force register to all zeros SYS_CLK_H : in STD_LOGIC; -- the clock line DIN : in STD_LOGIC_VECTOR ( 7 downto 0 ); -- reg in DOUT : out STD_LOGIC_VECTOR ( 7 downto 0 ); -- reg out RSI : in STD_LOGIC; -- Right Serial Input LSI : in STD_LOGIC; -- Left Serial Input CNTRL : in STD_LOGIC_VECTOR ( 1 downto 0 ) -- control ); end entity EIGHT_BI_DIR; architecture BEHAVIORAL of EIGHT_BI_DIR is signal THE_REG : STD_LOGIC_VECTOR ( 7 downto 0 ); -- internal val SHIFT_REG_PROC: process ( SYS_RST_H, SYS_CLK_H ) is -- work when RST or CLK change if SYS_RST_H = '1' then -- when reset, then THE_REG <= X"00"; -- set register to zero elsif RISING_EDGE ( SYS_CLK_H ) then -- else check clk low-to-high -- Note that this work is after clock check if CNTRL = "01" then -- is it shift right? THE_REG <= LSI & THE_REG ( 7 downto 1 ); -- load shifted val elsif CNTRL = "10" then -- is it shift left? THE_REG <= THE_REG ( 6 downto 0 ) & RSI; -- load shifted val elsif CNTRL = "11" then -- is it parallel load? THE_REG <= DIN; -- load shifted val -- end of CNTRL IF -- end of check-edge IF end process; -- end of the process DOUT <= THE_REG; -- hook up output from internal val end architecture BEHAVIORAL; First comment about this code is that it follows directly the pattern above: the work is encapsulated in a process, and the if-then-elsif scheme is used for looking at the reset and the active edge of the clock. In the elsif part is found the work description shift left, shift right, load, or do nothing based on CNTR. The second comment to make at this juncture is that this same mechanism can be applied to all synchronous systems especially to state machines. The VHDL language allows us to specify the activities of

15 the clocked sequential systems in the way that is most natural or most appropriate for the application, and leave the implementation details to others. In particular, using the FPGA or CPLD (or ASIC, for that matter) paradigm, the hardware description language (VHDL) allows the user to specifically describe the desired behavior of the system, and then using the primitives of the system (the basic building blocks of the FPGA or CPLD system) the compiler will connect the basic building blocks together in such a way that the system described by the user is actually implemented. The next mechanism described here is the state machine, and in order to describe the process we present first a fairly simple system, and then a more complicated system. The simple system is easily described in the following way: consider a unit that is attached to a serial data line and looking for a particular sequence. That is, the block diagram of this system is: The system is to look for the sequence of bits , and when this is received, assert the output for one cycle, then looking again. Hence, the zero that ends one pattern cannot be construed to be the first zero of the next pattern. The state diagram for this system is: The state diagram is a graphical representation of the desired behavior of the system, and the task of the logic designer is to create a system that will follow the behavior that is represented by that state diagram. In the state diagram, each of the states has been given a separate, unique 3 bit value that represents the state of the system. The classical method of sequential design is to combine the current state and the inputs into a truth table, then create the logic needed to implement the state machine, exactly like the example above of the BCD counter. In the case of the BCD counter, there were no

16 external inputs, only the count. In this example, there is a single input bit for data. The resulting table is: Present State Input Next State X XXX As we did before, we can convert the truth table to a K-Map and then create the logic equations to implement it. Let the three state bits be C2, C1, and C0, with the data bit D, then the result is: C2 C1 C0 = = = C2 C1 C0 D + C2 C1 D + C1 C0 C2 C1 C0 D + C2 C1 C0 D + C2 C1 D C2 C1 C0 D + C2 C0 D + C1 C0 D + C2 C1 The VHDL that implements this system is represented as: library IEEE; use IEEE.STD_LOGIC_1164.all; entity SEQUENCER is port ( SYS_RST_H : in STD_LOGIC; -- Force system to idle SYS_CLK_H : in STD_LOGIC; -- the clock line D_H : in STD_LOGIC; -- input data OUT_VAL_H : out STD_LOGIC -- output signal ); end entity SEQUENCER; architecture EQUATIONS of SEQUENCER is signal C2 : STD_LOGIC; signal C1 : STD_LOGIC; signal C0 : STD_LOGIC; -- MSB of state machine -- middle bit of state machine -- LSB of state machine STATE_MACHINE_PROC: -- name is optional process ( SYS_RST_H, SYS_CLK_H ) is -- work when RST or CLK change if SYS_RST_H = '1' then -- if RESET asserted, then C2 <= '0'; -- set all state

17 C1 <= '0'; -- bits C0 <= '0'; -- to logic zero elsif RISING_EDGE ( SYS_CLK_H ) then -- else check clock low-to-hi -- the three equations below -- are derived directly from the -- equations for state machine C2 <= ( C2 and not C1 and not C0 and not D_H ) or ( not C2 and C1 and D_H ) or ( C1 and C0 ); C1 <= ( not C2 and not C1 and C0 and D_H ) or ( C2 and not C1 and not C0 and not D_H ) or ( C2 and C1 and D_H ); C0 <= ( not C2 and not C1 and not C0 and not D_H ) or ( C2 and C0 and not D_H ) or ( C1 and C0 and not D_H ) or ( C2 and C1 ); end process; -- end of action check -- end of present state reg process -- the only output occurs in state 5, which is done -- here with logic equation, in keeping with other scheme OUT_VAL_H <= C2 and not C1 and C0; end architecture EQUATIONS; If the basic building blocks that the designer has available for the system are registers and gates, then this method of generating and representing the system makes sense. However, there are others ways to accomplish the same thing creating a system whose behavior is represented by the state diagram shown above. One comment that could be made at this time concerns the design process itself. The designer has the responsibility of creating a system with the desired behavior, but also doing so in such a way that other criteria are also satisfied. Generally, the other criteria have something to do with the technology being used do implement the system, and also, either directly or indirectly, the costs involved in the system. In the system described above, the state was represented as a three bit thing minimizing the number of flip-flops needed to represent the state itself. This method of assigning the state values comes from a time when flip-flops were very expensive, either in purchase price, board space, or some other way of measuring costs. But what if flip-flops were very inexpensive? How might the process be changed? One answer to the question just posed is to represent the states in a different way. At the left is a version of the state diagram in which the states are not represented by a binary pattern, but rather by a name, and the names range from S0 to S6. Now the designer is free to utilize any scheme that is appropriate for the representation of the state. One method that is used extensively for this is called the One-Hot method. This scheme calls for each state to be represented by a single flip-flop, and then the state of the system is identified by the flip-flop that is set (contains a 1 ). In the design of the system, care is taken to make sure that only one flip-flop at a time can be asserted. Hence the name one hot. So, although seven flip-flops would be used to represent this system,

18 only one of the seven will be asserted at a time. Schematically, this is quite easy to represent. One logic system for the state machine shown here is: Note that this diagram shows the correlation between the state diagram and the logic used to implement that state diagram. Each transition in the state diagram has a corresponding gate in the logic. Since there is single input bit, each of the AND functions in the logic diagram corresponds to a state transition in the state diagram. (If, for example, a state diagram had a transition from Sx to Sy always no condition involved then there would not be an ANDing function involved in that state transition.) For example, the final AND gate in the diagram above is used for the transition to S6. The AND condition is: if the system is in state S5 (S5_H asserted), AND the data is low (D_L will then be high), then the system will transition to S6 after the active edge of the clock. There are similar correlations between the transitions identified in the state diagram and the logic in the diagram. There are two things missing in the logic diagram shown above. One is the assertion of the output. This will occur in state S6, and hence S6 is the logical output. The other thing that is missing from the diagram is an indication of what the system should do on

19 reset. The reset activity should clear all flip-flops except S0, which should be forced to a 1 condition. This will force the system to state S0. The logic shown on the previous page is also very easy to implement in VHDL: library IEEE; use IEEE.STD_LOGIC_1164.all; entity ONE_HOT is port ( SYS_RST_H : in STD_LOGIC; -- Force system to idle SYS_CLK_H : in STD_LOGIC; -- the clock line D_H : in STD_LOGIC; -- input data OUT_VAL_H : out STD_LOGIC -- output signal ); end entity ONE_HOT; architecture BEHAVIORAL of ONE_HOT is signal S0 : STD_LOGIC; signal S1 : STD_LOGIC; signal S2 : STD_LOGIC; signal S3 : STD_LOGIC; signal S4 : STD_LOGIC; signal S5 : STD_LOGIC; signal S6 : STD_LOGIC; -- Bit for state S0 -- Bit for state S1 -- Bit for state S2 -- Bit for state S3 -- Bit for state S4 -- Bit for state S5 -- Bit for state S6 ONE_HOT_PROC: -- name is optional process ( SYS_RST_H, SYS_CLK_H ) is -- work when RST or CLK change if SYS_RST_H = '1' then -- if RESET asserted, then S0 <= '1'; -- Set S0 to 1 S1 <= '0'; -- and all the S2 <= '0'; -- other state S3 <= '0'; -- bits to zero S4 <= '0'; S5 <= '0'; S6 <= '0'; elsif RISING_EDGE ( SYS_CLK_H ) then -- else check clock low-to-hi if ( S0 = '1' and D_H = '1' ) or -- in state 0, with D=1 ( S1 = '1' and D_H = '0' ) or -- in state 1, with D=0 ( S2 = '1' and D_H = '0' ) or -- in state 2, with D=0 ( S3 = '1' and D_H = '1' ) or -- in state 3, with D=1 ( S6 = '1' and D_H = '1' ) then -- in state 6, with D=1 S0 <= '1'; -- next state is S0 else -- otherwise, S0 <= '0'; -- next state is NOT S0 if ( S0 = '1' and D_H = '0' ) or -- in state 0, with D=0 ( S4 = '1' and D_H = '0' ) or -- in state 4, with D=0 ( S6 = '1' and D_H = '0' ) then -- in state 6, with D=0 S1 <= '1'; -- next state is S1 else -- otherwise, S1 <= '0'; -- next state is NOT S1 if S1 = '1' and D_H = '1' then -- in state 1, with D=1 S2 <= '1'; -- next state is S2 else -- otherwise,

20 S2 <= '0'; -- next state is NOT S2 if ( S2 = '1' and D_H = '1' ) or -- in state 2, with D=1 ( S5 = '1' and D_H = '1' ) then -- in state 5, with D=1 S3 <= '1'; -- next state is S3 else -- otherwise, S3 <= '0'; -- next state is NOT S3 if S3 = '1' and D_H = '0' then -- in state 3, with D=0 S4 <= '1'; -- next state is S4 else -- otherwise, S4 <= '0'; -- next state is NOT S4 if S4 = '1' and D_H = '1' then -- in state 4, with D=1 S5 <= '1'; -- next state is S5 else -- otherwise, S5 <= '0'; -- next state is NOT S5 if S5 = '1' and D_H = '0' then -- in state 5, with D=0 S6 <= '1'; -- next state is S6 else -- otherwise, S6 <= '0'; -- next state is NOT S6 end process; -- end of action check -- end of present state reg process -- the only output occurs in S6 OUT_VAL_H <= S6; end architecture BEHAVIORAL; In the VHDL above, each of the if-then-else constructs in the section after checking the rising edge specifies one more flip-flop in the one-hot scheme. This technique is very simple to implement with either the logic of the gating system shown above or the corresponding VHDL version. The common thread in the state machines and counter presented here is that the user identifies a number of states and then specifies the transitions between those states. Traditionally, the user identified the states with a bit string and designed the logic to make it work. Or, in the one-hot method, the user identified the state with a flip-flop and designed logic to cause the flip-flops to be asserted at the appropriate time. VHDL makes things easy by providing a mechanism for the user to identify legal states with a single construct. The basic idea is that the user creates a type that enumerates all possible elements. This is called an enumeration type, and has the following format: type STATE_TYPE is ( S0, S1, S2, S3, S4, S5, S6); signal PSR : STATE_TYPE; The first statement creates a new type, called in this case STATE_TYPE. The statement also allows the user to enumerate all possible members of this type (hence the name, enumeration type). In the statement, type and is are the keywords in the language, and the other names are up to the user. So, the syntax is: the keyword type, followed by the name the user wants to utilize for the type, followed by the keyword is, then an open parenthesis, then a comma-separated list of legal VHDL identifiers that enumerate all

21 possible elements of the type, and finally a close parenthesis and a semi-colon. This creates the type which the user can then utilize in the description of the system. The second statement instantiates one element of this type, and in this case gives it the name PSR. This appears here as a signal, which is the common way to do this: declare the signal in the declaration area of the architecture, and it will be visible to all of the other elements included in the architecture as needed. With these two statements, VHDL provides to the user a very easy way to specify the system by utilizing a case construct and specifying the desired behavior. For the simple system shown above, the alternative method of system specification is demonstrated by the following VHDL description: library IEEE; use IEEE.STD_LOGIC_1164.all; entity CASE_CON is port ( SYS_RST_H : in STD_LOGIC; -- Force system to idle SYS_CLK_H : in STD_LOGIC; -- the clock line D_H : in STD_LOGIC; -- input data OUT_VAL_H : out STD_LOGIC -- output signal ); end entity CASE_CON; architecture BEHAVIORAL of CASE_CON is -- define a type with 7 elements type STATE_TYPE is ( S0, S1, S2, S3, S4, S5, S6 ); signal PSR : STATE_TYPE; -- instantiate one element CASE_VERSION_PROC: -- name is optional process ( SYS_RST_H, SYS_CLK_H ) is -- work when RST or CLK change if SYS_RST_H = '1' then -- if RESET asserted, then PSR <= S0; -- force system to state S0 elsif RISING_EDGE ( SYS_CLK_H ) then -- else check clock low-to-hi case PSR is when S0 => -- if current state is S0 if D_H = '0' then -- if data is zero, then PSR <= S1; -- go to state S1 else -- otherwise, PSR <= S0; -- stay in state S0 when S1 => if D_H = '1' then PSR <= S2; else PSR <= S0; when S2 => if D_H = '1' then PSR <= S3; else PSR <= S0; when S3 => -- if current state is S1 -- if data is one, then -- go to state S2 -- otherwise, -- return to state S0 -- if current state is S2 -- if data is one, then -- go to state S3 -- otherwise, -- return to state S0 -- if current state is S3

22 if D_H = '0' then -- if data is zero, then PSR <= S4; -- go to state S4 else -- otherwise, PSR <= S0; -- return to state S0 when S4 => if D_H = '1' then PSR <= S5; else PSR <= S1; when S5 => if D_H = '0' then PSR <= S6; else PSR <= S3; when S6 => if D_H = '1' then PSR <= S0; else PSR <= S1; end case; end process; -- if current state is S4 -- if data is one, then -- go to state S5 -- otherwise, -- return to state S1 -- if current state is S5 -- if data is zero, then -- go to state S6 -- otherwise, -- return to state S3 -- if current state is S6 -- if data is one, then -- go to state S0 -- otherwise, -- go to state S1 -- end of clock check -- end of present state reg process -- the only output occurs in S6 OUT_VAL_H <= '1' when PSR = S6 else '0'; end architecture BEHAVIORAL; Note the natural way that the user can specify the state machine. With the enumeration type the user specifies all of the states in the system. Then, with the register construct (the process statement with the edge check...) the user creates a present-state register, and finally with the case construct the user identifies the transitions involved in the state machine. The user has not identified the implementation method classical, one-hot, or any other scheme that may be appropriate. Hence, the compiler utilized in generating a physical system from the VHDL is free to choose the type of implementation that is most appropriate, based on the metrics of interest as prioritized by the user. Now that we have described the basic technique and where it originated, let s go ahead and make something a little more complicated. For this example, we want to demonstrate the activities associated with one approach to creating a floating point divide. This method uses the Newton-Raphson iteration method to come to a final answer. The technique can be pipelined in order to provide very high speed functionality, but doing so utilizes many system resources, since multipliers are part of the method. But first, how dies this work? More details can be determined by finding a good reference for computer arithmetic. But the basic idea is to utilize high speed multipliers to generate the final answer. The method assumes that, given values A and B (some restrictions on the values), to form A/B the following block diagram identifies the operations to create the answer:

23 This particular block diagram shows four iterations; the actual number of iterations is determined by the user based on the number of correct bits needed in the answer. Since this mechanism follows the Newton-Raphson method of doing things, the number of correct bits doubles at every iteration. If more bits are needed, such as for double precision, then more iterations are needed. Anyway, to do the work as shown above, many multipliers (seven, in the figure) are needed. Or, if the task is to do the work with a single multiplier, then a different approach is needed. In this case, we will be using a multiplier that is synchronous and requires a cycle to do its work. Also, the inputs are only sampled when the enable is asserted. That way, if the multiplier is not being used it will not utilize as much power as it would when it is working. The timing for the multiplier is: Therefore, in order to get the multiplier to function as it should, the input values are presented in one cycle, along with the assertion of the enable line, and two clocks later the multiply out is available for the system to use. The other tricky part, one that is not indicated in the above timing diagram, is that the multiplier is piplined. That is, the result of a multiply started at the end of cycle 4 will be available at the end of cycle 6, but it is also possible to start a different multiply at the end of cycle 5, and the results of this second multiply will be available at the end of cycle 7. Thus, the two different calculations will overlap in the hardware itself. This multiplier is then used in the following fashion:

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