Virtual Memory: Policies. CS439: Principles of Computer Systems March 5, 2018

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1 Virtual Memory: Policies CS439: Principles of Computer Systems March 5, 28

2 Last Time Overlays Paging Pages Page frames Address translation

3 Today s Agenda Paging: Mechanisms Page Tales Page Faults Paging: Policy Demand paging vs. pre-paging Page Replacement Algorithms Gloal vs. local Page Sizes Multiprogramming Swap

4 Address Translation: Current Picture P s Virtual Address Space (4,) (3,23) 5 p This is a picture. Text description on next slide. A system with 6-it addresses Ø 32 KB of physical memory Ø 24 yte pages CPU 9 Virtual Addresses o f 4 9 Physical Addresses o (4,23) Physical Memory Page Tale (,)

5 Virtual Address Translation: Text Description Steps to Virtual-Physical Memory Translation: The program gives a virtual address to the CPU to translate The MMU splits the virtual address into its page and offset numers Since the offset is the same in Virtual and Physical memory it is sent along with no change The page numer is translated into a frame numer Look into page tale to find out if page exists in physical memory The page numer is the index of the correct entry in the page tale (much like indexing an array) If the page exists in memory the frame numer is sent along If it doesn t exist in memory ut exists on disk, the corresponding page is moved from disk into physical memory and its frame numer is recorded Append offset to end of frame numer to get the full physical address

6 Performance Issues: Speed Prolem: Virtual memory references require two memory references! One access to get the page tale entry One access to get the data

7 Back to Architecture: Text Description There is a system us that connects to the CPU, the Disk Controller, and the Memory Controller. It controls the flow of information etween them. The Disk Controller connects to disks and allows the System Bus to interface with them. It creates the astraction etween the system and the disk hardware. The Memory Controller connects to memory and controls the astraction etween the system and the memory hardware. The System Bus interacts with the CPU: it gets a Physical Address from the TLB/MMU and sends/receives data from the Processor and/or Cache. The TLB (Translation Lookaside Buffer)/ MMU (Memory Management Unit) are an intermediary etween the System Bus and Processor for Physical Addresses. The Processor sends Virtual Addresses to the TLB/MMU, they are translated into physical addresses and then sent along the System Bus. The TLB is a cache for these translations, as we will see next.

8 Improving Speed: Translation Lookaside Buffers (TLBs) CPU This is a picture. Text desription on next slide. Cache recently accessed page-to-frame translations in a TLB For TLB hit, physical page numer otained in cycle For TLB miss, translation is updated in TLB Has high hit ratio (why?) Physical Addresses f 6 9 o p 2 9 o Virtual Addresses? Key Value p f f TLB X p Page Tale

9 Improving Speed: Translation Lookaside Buffers (TLBs) Text Description The TLB adds an extra step to getting a frame numer from a page numer. The TLB holds recently used frame/page pairings. TLBs have high hit ratio ecause they exploit locality within the system For a TLB hit, the translation can e completed in cycle The system simultaneously sends the page numer to oth the TLB and the page tale looking for a frame numer. If there is a hit in the TLB then it stops looking in the page tale and sends the frame numer along. If there is a miss in the TLB then it finds the frame numer in the page tale, sends the frame numer along, and updates the TLB.

10 Back to Architecture This is a picture. Text description next slide. Translation Lookaside Buffer/Memory Management Unit

11 Performance Issues: Space Two sources: data structure overhead (the page tale) fragmentation (How large should a page e?) Page tale can e very large! 32-it addresses, 496-yte pages million pages! 32-it addresses imply a VAS of 2^32 ytes Divide VAS into pages (2^32/2^2) million pages (2^2)

12 Dealing With Large Page Tales: Multi-Level Paging This is a picture. Text description on next slide. Add additional levels of indirection to p the page tale y su-dividing page numer into k parts Create a tree of page tales TLB still used, just not shown The architecture determines the numer of levels of page tale p 2 Virtual Address o p 3 Second-Level Page Tales p 2 p 3 p First-Level Page Tale Third-Level Page Tales

13 Dealing with Large Page Tales: Multi-Level Paging Text Description Add additional levels of indirection to the page tale y sudividing page numer into k parts. This creates a k-depth tree of page tales. The architecture of the system determines k. Example: A system with 3 levels of page tales: There are 3 its for the first level page tale There are 4 its for the second level page tale There are 5 its for the third level page tale Note that if this were a single-level paged system, there would e 2 (3+4+5) its for the page numer Each entry in the first level page tale points to a second level page tale, and each entry in the second level page tale points to a third level page tale. The third level page tale entries actually hold the it/frame numer information that is usually associated with a page tale entry. Multi-Level page tales save space ecause you only have to allocate space for the page-tale levels that you need. For example if you insanely only needed to hold information for page tale entry you would only need one first level page tale, one second level tale and one third level page tale. It is important to note that you will always have only one first level page tale.

14 Multi-Level Paging: Example This is a picture. Text description on next slide. Example: Two-level paging CPU Memory p p o Virtual Addresses Physical Addresses f 6 o PTBR + page tale + f p p 2 First-Level Page Tale Second-Level Page Tale

15 Multi-Level Paging: Example Text Description This example has two-level paging The first 3 its are for the first level page tale. The value of these its is added to the PTBR (Page Tale Base Register) which points to the eginning of the first level page tale. The next 4 its are for the second level page tale. From the first level page tale entry we get the address of the eginning of the second level page tale, then we add the value from the secondlevel its in the virtual address to this address. This gives us the address of the corresponding page tale entry in the second level page tale. Now we can access the relevant its and frame numer from the right second level page tale entry. The TLB is very important now ecause each lookup from the page tale requires a 2 step look up instead of just a single step.

16 64-it Addresses Multi-level page tales work decently well for 32- it address spaces ut what happens when we get to 64-it? Too cumersome (5 levels?) Rethink the page tale: Instead of making tales proportional to the size of the VAS, make them proportional to the size of the physical address space One entry for each physical page---and hash! Result: Hashed/Inverted Page tales

17 Inverted Page Tales Each frame is associated with an entry Entry contains: Residence it: is the frame occupied? Occupier: page numer of the page in the frame Protection its

18 Inverted Page Tales: Virtual Address Translation As the CPU generates virtual addresses, where is the physical page? Must search entire page tale (32KB of Registers!) Uh-Oh How can we solve that prolem? Cache it! (How did you know?) Use the TLB to hold all the heavily used pages But, um the TLB is limited in size So what aout a miss in the TLB?

19 Use a Hash Tale! Page i is placed in slot f(i) where f is an agreed-upon hash function Deal with collisions using linked list or rehashing To look up page i, perform the following: Compute f(i) and use it as an index into the tale of page entries Extract the corresponding page entry

20 Hashed Inverted Tale In Use Hash page numers to find corresponding frame numer Page frame numer is not explicitly stored ( frame per entry) Protection, dirty, used, resident its also in entry 2 9 CPU p o Virtual Address PID running Physical Addresses f 6 9 Memory o Hash =? =? tag check PTBR + PID page f max f max 2 h(pid, p) Inverted Page Tale

21 Hashed Inverted Tale In Use: Text Description Hash page numers to find corresponding frame numer page frame numer is not explicitly stored ( frame per entry) protection, dirty, used, and resident its also in entry The hash function takes in the PID of the process and the page numer. The answer from this hash function is added to the PTBR to get the address of the right page tale entry. Once at the right page tale entry the PID and page numer saved in the entry are checked against the given PID and page numer. If they do not match, then the frame isn t holding information for that page and it needs to e swapped in. If they do match then the right frame has een found and the frame numer is sent along.

22 iclicker Question Why use hashed/inverted page tales? A. Regular (forward-mapped) page tales are too slow B. Forward-mapped page tales don t scale to larger virtual address spaces C. Inverted page tales have a simpler lookup algorithm, so the hardware that implements them is simpler D. Inverted page tales allow a virtual page to e anywhere in physical memory

23 This slide is a picture. Text description next slide.

24 The BIG Picture (): Text Description The CPU generates virtual addresses The address is translated into a physical address The physical address is used to reference memory

25

26 The BIG Picture (2): Text Description The CPU generates a virtual address That virtual address is used to reference a virtually addressed cache. If there s a match, we re finished If there is no match, the address is used to access the TLB, if there is a match, then the resulting physical address is used to access the physically addressed cache. If no match, then the translation must from from the page tale, which is located using the Page Tale Base Register (PTBR) and then indexed using the page numer. The resulting frame numer is comined with the offset and used to access the physically addressed cache. If there is a match in the physically addressed cache, we re finished. Otherwise, the physical address is used to access main memory.

27 Virtual Memory: The Bigger Picture A process s VAS is part of its context Contains its code, data, and stack Code pages are stored in a user s file on disk Some are currently residing in memory; most are not Data and stack pages are also stored in a file Although this file is typically not visile to users File only exists while a program is executing OS determines which portions of a process s VAS are mapped in memory at any one time Code Data Stack File System (Disk) OS/MMU Physical Memory

28 Page Faults Physical Memory References to non-mapped pages generate a page fault CPU Page fault handling steps: Processor runs the interrupt handler OS locks the running process OS starts read of the unmapped page OS resumes/initiates some other process Read of page completes OS maps the missing page into memory OS restarts the faulting process Page Tale Program P s VAS Disk

29 Paging: The Policy When should a process s pages e loaded into memory? If memory is full ut a page fault has just occurred (so a process needs another page!), what should happen? If a page should e replaced, which one? What is a good page size? How many processes are too many?

30 When to Load a Page? Demand paging: OS loads a page the first time it is referenced Pre-paging: OS guesses in advance which pages the process will need and pre-loads them

31 Initializing Memory: Pre-Paging with a TLB. A process needing k pages arrives 2. The OS allocates all k pages to the free frames. The OS puts each page in a frame The OS updates the entries in the page tale 3. OS marks all TLB entries as invalid (flushes the TLB). 4. OS starts a process 5. As process executes, OS loads TLB entries as each page is accessed, replacing an existing entry if the TLB is full.

32 Initializing Memory: Demand Paging with a TLB. A process arrives 2. The OS stores the process s VAS on disk and does not put any of it into memory 3. OS marks all TLB entries as invalid (flushes the TLB). 4. OS starts the process 5. As process executes:. Pages are faulted in as they are needed The OS puts each page in a frame The OS updates the entries in the page tale 2. OS loads TLB entries as each page is accessed, replacing an existing entry if the TLB is full.

33 Performance of Demand Paging Theoretically, a process could access a new page of memory with each instruction (expensive!) But processes tend to exhiit locality of reference temporal locality: if a process accesses an item in memory, it will tend to reference the same item again soon spatial locality: if a process accesses an item in memory, it will tend to reference an adjacent item soon

34 What happens when we have a page fault. ut memory is full? The OS:. selects a page to replace (page replacement algorithm) 2. invalidates the old page in the page tale 3. starts loading the new page into memory from disk 4. context switches to another process while I/O is eing done 5. gets interrupt that the page is loaded in memory 6. updates the page tale entry 7. continues faulting process

35 Page Replacement Algorithms: Goals Improve OS performance y: Reducing the frequency of page faults Being efficient Overarching goal: Make good decisions quickly

36 Page Replacement Algorithms: FIFO First-In, First-Out Throw out the oldest page Simple to implement OS can easily throw out a page that is eing accessed frequently

37 FIFO Replacement This slide is a picture. Text description next slide. Implemented with a single pointer Performance with 4 page frames: 3 2 Frame List Physical Memory Time Requests Page Frames Faults 2 3 a c d c a d e a c d 37

38 FIFO Replacement: Text Description Implemented with a single pointer pointer points to the oldest page Performance with 4 page frames: keep track of time and requests made at each time requests denoted with letters (a,, c etc) time shown on the x-axis page frames kept track on the y-axis keep count of faults as you go At time, pages a,, c, and d are loaded into frames,, 2, and 3 respectively. The request string is c, a, d,, e,, a,, c, d. Each request occurs at another time tick, so requests are at times -.

39 FIFO Replacement: Solution This slide is a picture. Text description next slide. Implemented with a single pointer Performance with 4 page frames: 3 2 Frame List Physical Memory Time Requests Page Frames 2 3 a c d c a d e a c d a a a a e e e e e d a a a a c c c c c c c d d d d d d d d c c Faults 39

40 FIFO Replacement: Solution Text Description Performance with 4 page frames and requests: single letters denote virtual pages Time : a in frame, in frame, c in frame 2 and d in frame 3 oldest page is a Time : request page c, already in memory so no fault Time 2: request page a, already in memory so no fault Time 3: request page d, already in memory so no fault Time 4: request page, already in memory so no fault Time 5: request page e which isn t in memory, causes a page fault puts e where a used to e since a was the oldest page in memory new frame setup: e in frame, in frame, c in frame 2 and d in frame 3 new oldest page is Time 6: request page, already in memory so no fault Time 7: request page a which isn t in memory, causes a page fault puts a where used to e since was the oldest page in memory new frame setup: e in frame, a in frame, c in frame 2 and d in frame 3 new oldest page is c Time 8: request page which isn t in memory, causes a page fault puts where c used to e since was the oldest page in memory new frame setup: e in frame, a in frame, in frame 2 and d in frame 3 new oldest page is d Time 9: request page c which isn t in memory, causes a page fault puts c where d used to e since d was the oldest page in memory new frame setup: e in frame, a in frame, in frame 2 and c in frame 3 new oldest page is e Time : request page d which isn t in memory, causes a page fault puts d where e used to e since e was the oldest page in memory final frame setup: d in frame, a in frame, in frame 2 and c in frame 3 Total numer of page faults: 5

41 Page Replacement Algorithms: Optimal Look into the future and throw out the page that will e accessed farthest in the future Provaly optimal

42 Optimal Page Replacement Clairvoyant replacement This slide is a picture. Text description next slide. Replace the page that won t e needed for the longest time in the future Time Requests c a d e a c d Page Frames 2 3 a c d Faults Time page needed next 42

43 Optimal Page Replacement: Text Description Clairvoyant replacement---impossile in real life Replace the page that won t e needed for the longest time in the future Time and requests on x axis Page frames on the y axis Keep track of faults as you go At time, pages a,, c, and d are loaded into frames,, 2, and 3 respectively. The request string is c, a, d,, e,, a,, c, d. Each request occurs at another time tick, so requests are at times -.

44 Optimal Page Replacement: Solution Clairvoyant replacement slide is a picture. Text description next slide. Replace the page that won t e needed for the longest time in the future Time Requests c a d e a c d Page Frames 2 3 a c d a a a a a a a a a d c c c c c c c c c c d d d d e e e e e e Faults Time page needed next a = 7 = 6 c = 9 d = a = 5 = c = 3 d = 4 44

45 Optimal Page Replacement: Solution Text Description Performance with 4 frames and requests: request order: c a d e a c d we will keep this order in mind as we run the algorithm Time : a in frame, in frame, c in frame 2 and d in frame 3 Time : request page c, in memory so no page fault Time 2: request page a, in memory so no page fault Time 3: request page d, in memory so no page fault Time 4: request page, in memory so no page fault Time 5: request page e which isn t in memory, causes a page fault look at future requests: a c d, see that d is the one farthest in the future put e where d used to e current frame setup: a in frame, in frame, c in frame 2 and e in frame 3 Time 6: request page, in memory so no page fault Time 7: request page a, in memory so no page fault Time 8: request page, in memory so no page fault Time 9: request page c, in memory so no page fault Time : request page d which isn t in memory, causes a page fault don t have any future requests so just pick something to kick out put d where a used to e final frame setup: d in frame, in frame, c in frame 2 and e in frame 3 Total numer of page faults: 2

46 Page Replacement Algorithms: LRU Least Recently Used Approximation of optimal that works well when the recent past is a good predictor of the future Throw out the page that has not een used in the longest time

47 Least Recently Used Page Replacement Use the recent past as a predictor of the near future This is a picture. Text description next slide. Replace the page that hasn t een referenced for the longest time Time Requests Page Frames Faults 2 3 Time page last used a c d c a d e a c d 47

48 Least Recently Used Page Replacement Algorithm: Text Description Use the recent past as a predictor of the near future Replace the page that hasn t een referenced for the longest time Time and requests on x axis Page frames on the y axis Keep track of faults as you go At time, pages a,, c, and d are loaded into frames,, 2, and 3 respectively. The request string is c, a, d,, e,, a,, c, d. Each request occurs at another time tick, so requests are at times -.

49 Least Recently Used Page Replacement: Solution Use the recent past as a predictor of the near futurethis is a picture. Text description next slide. Replace the page that hasn t een referenced for the longest time Time Requests Page Frames 2 3 a c d c a d e a c d a a a a a a a a a a c c c c e e e e e d d d d d d d d d c c Faults Time page last used a = 2 = 4 c = d = 3 a = 7 = 8 e = 5 d = 3 a = 7 = 8 e = 5 c = 9 49

50 Least Recently Used Page Replacement: Solution Text Description Performance with 4 frames and requests: request order: c a d e a c d Time : a in frame, in frame, c in frame 2 and d in frame 3 Time : request page c, in memory so no page fault Time 2: request page a, in memory so no page fault Time 3: request page, in memory so no page fault Time 4: request page d, in memory so no page fault Time 5: request page e which isn t in memory, causes a page fault look ack in time and see that c was used least recently past requests: a used at time 2, used at time 4, c used at time and d used at time 3 put e where c used to e current frame setup: a in frame, in frame, e in frame 2 and d in frame 3 Time 6: request page, in memory so no page fault Time 7: request page a, in memory so no page fault Time 8: request page, in memory so no page fault Time 9: request page c which isn t in memory, causes a page fault look ack in time and see that d was used least recently past requests: a used at time 7, used at time 8, e used at time 5 and d used at time 3 put c where d used to e current frame setup: a in frame, in frame, e in frame 2 and c in frame 3 Time : request page d which isn t in memory, causes a page fault look ack in time and see that e was used least recently past requests: a used at time 7, used at time 8, e used at time 5 and c used at time 9 put d where e used to e current frame setup: a in frame, in frame, d in frame 2 and c in frame 3 NOTE: replaced d and had to immediately ring it ack in. So the past is not a perfect prediction of the future Total numer of page faults: 3

51 Implementing LRU Option : keep a time stamp for each page representing the last access Prolem: OS must record time stamp for each memory access and search all pages to find one to toss Option 2: keep a list of pages, where the front of the list is the most recently used and the end is the least recently used. Move page to front on access. Douly link the list. Prolem: Still too expensive, since OS must modify up to 6 pointers on memory access

52 iclicker Question What is the goal of a page replacement algorithm? A. Reduce the numer of page faults B. Reduce the penalty for page faults when they do occur C. Minimize CPU time for a process

53 Approximating LRU: Clock Maintain a circular list of pages in memory Maintain pointer (clock hand) to oldest page Before replacing a page, check its reference it Rememer the reference/clock it? It tracks whether the page was referenced recently If the reference it is (was referenced recently), clear it and then check next page How does this algorithm terminate?

54 Clock This slide is text followed y a picture. Text description next slide. Clock hand points to oldest page Clock hand sweeps over pages looking for one with reference it = Replace pages that haven t een referenced for one complete revolution of the clock resident it reference it frame numer Page 7: Page : 5 Page 4: 3 Page 3: Page : 4 func Clock_Replacement egin while (victim page not found) do if(reference it for cur page = ) then replace current page else reset reference it advance clock pointer end while end Clock_Replacement

55 Clock: Text Description Pages are arranged in a (logical) circle Each page around the clock face keeps track of 3 its: resident, reference and frame numer Clock hand points to the oldest page Clock hand sweeps over pages looking for one with reference it that is Replace pages that haven t een referenced for one complete revolution of the clock Pseudocode for algorithm: func clock_replacement egin while(victim page not found) do if(reference it for current page is ) then» replace current page else» reset reference it advance clock pointer end while end clock_replacement Can e implemented with a circular list of all resident pages from the page tale Is an approximation of the LRU algorithm

56 56 d c a c Clock Page Replacement Example This slide is a picture. Text description next slide. Faults Page Frames 2 3 a c d Requests Time Page tale entries for resident pages: d c a a 2 d c a d 3 d c a 4 e 5 6 a 7 8 c 9 d e c d e c d e a d e a d e a c d a c a c d

57 Clock Page Replacement: Example Text Description Same setup as earlier examples Time and requests on x axis Page frames on the y axis Keep track of faults as you go At time, pages a,, c, and d are loaded into frames,, 2, and 3 respectively. The request string is c, a, d,, e,, a,, c, d. Each request occurs at another time tick, so requests are at times -. In earlier examples, we learned that no page replacements were necessary until time 5, so this example starts at time 5.

58 58 d c a c Clock Page Replacement Example: Solution This slide is a picture. Text description next slide. Faults Page Frames 2 3 a c d Requests Time Page tale entries for resident pages: d c a a 2 d c a d 3 d c a 4 d c e e 5 d c e 6 d a e a 7 d a e 8 c a e c 9 c a d d e c d e c d e a d e a d e a c d a c a c d

59 Clock Page Replacement Example Solution: Text Description ( of 2) Performance with 4 frames and requests: Time : a in frame, in frame, c in frame 2 and d in frame 3 clock pointer at frame Time : request page c, in memory so no page fault update reference it to e Time 2: request page a, in memory so no page fault update reference it to e Time 3: request page, in memory so no page fault update reference it to e Time 4: request page d, in memory so no page fault update reference it to e Time 5: request page e which isn t in memory, causes a page fault have to run the clock algorithm frame (a) has reference it of one, clear it and move pointer to frame frame () has reference it of one, clear it and move pointer to frame 2 frame 2 (c ) has reference it of one, clear it and move pointer to frame 3 frame 3 (d) has reference it of one, clear it and move pointer ack to frame since we cleared all the its as we went frame now has a reference it of zero, this is the page to replace put e in frame and move pointer to frame current frame setup: e in frame, in frame, c in frame 2 and d in frame 3

60 Clock Page Replacement Example Solution: Text Description (2 of 2) Time 6: request page which is in memory, no page fault frame s reference it is set to one since it holds page Time 7: request page a which isn t in memory, causes a page fault have to run the clock algorithm frame () has reference it of one, clear it and move pointer to frame 2 frame 2 (c ) has reference it of zero, this is the page to replace put a in frame 2 and move pointer to frame 3 current frame setup: e in frame, in frame, a in frame 2 and d in frame 3 Time 8: request page, in memory so no page fault update reference it to e Time 9: request page c which isn t in memory, causes a page fault have to run clock algorithm frame 3 (d) has reference it of zero, this is the page to replace put d in frame 3 and move pointer to frame current frame setup: e in frame, in frame, a in frame 2 and c in frame 3 Time : request page d which isn t in memory, causes a page fault have to run clock algorithm frame (e) has reference it of one, clear it and move to frame frame () has reference it of one, clear it and move to frame 2 frame 2 (a) has reference it of one, clear it and move to frame 3 frame 3 (c) has reference it of one, clear it and move to frame since we cleared all the its as we went frame now has a reference it of zero, this is the page to replace put d in frame and move pointer to frame final memory setup: d in frame, in frame, a in frame 2 and c in frame 3 total numer of page faults: 4

61 Second Chance Cheaper to replace a page that has not een written since it need not e written ack to disk Check oth the reference it and modify it to determine which page to replace (reference, modify) pairs form classes: (,): not used or modified, replace! (,): not recently used ut modified: OS needs to write, ut may not e needed anymore (,): recently used and unmodified: may e needed again soon, ut doesn t need to e written (,): recently used and modified On page fault, OS searches for page in the lowest nonempty class

62 Second Chance Implementation The OS goes around at most three times searching for the (,) class:. If the OS finds (,) it replaces that page 2. If the OS finds (,) it initiates an I/O to write that page, locks the page in memory until the I/O completes, clears the modified it, and continues the search in parallel with the I/O 3. For pages with the reference it set, the reference it is cleared 4. On second pass (no page (,) found on first), pages that were (,) or (,) may have changed

63 Second Chance Implementation (another option) The OS goes around at most three times searching for the (,) class:. If the OS finds (,) it replaces that page 2. If the OS finds (,), clear dirty it and move on, ut rememer page is dirty. Write only if evicted. 3. For pages with the reference it set, the reference it is cleared 4. On second pass (no page (,) found on first), pages that were (,) or (,) may have changed

64 Optimizing Approximate LRU Replacement The Second Chance Algorithm This slide is a picture. Text description next slide. There is a significant cost to replacing dirty pages Modify the Clock algorithm to allow dirty pages to always survive one sweep of the clock hand Ø Use oth the dirty it and the used it to drive replacement resident it used it dirty it Page 7: Page : 5 Page 4: 3 Page 3: 9 Page : 4 Second Chance Algorithm Before clock sweep used dirty After clock sweep used dirty replace page 64

65 The Second Chance Algorithm: Text Description There is a significant cost to replacing dirty pages Modify the clock algorithm to allow dirty pages to always survive one sweep of the clock hand Use oth the dirty it and the used it to drive replacement When a page is referenced the reference it is set If the page was modified, aka written to, the dirty it is set During first sweep of the hand the used it is cleared During second sweep of the hand the dirty it is cleared Assumption: OS rememers that the pages is really dirty Only replace pages that have oth dirty and used it equal to zero So if a page is dirty have to wait full 2 sweeps for it to e replaced

66 Local vs. Gloal Page Replacement Local page replacement algorithms only consider the pages owned y the faulting process Essentially a fixed numer of pages per process Gloal page replacement algorithms consider all the pages

67 Local Page Replacement How much physical memory do we allocate to a process? This slide is a picture. Text description on next slide. Time Requests a c d a c d a c d Page Frames 2 a c Faults Page Frames 2 3 a c Faults 67

68 Local Page Replacement: Text Description Two examples, one slide For oth: Time and requests on x axis Page frames on the y axis Keep track of faults as you go The request string is a,, c, d, a,, c, d, a,, c, d. Each request occurs at another time tick, so requests are at times -2 Example : 3 page frames At time, pages a,, and c are loaded into frames,, and 2 respectively. Example 2: 4 page frames At time, pages a,, and c are loaded into frames,, and 2 respectively. Frame 3 is empty.

69 Local Page Replacement How much physical memory do we allocate to a process? (Solution)This slide is a picture. Text description on next slide. Time Requests a c d a c d a c d Page Frames 2 a c a a a d d d c c c a a a d d d c c c c c c c a a a d Faults a a a a a a a a a a a a a Page Frames 2 3 c c c c c c c c c c c c c d d d d d d d d d Faults 69

70 Local Page Replacement: Solution Text Description ( of 2) How much memory do we allocate to a process? Example with 3 page frames and 4 pages with FIFO replacement: reference order: a c d a c d a c d Time : a in frame, in frame and c in frame 2 Time : request page a, in memory so no page fault Time 2: request page, in memory so no page fault Time 3: request page c, in memory so no page fault Time 4: request page d which isn t in memory, causes a page fault put d where a used to e since a was the oldest page in memory current frame setup: d in frame, in frame and c in frame 2 Time 5: request page a which isn t in memory, causes a page fault put a where used to e since was the oldest page in memory current frame setup: d in frame, a in frame and c in frame 2 Time 6: request page which isn t in memory, causes a page fault put where c used to e since c was the oldest page in memory current frame setup: d in frame, a in frame and in frame 2 Time 7: request page c which isn t in memory, causes a page fault put c where d used to e since d was the oldest page in memory current frame setup: c in frame, a in frame and in frame 2 Time 8: request page d which isn t in memory, causes a page fault put d where a used to e since a is the oldest page in memory current frame setup: c in frame, d in frame and in frame 2

71 Local Page Replacement: Solution Text Description (2 of 2) Time 9: request page a which isn t in memory, causes a page fault put a where used to e since was the oldest page in memory current frame setup: c in frame, d in frame and a in frame 2 Time : request page which isn t in memory, causes a page fault put where c used to e since c was the oldest page current frame setup: in frame, d in frame and a in frame 2 Time : request page c which isn t in memory, causes a page fault put c where d used to e since d was the oldest page current frame setup: in frame, c in frame and a in frame 2 Time 2: request page d which isn t in memory, causes a page fault put d where a used to e since a was the oldest page final frame setup: in frame, c in frame and d in frame 2 Total numer of page faults: 9 page faulted on almost every request Example with 4 page frames and 4 frames and FIFO replacement reference order: a c d a c d a c d Time : a in frame, in frame, c in frame 2 and frame 3 is empty Time - 3: request pages a and c which are already in memory Time 4: request page d which isn t in memory, causes a page fault put d in the empty frame current frame setup: a in frame, in frame, c in frame 2 and d in frame 3 now all pages are resident in memory so the rest of the requests don t cause any page faults Total numer of page faults: These examples show that allocating too few frames to a process can cause a massive jump in the numer of page faults

72 So how much physical memory should we allocate to each process? A. 4 frames B. 8 frames C. % of the frames D. 5% of the frames E. It depends. Do we really want to decide this ahead of time? Do we really want a fixed numer per process? Does that make sense?

73 Is there another way? The Principle of Locality Recall: programs exhiit temporal and spatial locality 9% of execution is sequential Most iterative constructs consist of a relatively small numer of instructions When processing large data structures, the dominant cost is sequential processing on individual structure elements

74 Explicitly Using Locality: The Working Set Model The working set is: informally, the pages the process is using right now formally, the set of all pages that a process referenced in the last T seconds Assume that recently references pages are likely to e referenced again soon Only keep those pages in memory (the working set!) Pages may e removed even when no page fault occurs Numer of frames allocated to a process will vary over time Also allows pre-paging.

75 Working Set Page Replacement Implementation This slide is a picture. Text description next slide. Keep track of the last T references Ø The pages referenced during the last T memory accesses are the working set Ø T is called the window size Example: Working set computation, T = 4 references: Time Requests Pages in Process Faults Page a Page Page c Page d Page e t = - - t = 2 t = c c d c e c e a d 75

76 Working Set Page Replacement: Text Description Implementation of working set keep track of the last T references the pages referenced during the last T memory accesses are the working set T is called the window size Example: working set computation with T = 4 references Time and requests on x axis Pages (not frames) on the y axis Are keeping track of whether or not each page is in memory instead of keeping track of what each frame is holding also keep track of the age of each page in memory when a page ecomes 5 ticks old it is kicked out of memory Keep track of faults as you go Time : pages a, d and e in memory a is tick old, d is 2 ticks old and e is 3 ticks old The request string is c, c, d,, c, e, c, e, a, d. Each request occurs at another time tick, so requests are at times -.

77 Working Set Page Replacement Implementation Keep track of the last T references Ø The pages referenced during the last T memory accesses are the working set Ø T is called the window size Example: Working set computation, T = 4 references: Ø What if T is too small? too large? Time Requests Pages in Process Page a Page Page c Page d Page e t = - - t = 2 t = c c d c e c e a d F F F F F Faults 77

78 Working Set Page Replacement: Solution Text Description ( of 2) Example: working set computation with T = 4 references are keeping track of whether or not each page is in memory also keep track of the age of each page in memory when a page ecomes 5 ticks old it is kicked out of memory Time : pages a, d and e in memory a is tick old, d is 2 ticks old and e is 3 ticks old Time : page c is requested which isn t in memory, causes a page fault pages in memory: a, c, d and e Time 2: page c is requested, is in memory so no page fault Time 3: page d is requested, is in memory so no page fault at this time page e ecomes 5 ticks old so is kicked out of memory pages in memory: a, c and d Time 4: page is requested which isn t in memory, causes a page fault at this time page a ecomes 5 ticks old so is kicked out of memory pages in memory: c and d

79 Working Set Page Replacement: Solution Text Description (2 of 2) Time 5: page c is requested, is in memory so no page fault Time 6: page e is requested which isn t in memory, causes a page fault pages in memory: c d and e Time 7: page c is requested, is in memory so no page fault at this time page d ecomes 5 ticks old so is kicked out of memory pages in memory: c and e Time 8: page e is requested, is in memory os no page fault at this time page ecomes 5 ticks old so is kicked out of memory pages in memory: c and e Time 9: page a is requested which isn t in memory, causes a page fault pages in memory: a c and e Time : page d is requested which isn t in memory, causes a page fault pages in memory: a c d and e Total numer of page faults: 5

80 How do we choose the value of T? What if T is too ig? What if T is too small?

81 Thrashing Thrashing occurs when the memory is overcommitted and pages are tossed out while they are still in use Many memory references cause pages to e faulted in Very serious and very noticeale loss of performance How do we limit thrashing in a multiprogrammed system?

82 How do we choose the value of T? What if T is too ig? What if T is too small? page fault = ms ms = 2M instructions T needs to e a lot igger than 2 million instructions

83 Load Control Load control refers to the numer of processes that can reside in memory at one time Working set model provides implicit load control y only allowing a process to execute if its working set fits in memory BUT process frame allocations are variale What happens when the total numer of pages needed is greater than the numer of frames availale? Processes are swapped out to disk

84 Load Control This slide is a picture. Text description next slide. Ready Running Physical Memory suspended queue Suspended ready queue? Blocked semaphore/condition queues When the multiprogramming level should e decreased, which process should e swapped out? Lowest priority process? Smallest process? Largest process? Oldest process? Faulting process? Disk

85 Load Control: Text Description When a process is totally swapped out of memory it is put onto swap (aka the paging disk) Adds another stage to the process life cycle This new stage is called suspended We also saw this stage in relocation, when we also swapped out entire processes Can go from any of the other states to suspended Usually locked or ready Process can go from suspended to ready

86 Another Decision: Page Sizes Page sizes are growing slowly ut steadily. Why? Benefits for small pages: more effective memory use, higher degree of multiprogramming possile Benefits for large pages: smaller page tales, reduced I/O time, fewer page faults Growing ecause: memory is cheap---page tales could get huge with small pages and internal fragmentation is less of a concern CPU speed is increasing faster than disk speed, so page faults cause a larger slow down

87 iclicker Question Can an application modify its own translation tales (however they are implemented)? A. Yes B. No

88 Summary: Page Replacement Algorithms Unix and Linux use a variant of the second chance algorithm Windows NT uses FIFO replacement All algorithms do poorly on typical processes if processes have insufficient physical memory All algorithms approach optimal as the physical memory allocated to a process approaches virtual memory size The more processes running concurrently, the less physical memory each process can have

89 Summary: Paging We ve considered: Placement Strategies None needed, can place pages anywhere Replacement Strategies What to do when more jos exist than can fit in memory Load Control Strategies Determine how many jos can e in memory at one time

90 Summary: Paging The Good Eliminates the prolem of external fragmentation Allows sharing of memory pages amongst processes Enales processes to run when they are only partially loaded into main memory The Cost Translating from a virtual address to a physical address is time consuming Requires hardware support (TLB) to e decently efficient Requires more complex OS to maintain the page tale The expense of memory accesses and the flexiility of paging make paging cost effective.

91 Announcements Discussion sections on Friday! Prolem Set 6 is posted. Stack Check appointments today and tomorrow You should have received at your CS account telling you who to meet If you didn t, check that you didn t give me your EID If you haven t signed up, see me Project 2 due Friday, 3/23 You MUST get it working

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