A middle ground between CAMs and DAGs for high-speed packet classification

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1 A middle ground between CAMs and DAGs for high-speed packet classification Amit Prakash Adnan Aziz The University of Texas at Austin Abstract Packet classification is a computationally intensive task that routers need to perform at high speed to implement features such as QoS, access control, and VPNs. A classification rule-set consists of a prioritized set of rules, where each rule is a condition-action pair. Current approaches to classification can be categorized as belonging in one of two extreme categories: (1.) an incoming packet is fed to custom hardware which concurrently checks all rules for applicability and returns the action of the highest priority applicable rule; (2.) a graph-like data-structure is stored in memory and traversed based on the bits in the incoming packet s header. Both these approaches suffer from severe limitations: the former uses a large amount of hardware; the latter requires huge amounts of memory to achieve high performance. Our thesis is that the right approach to packet classification lies in the middle. Specifically, we describe an architecture with a small number of hardware-based rule evaluation units operating in parallel. We show that dividing the rule-set across these units so as to make them fit in the hardware available is NP-hard; our primary contribution is a heuristic for doing this division. 1 Introduction Fast packet classification is essential to implementing QoS, intrusion detection, per-flow accounting, and many other desirable services in networks. Packet classification on multiple fields is computationally difficult. Despite a great deal of recent activity in this field, the problem is far from solved. The following features are desirable in a packet classifier: (1.) it should be fast, in order to keep up with highspeed link technologies, (2.) it should be cheap, i.e., use limited hardware resources, and (3.) it should support incremental updates. Rule-sets used for level-4 classification typically come from service level agreements and hence change infrequently. Consequently, performance and cost are more important than an ability to perform fast incremental updates. 1.1 Packet classification formalization A packet header is a binary string of fixed length Ä. Semantically, the header consists of multiple fields that are used for classifying the packet. We define a predicate to be a string of length Ä on alphabet ¼ ½. Two characters ¾ are defined to match if and only if Ï Ï µ µ µµ. A predicate Ô is defined to match a header if and only if matches Ô for all ¼ Ä, where and Ô are -th characters of and Ô respectively. Clearly, this representation is rich enough to represent a collection of prefixes on the header fields. A rule in this context is a predicate-action pair, and an action is an integer, encoding an operation performed by the router. A rule-set is a collection of rules along with their associated priorities. Given a packet header and a rule-set the task of classification consists of determining the action associated with the highest priority matching rule. 1.2 Background: Binary Decision Diagrams Our approach is motivated from the observation that rule-set represents a Boolean function that takes header bits as input and gives action as output. We make use of Binary Decision Diagrams (BDDs) [4] to represent the classification function. Given a Boolean function Ü ½ Ü ¾ Ü Ò µ and a total order on input variables, Ü ½ Ü ¾ Ü Ò the BDD of the function is computed as follows. The root node of the BDD contains two pointers one pointing to the BDD of the function ¼ Ü ¾ Ü Ò µ and other pointing to the BDD of the function ½ Ü ¾ Ü Ò µ. Applying this definition recursively, we get a tree structure in which if we merge the isomorphic sub-trees we get the BDD of the function. 1.3 Prior work At first glance, CAMs [1] seem to be ideally suited to packet classification, as they meet the asymptotic lower bounds on the problem: a CAM-based classifier for Æ rules, with header bits examined, uses Æ Æ ÐÓ Æ µ area ( Æ µ for storing the rules, and Æ ÐÓ Æ µ for the

2 priority encoder) and computes the result in ÐÓ Æ µ time ( µ for the signal to propagate down the CAM word match line [11], and ÐÓ Æ µ for the priority encoder. However, the asymptotic notation hides constants and veils the true story. We will now argue that layout and circuit constraints make CAMs distinctly inferior. We do so by comparing a CAM-based solution to IP forwarding to a solution based on a pipeline of SRAMs that evaluates a Binary Decision Diagram (BDD) representation of the IP forwarding function that we presented at Hot Interconnects last year [10]. The solution we proposed in [10] can be made to operate on a forwarding table containing entries with a pipeline of 8 SRAMs, each 512 kbits in size. 1 A CAM-based scheme requires ¼¼¼ ¾ ½ ¾ ¼¼¼ CAM cells. These are ternary CAM cells, which are of the order of 10 the size of SRAM cells, so the CAM solution is approximately the BDD-based solution in area. However, there is a subtle but significantly greater problem with a CAM-based solution. Because of pipelining, the BDD-based solution can perform one forwarding decision per SRAM access time. A CAM-based solution can also be pipelined but at much higher cost: to fully pipeline a CAM we need to insert a pipeline latch after every CAM cell. Latches burn a great deal of power, and now there is also the associated clock tree, which consumes power, and introduces problems with skew. Another problem with CAMs is that compared to BDDs and related data-structures, they are very bad at representing certain kinds of rules, e.g., rules which are on the product of two sets of prefixes. For example consider an enterprise with Æ physically separated network domains connected through a VPN. In order to classify these packets separately, we would need Æ Æ ½µ entries in the CAM to identify every source destination pair. However in case of a BDD we will need only Æ µ nodes to represent such a classifier. In contrast, our SRAM pipeline needs pipeline latches after each SRAM stage, and not each SRAM cell; thus latch cost is negligible in our architecture. In view of the above, it would seem obvious to use a BDD-based architecture for packet classification on multiple fields. However, without severe restrictions on the nature of the rule-set, the BDD for the classification function grows exponentially with the number of rules and the number of variables. To understand the origins of BDD blowup, note that the packet classification is similar to the point location problem [2]. The best algorithms for this problem either have exponential space complexity and logarithmic time complexity, or linear time and space complexity. Roughly, all approaches either proceed one rule at a time (which in- 1 In [10], we needed 14 levels, but we have since developed a dynamic programming algorithm which achieves the minimum pipeline depth for given memory constraints. volves multiple queries of the bits, but only linear space), or query the bits only once, but have exponential space. Given the maturity of the computational geometry area, it is unlikely that there will be any breakthroughs (in the computational complexity sense) on the general form of this problem. Thus any improvements are heuristic, and justified on real-world rule-sets. Most existing schemes that try to trade space for time, use some variant of DAGs or trees and query each bit from the input only once to choose one of the two paths in the data-structure. At level of a DAG or a tree there can be potentially ¾ nodes. Different data-structures such as, Gupta s RFC and HiCuts [8], our pipelined BDDs [10], and Woo s modular approach [12] try to get around this exponential blowup by tricks like merging equivalence classes and querying the variables in a dynamic order. 2 Both these approaches yield more compact data-structure than a BDD for certain class of functions. However, if a rule depends upon some input bits that are evaluated in the beginning and some input bits that are evaluated in the end, the information obtained from the bits in the beginning needs to be propagated in the data-structure till the end. This results in a large number of nodes in the middle. If a large number of diverse rules (classifying on different set of fields) are present in the rule-set, then it may not be possible to avoid such a situation for some rules under any variable ordering. Thus both HiCuts and Woo s approach also need large data-structures. Although RFC queries all the input bits at lowest level and combines the results at subsequent stages, this problem can again occur as each intermediate table in RFC represents equivalence classes of inputs seen by that table and as we go up in the hierarchy these equivalence classes can grow exponentially. Visiting inputs in dynamic order as done by HiCuts and Woo s algorithm, certainly reduces the data-structure size but also adds significant hardware complexity. Specifically, hardware must be able to connect any input bit to any lookup structure. Such interconnection networks are expensive in hardware. Before proposing the SRAM-based pipeline structure we tried to map the BDDs on an FPGA but it performed poorly because there were not enough long programmable wire on an FPGA. Hence we believe that if a hardware scheme supports dynamic order of querying inputs, the interconnection structure must be very simple. 2 Our Architecture and mapping algorithm Since the space consumed by faster classification schemes increases exponentially with the number of rules, it is natural to consider approaches which trade space for 2 We remark in passing that the RFC data-structure is similar to Tree BDDs proposed in [9] and HiCuts is very similar to Free-BDDs proposed in [6].

3 time. Specifically, if we randomly divide the rule-set into equal-sized disjoint subsets, and build lookup structures, although the time complexity increases by a factor of, the space complexity decreases exponentially (roughly ¾ Æ to ¾ Æ ). Note that by employing hardware units we can evaluate the subsets in parallel. Since our hardware is only memory banks, and memory requirements go down by partitioning there is hardly any overhead associated with having multiple hardware units. However, in the limit, when cost of sense amplifiers and decode logic starts dominating the cost of SRAM cells, this architecture ends up looking like a CAM, which we have previously argued against. This reasoning suggests we divide the rule-set into disjoint subsets, where is small, and then having hardware units that can evaluate the subsets in parallel. The output of each hardware unit can then be sent to taking a priority encoder to obtain the overall highest priority rule. This approach can be used with any lookup structure, including [8, 12, 1], and with random division of the rule-set. Of course intelligent partitioning of the rule-set will give even better results. We will now develop an algorithm for dividing the rule-set that targets a BDD-based architecture for the individual units because with BDDs we know how to pick a few top variables to reduce size even further. 2.1 BDDs The size of the BDD of a function is influenced by a number of factors. One of these is the order in which the variables are tested. For a particular Boolean function it is possible that one variable ordering gives a linear sized BDD while another variable ordering results in a BDD having an exponential number of nodes [4]. If two functions require different variable orderings in order for their BDD representation to be small, there may be no ordering under which their union is reasonably sized [5]. In our context it is possible to have two sets of rules that have compact separate BDD representation but their union has a large BDD. Our objective is to find a partition of a given rule-set, and find a good variable ordering for each subset so that the BDD representation of each subset is compact. Each BDD will return the highest priority matching rule for its ruleset and then a priority encoder will be used to obtain the highest priority matching. If we do this (1.) the total hardware cost will go down as we will use a small amount of memory, and (2.) we can use much faster memories as each memory bank will be small. However there are two issues that must be addressed. First, the number subsets in the partition must be small otherwise we will be back to TCAMs. Second, we cannot use arbitrary variable ordering as that requires implementing a costly interconnection network for each BDD (R1,R2,R3,) (R1,R2,R4) (R1,R2,R5) (R1,R2) (R1) (a) Indexing on Source IP (R3) (R4) (R5) (R1) (R2) (b) 2 Partitions, one indexing on source Ip, the other on destination IP Figure 1. Predicate source IP Destination IP R1 ******** R ** R *** R ** R ***** Table 1. A rule-set on two fields. 2.2 Variable ordering and its relationship to partitioning The individual BDD sizes depend upon associated variable ordering. Given a rule-set, the problem of finding optimum variable ordering is hard. Thus the problem of optimally partitioning the rule-set so that the resulting BDDs are compact under corresponding optimum variable orderings has two hard problems embedded in it that need to be solved simultaneously, namely optimum partitioning and optimum variable ordering for each subset of rules. The interplay between these two makes this problem extremely difficult. Our approach takes advantage of the following observation. For a given rule-set if there exists a small index set Á consisting of integers between 0 and Ä ½ such that for any pair of rules in the rule-set there is at least one integer ¾ Á such that the predicates corresponding to the rules differ at the -th bit, then the knowledge of header bits indexed by Á will allow us to eliminate all but one rule from consideration. Thus if we use the bits indexed by Á as top variables in the BDD ordering then any Á -th level node in the BDD will be matching only one rule so the BDD rooted at that node will be of constant size. At Á -th level of a BDD there can be at most ¾ Á nodes so if we can contain the size of I within a small constant Ì then we will have a small BDD. Thus our approach consists for partitioning the rule-set into small subsets such that each of them has such a small index set. As an example consider the predicates shown in Table 1. The predicates have two parts, one corresponding to the source IP address bits and another corresponding to the des-

4 tination IP address bits. As shown in the Figure 1(b) if we put R3, R4 and R5 in one subset and R1 and R2 in another then 8 bits of source IP address can be used as index bits for first subset and 8 bits of destination IP address can be used as index bits for second subset. Figure 1(a) shows if we do not partition the rule-set then even after reading first 8 bits of source IP address the BDD will still have significant number of the rules in consideration. In general, since different rules use different fields to classify it is not possible to obtain a small index set that can work for all the rules. By doing a partition we try to separate rules that favor different index sets. 2.3 Partitioning Algorithm Ideally we would like our partitioning algorithm to return a small number of subsets of the rule-set, with each set having a small number of index bits such that by just examining these bits from a packet header we could eliminate all but one rule from any subset as a potential match. We would like to limit the size of index set to a small integer Ì for the index set to be useful. Formally, we would like to partition Ê into È ½ È ¾ È Ô and a set of index positions Á for each set È such that, 1. for all, Á Ì, 2. for any pair of rules in È with corresponding predicate strings and, there is at least one index position Ð ¾ Á such that Ð Ð ; furthermore, Ð and Ð. In Section 4 we show that the decision version of this problem is NP-complete. Hence we can only hope for a good-approximation to the optimal solution. In order to compute a reasonable approximation quickly we relax some of the requirements and make some restrictions on the choice of index bits. Specifically, we limit ourselves to choosing only consecutive index bit positions, which makes sense when we are dealing with prefixes. It also makes the interconnection structure in hardware very simple because all we need to do is shift the input by the appropriate amount so that relevant index bits are on top. We allow violation of the restriction that only one rule should remain as a potential match after examining index bits but try to minimize the number of violations, i.e., for a particular assignment to index bits there should be a small number of predicates that agree over the index set. For each set in the partition define ¾ Ì buckets, each corresponding to a particular assignment to the index bits. In any set from the partition a rule is put in all the buckets that have an assignment matching the rule. So, if a rule has s in the index bits then that rule will be in present in ¾ buckets. We would like to pick the rules for a set with small such that average occupancy of buckets is small. The procedure Ö Ý Ë Ð Ø ÓÒ takes two inputs, à and. Parameter à is the maximum number of rules that are allowed in a bucket and is the maximum number of s a rule can have in index bits. Since we restrict ourselves to choice of only consecutive bits for indexing, we have only Ä choices of index bits. The procedure tries all possible index bits for a set in the partition and selects as many rules as it can under the and à constraints, and decides on the index bits that yield the largest set. The selected rules are removed from the rule-set and the procedure is repeated for all Ô sets. Once this procedure is done there may still be some rules not selected in any of the sets. We iterate over this procedure relaxing either or à by one in each iteration till a large fraction of rules make into Ô sets; the remaining rules are distributed among the subsets based on where they occupy least number of buckets. Iterating through the Ö Ý Ë Ð Ø ÓÒ procedure gives an optimal solution because it gives a solution with minimal value of à and. If we can bound à to a small constant, each node at the Ì -th level of each BDD will have to represent a BDD for at most à rules so it can have at most ¾ à nodes. Hence each rule can contribute at most ¾ à à nodes. So there can be at most Æ ¾ à õ nodes. If à can be bounded by a small constant then essentially the datastructure grows linearly in Æ. A small value of makes sure that each rule is contributing to only a small number of BDDs rooted at Ì -th level. This helps us lower the value of à 2.4 Architecture The architecture we propose uses a pipeline of SRAMs as the basic unit for evaluating each individual BDD. Each unit has as many SRAM banks as the number of levels in the BDD. The nodes of the BDD from the -th level are stored in the -th SRAM. The node consists of two pointers in the next SRAM bank for the Ø Ò and Ð branch. Once we have a BDD evaluation unit, we keep as many such units as there are component BDDs. Each BDD unit returns the highest priority matching rule along with its priority as shown in Figure 2. We put dummy rules in each subset so that at least there is one match. A priority encoder takes all these results and outputs the final match with highest priority. We will see that 10 subsets suffice to handle up to rules with reasonably sized BDDs. Thus a small, 4-stage priority encoder suffices. The barrel shifter that feeds each pipelined unit is essentially a series of Ð Ä muxes where Ä is size of header; it can also be pipelined based on cycle time requirements. From the results on our examples it is more than sufficient to provision for 1024 nodes for any level of the BDD for rules. In order to reduce the pipeline latency, we propose to read the input 4 bits at a time. This marginally in-

5 Header Bits Source IP Source Port Dest.IP Dest Port Protocol Byte reorder Pipelined SRAMs for BDD evaluation Byte reorder Pipelined SRAMs for BDD evaluation Priority Encoder Byte reorder Pipelined SRAMs for BDD evaluation Best Match Best Match Best Match Final Result Table 2. Fraction of rules with a nonempty entry in that field. N= Table 3. Fraction of rules containing Æ nonempty entries. Figure 2. Parallel BDD evaluation creases the memory requirement but decreases the number of pipeline stages from 104 to 26. We will need 16 pointers, each Ð ½¼¾ bits wide, at each node, i.e., ½ ¼ bits of storage at each node. Hence each bank requires 20KB of memory. Since we start by taking the top 8 bits as address, we need only 24 levels of SRAM. As we have 10 such units, we will have KB units, resulting in needing 4.8 MB of SRAM total. In a modern CMOS process, a 20KB SRAM block can easily deliver one access per nanosecond, and the entire 4.8 MB together with the associated control logic can (just) fit on a single die. If we design the system for 1000 rules with 5 pipelined SRAM units and at most 256 nodes per level the memory required is 480KB. Budgeting a generous one nanosecond for wiring delay, our classifier achieves a throughput of 500 Million packets per second. 3 Experiments We needed some classification rules to evaluate our scheme. The main evaluation criteria was BDD size, as that would determine the amount of memory needed. As the memory for each level is being statically allocated, the number of nodes at each level is the most important figure that determines the effectiveness of a partitioning algorithm. The other important figure is the total number BDD nodes. We could not test our scheme on real world rule-sets: network operators are not given to sharing such data. Furthermore, no-one uses rule-sets of the size we needed to see how our scheme scales. Thus we elected to evaluate our scheme on synthetically generated rule-sets. To make the test-bench realistic, we used published statistics on realworld rule-sets [8, 3]. For the source and destination address fields, we randomly selected a prefix from a snapshot of the routing table used at MAE-WEST. For ports, we used special purpose ports numbers (e.g., ftp, telnet, ssh, smtp) and random ranges. The statistical distribution of the rules generated are given in Tables 2 and 3. We now describe our results on a rule-set containing 1024 rules. We used our partitioning procedure to create 5 subsets. The BDDs for these 5 sets had 2783, 2928, 3190, 2631, and 2548 nodes. No level had more than 200 BDD nodes. Hence if we allocate 512 nodes for each level, we will be over-provisioning by a factor of 2.5 for 1024 rule. In order to show how the BDD sizes scale we have tested it on different rule-sets with 1000 to rules and partitioned them into 10 units. Figure 3 shows the total number of nodes in each case and Figure 4 shows the largest number of nodes to be accommodated in one memory bank in each case. In both cases the scaling is fairly linear. The rule-sets used for our results were generated randomly although in real world big rule-sets are made of small disjoint sets of rule that effect a particular of flow. The randomness in the synthetic database actually makes the classification more difficult than the usual case where large classifiers are built out of small classifiers [3], that tend to be disjoint. In order to reinforce this point we generated two rule-sets each containing 1024 rules. In one of these rulesets, 640 rules were generated from 10 small classifiers and Size of pbdd (number of nodes) 2e e+05 1e Number of rules Figure 3. Scaling of BDD size, as measured in the total number of BDD nodes in all BDDs.

6 Maximum width of BDD Number of rules Figure 4. Scaling of size of memory banks, as measured by the largest width of any BDD. 0% 60% 100% Subset Subset Subset Subset Subset Table 4. BDD size with X% of structured rules the rest were randomly generated as before, while the other had all its rules from 16 small sets. From these two rule-sets, we created 5 subsets. The sizes of the BDDs for these subsets for both rule-sets, and the original rule-set (which was completely randomly generated) are shown in Table 4. Clearly, adding more structure to the rule-set only helps our classifier. References [1] [2] P. K. Agarwal and J. Erickson. Advances in Discrete and Computational Geometry, chapter Geometric range searching and its relatives, pages American Mathematical Society, [3] F. Baboescu and G. Varghese. Scalable Packet Classification. In ACM SIGCOMM, [4] R. Bryant. Graph-based Algorithms for Boolean Function Manipulation. IEEE Transactions on Computers, C- 35(8): , Aug [5] R. Bryant. On the complexity of VLSI implementations and graph representations of boolean functions with application to integer multiplication. IEEE Transactions on Computers, 40(2): , Feb [6] R. Bryant. Binary Decision Diagrams and Beyond: Enabling Technologies for Formal Verification. In International Conference on Computer-Aided Design, Nov [7] M. R. Garey and D. S. Johnson. Computers and Intractability. W. H. Freeman and Co., [8] P. Gupta. Algorithms for routing lookups and packet classification. PhD thesis, CS Department, Stanford University, [9] K. L. McMillan. Hierarchical representation of discrete functions, with application to model checking. In Computer Aided Verification, July [10] A. Prakash and A. Aziz. OC-3072 Packet Classification Using BDDs and Pipelined SRAMs. In Hot Interconnects, Stanford University, CA, Aug [11] L. Tamura, T. Yang, D. Wingrad, M. Horowitz, and B. Wooley. A 4-ns BiCMOS Translation-Lookaside Buffer. IEEE Journal of Solid-State Circuits, 25(5): , Oct [12] T. Y. C. Woo. A modular approach to packet classification: Algorithms and results. In INFOCOM (3), pages , Appendix: NP-completeness proof The rule partitioning problem can be abstracted in terms of strings as follows. Given a set Ê Ö of ternary strings Ö, size of partition Ô and size of index set Ì, determine whether there exists a partition of Ê into sets Ë ½ Ë ¾ Ë Ô and an index set Á consisting of integers between 1 and Ä for each set Ë such that, Á Ì and for any pair of strings Ö ¾ Ë Ö ¾ Ë there is at least one index Ð ¾ Á such that Ö Ð Ö Ð and neither of them is an. Given a an instance of this problem and solution it is easy to verify the correctness in polynomial time by looking at each pair of rules and each index bit to make sure that there is at least one index bit where the two rules differ. Thus the rule partitioning problem is in ÆÈ. Partition into triangles problem for a graph Î µ with Î Æ is to determine whether a partition of Î into Î ½ Î ¾ Î Æ exists, such that for any Î Ù Ú Û, all three edge Ù Ú, Ù Û, and Û Ú are in. In this section we show that rule partitioning problem is at least as hard as partitioning into triangles, which is known to be NP-complete [7]. Given an instance of triangle problem on graph Î µ, such that Î Ú ½ Ú ¾ Ú Æ and ½ ¾ Ñ, construct a set of ternary strings Ê Ö such that there is one string Ö of length for each vertex Ú. For all ¼ Ñ, if Ú Ú µ and then set Ö ¼ Ö ½, and for all other strings Ö Ó, Ö Ó. Let È Ë be a partition of Ê. So for any pair of strings Ö ¾ Ë, Ö ¾ Ë, there must be at least one bit position Ð such that Ö Ð Ö Ð, Ö Ð, and Ö Ð. Hence µ is an edge in. So each Ë corresponds to a clique in the graph Î µ. As we fixed number of index bits equal to 3 and number of partitions equal to Æ then any partition can at most contain 3 rules as more than 3 strings can not be differentiated by just 3 index bits (one index bit can only differentiate between a pair of strings) and it must be exactly 3 strings because there are only Æ partitions and Æ rules. Hence we can obtain a partition of Ê only if Î µ can be partitioned into triangles. Similarly any partition of into triangles will yield a partition of Ê hence any instance of graph partitioning to triangles can be reduced to rule partitioning.

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