Multiple Cycle Data Path

Transcription

1 Multiple Cycle Data Path CS 365 Lecture 7 Prof. Yih Huang CS365 1 Multicycle Approach Break up the instructions into steps, each step takes a cycle balance the amount of work to be done restrict each cycle to use only one major functional unit At the end of a cycle store values for use in later cycles introduce additional internal registers CS

2 Multicycle Datapath and Control PCWriteCond PCSource PC 0 M u x 1 Address Write data Memory MemData [31-26] [25 21] [20 16] [15 0] register [15 0] Memory data register PCWrite IorD MemRead MemWrite MemtoReg IRWrite [15 11] Outputs Control Op [5 0] 0 M u x 1 0 M u x 1 Op SrcB Read register 1 Read Read register 2 data 1 Registers Write Read register data 2 16 SrcA RegWrite RegDst [25 0] Shift Write data 32 Sign extend Shift left 2 A B 4 0 M u x M u 2 x 3 control left 2 PC [31-28] Zero result Jump address [31-0] Out 0 M 1 u x 2 [5 0] CS365 3 Highlights in the New Datapath and data memory merged. An Register (IR) is introduced to store the current instruction. A Memory Data Register (MDR) is introduced to store data read from memory. New registers, simply called A and B, store the output of register read port 1 and 2. A new register, out, stores the output of. PC-only adders removed. CS

3 New Control Signals IorD: Determine the input to the memory address port 0: PC (for instruction fetches) 1: output (for data accesses) RegDst: select rt or rd as the destination register Write signals for IR, MDR, A, B, PC, and out. CS365 5 srca: determines the first operand to 0: PC 1: A srcb (2 bits): determines the first operand to 00: B 01: 4 10: Sign-extended immediate 11: shifted immediate CS

4 Five Execution Steps Fetch Decode and Register Fetch Execution, Memory Address Computation, or Branch Completion Memory Access or R-type instruction completion Write back INSTRUCTIONS TAKE FROM 3-5 CYCLES! CS365 7 Actions Step 1: Fetch IR = Memory[PC]; PC = PC + 4; Can we figure out the values of the control signals? Parallel or sequential actions? CS

5 Step 2: Decode and Register Fetch Read registers rs and rt in case we need them Compute the branch address in case the instruction is a branch Actions A = Reg[IR[25-21]]; B = Reg[IR[20-16]]; Out = PC + Offset CS365 9 Step 3: instruction dependent is performing one of three functions, based on instruction type Memory Reference: Out = A + sign-extend(ir[15-0]); R-type: Out = A op B; Branch: if (A==B) PC = Out; CS

6 Step 4: R-type or memory-access or or MDR = Memory[Out]; Memory[Out] = B; Reg[IR[15-11]] = Out; (lw) (sw) (R type) Step5: Write-back Reg[IR[20-16]]= MDR; CS Summary Step name fetch decode/register fetch Action for R-type instructions Action for memory-reference Action for instructions branches IR = Memory[PC] PC = PC + 4 A = Reg [IR[25-21]] B = Reg [IR[20-16]] Out = PC + (sign-extend (IR[15-0]) << 2) Action for jumps Execution, address Out = A op B Out = A + sign-extend if (A ==B) then PC = PC [31-28] II computation, branch/ (IR[15-0]) PC = Out (IR[25-0]<<2) jump completion Memory access or R-type Reg [IR[15-11]] = Load: MDR = Memory[Out] completion Out or Store: Memory [Out] = B Memory read completion Load: Reg[IR[20-16]] = MDR CS

7 Control Signals for ADD Op PCsrc srcb srca IorD RegDst PCWrite outwr BWrite AWrite MDRWr IRWrite Mem2Reg MemWrite MemRead RegWrite Sub, and, or, slt are similar CS Control Signals for LW Op PCsrc srcb srca IorD RegDst PCWrite outwr BWrite AWrite MDRWr IRWrite Mem2Reg MemWrite MemRead RegWrite CS

8 8 Control Signals for SW PCsrc srcb srca IorD RegDst PCWrite outwr BWrite AWrite MDRWr IRWrite Mem2Reg MemWrite MemRead RegWrite Op CS PCsrc srcb srca IorD RegDst PCWrite outwr BWrite AWrite MDRWr IRWrite Mem2Reg MemWrite MemRead RegWrite Op CS365 16

9 Control Signals for BEQ Op outwr BWrite AWrite MDRWr IRWrite Mem2Reg MemWrite MemRead RegWrite RegDst PCWrite srca IorD srcb PCsrc CS Review: finite state machines Finite state machines: a set of states and next state function (determined by current state and the input) output function (determined by current state and possibly input) CS

10 FSM Implementation State Register Next State Function (Combinational Circuit) Input Output Function (Combinational Circuit) Output CS Review: finite state machines Example: A fake security device consists of three lights lined up in a row, controlled by the outputs Left, Middle, and Right, which, if asserted, indicate that a light should be on. Only one light is on at a time, and the light moves from left to right and then from right to left, thus scaring away thieves who believe that the device is monitoring their activity. The rate of the eye s movement is controlled by the clock speed (which should not be too great) and that there are essentially no inputs. CS

11 Solution State Transition diagram Next/output functions Implementation CS FSM-based Control Unit 3-bit state register keeps track of the current instruction step. FSM Inputs: opcode (IR[31:26]), funct (IR[5:0]), Zero (that is rs==rt) Outputs: all control signals CS

12 State Transition Diagram CS FSM Control NS 0 NS 1 NS 2 S 0 S 1 S 2 Next State Function opcode funct zero 6 6 Output Function op srca srcb IR-Write CS

13 The Output Function CS