The Lekha 3GPP LTE FEC IP Core meets 3GPP LTE specification 3GPP TS V Release 10[1].

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1 Lekha IP 3GPP LTE FEC Encoder IP Core V1.0 The Lekha 3GPP LTE FEC IP Core meets 3GPP LTE specification 3GPP TS V Release 10[1]. 1.0 Introduction The Lekha IP 3GPP LTE FEC Encoder IP Core V1.0 addresses the implementation of the FEC building blocks compliant to 3GPP TS V Specifically, the IP core offers an efficient, easy to customize and reliable implementation of the following blocks. Optimization techniques have been used to achieve a reduced cycle count in the design of key building blocks thus making it amenable to parallel implementation for increased data rate requirements of the order of few gigabits as demanded by futuristic implementations. Similar techniques have been adopted in the decoder IP design as well to make it an efficient solution. Key sub-blocks of the IP core are Controlled selection of Turbo or Convolution path (based on data blocks input or control data input) Rate 1/3 tail biting Convolution encoder Rate 1/3 turbo encoder Rate matching for Turbo coded transport channels Rate matching for Convolution coded transport channels and control information Bit collection, selection and transmission. A high level functional block diagram of the FEC Encoder IP Core is shown in Fig.1 below. In the following pages, a brief data sheet for the IP core is provided. Control/ Data Data_in [7:0] BlockLen SoB Addr_Strt Input Double Buffer Turbo Encoder Conv. Encoder Rate Matching & Bit Collection e k NoofBitsout FEC Encoder IP Core Fig.1 High level Block diagram of FEC Encoder IP Core 1

2 Long Term Evolution (LTE) is a 3GPP initiative for next generation wireless technology which is gaining fast ground as a technology of choice to provide reliable communication and data rates for broadband mobile communications. Lekha FEC Encoder Features LTE/ LTE Advanced (LTE A) Complaint. Implements Turbo encoder as defined in Section of the specification[1]. Configurable Interleaver block sizes - Supports all block sizes i.e., K= as defined in [1] for Turbo and small block lengths (Ex: up to 64) for Convolution. Default code rate achieved is 1/3 with rate matching for other code rates supported. Easy interface definition. Customization to AXI or Avalon bus interface supported. Bit accurate C and MATLAB models available for RTL test vector generation. Device Support Supports several devices across Xilinx, Altera and Lattice device families. Test Environment HDL IP models have been verified to be bit exact with the Matlab/ ANSI C models. These are fully compliant to the LTE/ LTE A specification. Deliverables Licensable in Netlist or Verilog or VHDL source format Target technology Xilinx, Altera, Lattice devices Test bench MATLAB, C, VHDL, Verilog simulation models available Detailed technical documentation. 2

3 2.0 Turbo Encoder Turbo codes form the core part of forward error correction coding in 3GPP LTE and LTE advanced standards. A basic 1/3 rate Encoder block diagram is as shown in fig. 2 below. 1 st Constituent Encoder X k Z k C k D D D Turbo Code Interleaver C k 2 nd Constituent Encoder D D D Z k X k Fig. 2 1/3 Rate Turbo Encoder Block diagram 2.1 Input Interface All block sizes from are supported by the IP core. For a given block size of K, the input bit stream is ordered in the format X 0, X 1,., X k-1. The operation is block-wise. The input data path is doublebuffered to enable greater throughputs with pipelining. While a block of data is being written into the input buffer, a block of data is routed to the encoder sub-block in parallel. The input interface has well defined control and status signals to indicate buffer-empty, begin input block writes and to define the block length K. The input block is loaded into the input buffer in a byte-wide fashion and therefore the entire block load operation can be complete in K/8 clocks. 2.2 Interleaver It is important to achieve a minimum latency interleaver operation for efficient and high throughput operations. According to [1], the bits input to the Turbo code internal interleaver are denoted by c0, c1,, ck-1, where K is the number of input bits. The bits output from the Turbo code internal interleaver are denoted by c 0, c 1,, c K-1. The relationship between the input and output bits is represented by the equation C i = C (i), i = 0, 1,., (K-1) Where the relationship between the output index i and the input index (i) satisfies the following quadratic form: 3

4 (i)= (f 1.i + f 2.i 2 )mod K The parameters f1 and f2 depend on the block size, K and are specified in the standard. Lekha s implementation uses certain innovative methods to break the iterative computation such that the interleaver implementation is optimal both in terms of cycle count and area efficiency. Based on system s throughput requirements, there are implementations available that can parallelize the interleaver operation. 2.3 Output Interface The output follows the pattern X 0, Z 0, Z 0, X 1, Z 1, Z 1,, X K-1, Z K-1, Z K-1 Where X represents the systematic output bits from Recursive Systematic Convolutional (RSC) encoder 1, Z represents the parity bit from RSC encoder 1 and Z represents the parity output bits from RSC encoder 2. Systematic bit from RSC encoder 2 is optionally available. The output can be directly utilized or can be fed to the rate matching component based on system requirements. 2.4 Performance From the instance of block of size K being available in input buffer to the first data present at output of the encoder, K clocks are consumed. 3.0 Rate 1/3 Convolution Encoder The tail biting convolution code with constraint length 7 and coding rate 1/3 is defined according to [1]. The initial value of the shift register of the encoder shall be set to the values corresponding to the last 6 information bits in the input stream so that the initial and final states of the shift register are the same. A block diagram representation of Convolution encoder is as shown in Fig. 3 below C k D5 D4 D3 D2 D1 D0 d k (0) d k (1) d k (2) Fig.3 Block diagram of Rate 1/3 Convolution Encoder 4

5 The encoder output streams d k (0), d k (1) and d k (2) correspond to the first, second and third parity streams, respectively. 3.1 Performance From the instance the data is available in the input memory buffer to the first valid output bit from the encoder, the latency is 1 clock. To encode a block of size K bits, K clocks are consumed. 4.0 Rate matching and bit collection The rate matching and bit collection implementation is compliant to the specification of the sub-block interleaving and bit collection as in [1]. The rate matching for the FEC encoder(turbo coded transport channel and Convolutionally coded transport channels and control information) and is defined per coded block and consists of interleaving the three information bit streams represented by d (0) (1) (2) k, d k and d k respectively followed by the collection of bits and the generation of a circular buffer. The output bit streams are represented by V (0) k, V (1) k and V (2) k. The starting address for read-out from the circular buffer and the number of bits to be output and specified for read-out of the data from bit collection block. A control input T/nC selects the rate matching mode (Turbo/ Convolutional). 4.1 Performance Data from Encoder block will be filled in D k input RAM in D clocks and the data will be filled in V k memory based on interleaved addresses generated in D+Nz clocks (Nz represents the number of zeroes that are added to construct the matrix as a multiple of Resource Usage The following table provides guide values for resource usage of the FEC Encoder IP Block. The target FPGA device was taken as Xilinx 6vlx75tff484-3 Number of Slice Registers 642/ Number of Slice LUT s 2473/ Number of BRAMs inferred (18K) 6 The above resource numbers are for the FEC IP Core instance including the input dual buffer, memory for sub-block interleaved data, interleaver memory and output e k memory. Maximum operating frequencies close to 300 MHz are observed. Note: The above numbers can vary based on minor modifications in design, the exact part chosen and the tools used. The numbers are to be used as guidance values only. 5

6 References [1] 3GPP TS version Release 10 For further information or enquiry, send a request to ipbiz.rtl@lekhawireless.com The Above IP can be licensed either as a completely integrated core or separately as Turbo, Convolution and rate matching blocks. Lekha also offers customization services for these IP cores, and can also support in FPGA prototyping, board design and system software development. 6