24-Bit Pseudo Random Sequence Generator Data Sheet

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1 Bit Pseudo Random Sequence Generator 24-Bit Pseudo Random Sequence Generator Data Sheet Copyright Cypress Semiconductor Corporation. All Rights Reserved. PRS24 PSoC Blocks API Memory (Bytes) Pins (per Resources Digital Analog CT Analog SC Flash RAM External I/O) CY8C29/27/26/25/24/22/21xxx, CY8C23x33, CY8CNP102, CY8CTST110, CY8CTMG110, CY8CTST120, CY8CTMG120, CY8CTMA120, CY8C21x45, CY8C22x45 8-bit bit bit bit For one or more fully configured, functional example projects that use this User Module go to Features and Overview 2- to 8-, 16-, 24- or 32-bit general purpose pseudo-random number generator uses one, two, three or four PSoC blocks, respectively Data input clocking up to 48 MHz Programmable polynomial and seed values Serial output bit stream Computed pseudo-random number can be read directly from the LFSR The PRS User Module is a modular linear feedback shift register (LFSR) that generates a pseudo random bit stream. The polynomial and starting seed values can be specified to define its output number sequence. PRS Block Diagram, Data Path width n = 8, 16, 24 or 32 Functional Description The PRS User Module employs from one to four digital PSoC blocks, each contributing 8 bits to the total resolution. It implements a modular 2- to 8-, 16-, 24- or 32-bit linear feedback shift register, LFSR, that generates a pseudo-random bit stream. The Shift, Polynomial, Seed, and Control registers, of the PRS PSoC blocks, are used to define and control the generation of the pseudo-random bit sequence. The configuration of the underlying connective hardware, of the digital PSoC blocks, coordinate the operation of the PSoC blocks as a single PRS User Module. The Polynomial, Shift, and Seed registers refer to the combined registers. The PRSxx_MSB registers form the most significant byte of the register set and the PRSxx_LSB registers form the least significant byte. For example, the 32-bit PRS Polynomial register is composed of the PRS32_MSB, PRS32_ISB2, PRS32_ISB1, and PRS32_LSB Polynomial registers. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA Document Number: Rev. *C Revised February 12, 2009

2 The Shift register computes the LFSR function, the Polynomial register holds the polynomial that defines the LFSR polynomial, and the Seed register enables initialization of the starting data. The PRS User Module requires that the Seed and Polynomial registers be initialized, prior to setting the start bit in the PRS s Control register. Writing the seed value into the Seed register, while the PRS start bit is not set, causes the seed value to be latched into the Shift register, initializing the starting data. Writing the seed value, after the PRS has been started, has no effect. The architecture for a simple LFSR uses only a single XOR gate, to add the values of one or more bits and feed the result back into the least significant bit. The polynomial description for the simple LFSR is defined as [N, t 1, t 2,...,t m ], where N is the length of the output code in bits and t denotes the tap bit numbers that are XOR ed into the feedback summation. For example, the polynomial defined as [32,22,2,1] is a 32-bit polynomial with taps at bit 32, bit 22, bit 2, and bit 1. The polynomial defined as [8,4,3,2] is an 8-bit polynomial with taps at bit 8, bit 4, bit 3, and bit 2. Note that the most significant bit is always XOR ed into the summation. The PRS is an LFSR that is implemented using the modular form where there is one XOR gate between each bit of the shift register. The translation of the simple polynomial to the modular polynomial definition is given by the notation [N, N-t 1, N-t 2,,N-t m ]. The 32-bit PRS simple polynomial [32,22,2,1] is translated to [32,32-22,32-2,32-1] or [32,31,30,10] after re-ordering. The 8-bit PRS simple polynomial [8,4,3,2] is translated to [8,8-4,8-3,8-2] or [8,6,5,4] after re-ordering. The modular polynomial definition, similar to the simple polynomial, specifies the length and the tap bits. For the 32-bit PRS simple polynomial [32,22,2,1], the Polynomial register should be set with the modular equivalent polynomial of [32,31,30,10], which is specified as b or E h. The following table lists simple and modular irreducible polynomials that define 2- to 32-bit pseudorandom number sequences (including 8, 16, and 24 bits). Note that the table is not complete, in that only one of the many polynomials is specified. Simple and Modular Irreducible Polynomials Number of Bits Code Length Simple Form Polynomial Modular Form Polynomial 2 3 [2,1] [2,1] 3 7 [3,1] [3,2] 4 15 [4,1] [4,3] 5 31 [5,4,3,2] [5,3,2,1] 6 63 [6,5,2,1] [6,5,4,1] [7,6,5,2] [7,5,2,1] [8,4,3,2] [8,6,5,4] [9,6,4,3] [9,6,5,3] 10 1,023 [10,8,3,2] [10,8,7,2] 11 2,047 [11,8,5,2] [11,9,6,3] 12 4,095 [12,6,4,1] [12,11,8,6] 13 8,191 [13,4,3,1] [13,12,10,9] 14 16,383 [14,12,2,1] [14,13,12,2] 15 32,767 [15,13,10,9] [15,6,5,2] Document Number: Rev. *C Page 2 of 24

3 Simple and Modular Irreducible Polynomials Number of Simple Form Modular Form Bits Code Length Polynomial Polynomial 16 65,535 [16,12,3,1] [16,15,13,4] ,071 [17,3,2,1] [17,16,15,14] ,143 [18,10,7,5] [18,13,11,8] ,287 [19,5,2,1] [19,18,17,14] 20 1,048,575 [20,9,5,3] [20,17,15,11] 21 2,097,151 [21,14,7,2] [21,19,14,7] 22 4,194,303 [22,9,5,1] [22,21,17,13] 23 8,388,607 [23,17,11,5] [23,18,12,5] 24 16,777,215 [24,7,2,1] [24,23,22,17] 25 33,554,431 [25,3,2,1] [25,24,23,22] 26 67,108,863 [26,6,2,1] [26,25,24,20] ,217,727 [27,5,2,1] [27,26,25,22] ,435,455 [28,13,11,9,5,3] [28,25,23,19,17,15] ,870,911 [29,20,11,2] [29,27,18,9] 30 1,073,741,823 [30,23,2,1] [30,29,28,7] 31 2,147,483,647 [31,29,21,17] [31,14,10,2] 32 4,294,967,295 [32,22,2,1] [32,31,30,10] The maximal code length, for an N-bit LFSR pseudo random bit sequence generator, is 2 n -1. Zero is the missing value, as this will result in a terminal condition. The starting seed value must be set to any nonzero value. The polynomial length tap bit, N, is configured by the PRS PSoC block, as both the feedback and output bit. When the seed value and polynomial are initialized, the PRS User Module is started and a rising edge of the input clock generates the next state in the specified pseudo-random sequence. Tap bit N is output to the specified output bit stream synchronous with the clock. Reading the computed pseudo-random number is a two-step process. First, the Shift register is read, causing the result data to be latched into the Seed register. Then, the result is read directly from the Seed register. It is advisable to stop the PRS User Module before reading the pseudo-random value, to ensure that the linear feedback Shift register is not inadvertently clocked while reading the data. Document Number: Rev. *C Page 3 of 24

4 AC Electrical Characteristics PRS AC Electrical Characteristics for the CY8C26/25xxx Device Family Parameter Typical Limit Units Conditions and Notes Maximum input frequency MHz 8- or 16-bit width, Vdd=5.0V MHz 24- or 32-bit width Maximum output frequency MHz Vdd=5.0V and 48 MHz input clock MHz Vdd=3.3V and 24 MHz input clock PRS AC Electrical Characteristics for the CY8C29/27/24/22/21xxx Device Family Parameter Typical Limit Units Conditions and Notes Maximum input frequency MHz Vdd=5.0V 2 Maximum output frequency MHz Vdd=5.0V and 48 MHz input clock MHz Vdd=3.3V and 24 MHz input clock Electrical Characteristics Notes 1. If the input or output is routed through the global buses, then the frequency is limited to a maximum of 12 MHz. 2. Provided enable signal is always high; otherwise, the limit is 24 MHz. 3. Fastest clock available to PSoC blocks is 24 MHz at 3.3V operation. Placement The PRS consumes one digital PSoC block per 8 bits of resolution. When more than one block is allocated, all will be placed consecutively by the Device Editor in order of increasing block number from least-significant byte (LSB) to most significant (the MSB). Each block is given a symbolic name displayed by the device editor during and after placement. The API qualifies all register names with user assigned instance name and block name to provide direct access to the PRS registers through the API include files. The block names used by the various widths are given in the following table. PSoC Blocks 8-Bit PRS 16-Bit PRS 24-Bit PRS 32-Bit PRS 1 PRS8 PRS16_LSB PRS24_LSB PRS32_LSB 2 -- PRS16_MSB PRS24_ISB PRS32_ISB PRS24_MSB PRS32_ISB PRS32_MSB Parameters and Resources Clock The PRS User Module is clocked by one of 16 possible sources. The Global I/O busses may be used to connect the clock input to an external pin or a clock function generated by a different PSoC block. The 48 MHz clock, the CPU_32 khz clock, one of the divided clocks (24V1 or 24V2), or another PSoC block output can be specified as the clock input. Document Number: Rev. *C Page 4 of 24

5 OutputBitStream The output may be routed to one of four Global Output buses or disabled. CompareType Each cycle the PRS compares the value of the Shift register to the value of the Seed register. This parameter sets the type of compare function to be performed. The possible settings are given in the following table. Parameter Equal Less Than or Equal Less Than Description DAC output goes high when Shift register equals seed value. DAC output goes high when Shift register is less than or equal to seed value. DAC output goes high when Shift register is less than seed value. CompareOut The result of the compare operation (see the CompareType parameter, above) produces and active-high The DAC Output may be routed to one of four Global Ouptut buses or disabled. ClockSync In the PSoC devices, digital blocks may provide clock sources in addition to the system clocks. Digital clock sources may even be chained in ripple fashion. This introduces skew with respect to the system clocks. These skews are more critical in the CY8C29/27/24/22/21xxx PSoC device families because of various data-path optimizations, particularly those applied to the system busses. This parameter may be used to control clock skew and ensure proper operation when reading and writing PSoC block register values. Appropriate values for this parameter should be determined from the following table. ClockSync Value Use Sync to SysClk Use this setting for any 24 MHz (SysClk) derived clock source that is divided by two or more. Examples include VC1, VC2, VC3 (when VC3 is driven by SysClk), 32KHz, and digital PSoC blocks with SysClk-based sources. Externally generated clock sources should also use this value to ensure that proper synchronization occurs. Sync to SysClk*2 Use this setting for any 48 MHz (SysClk*2) based clock unless the resulting frequency is 48 MHz (in other words, when the product of all divisors is 1). Use SysClk Direct Use when a 24 MHz (SysClk/1) clock is desired. This does not actually perform synchronization but provides low-skew access to the system clock itself. If selected, this option overrides the setting of the Clock parameter, above. It should always be used instead of VC1, VC2, VC3 or Digital Blocks where the net result of all dividers in combination produces a 24 Mhz output. Unsynchronized Use when the 48 MHz (SysClk*2) input is selected. Use when unsynchronized inputs are desired. In general this use is advisable only when interrupt generation is the sole application of the Counter. Application Programming Interface The Application Programming Interface (API) routines are provided as part of the user module to allow the designer to deal with the module at a higher level. This section specifies the interface to each function together with related constants provided by the include files. Document Number: Rev. *C Page 5 of 24

6 Note In this, as in all user module APIs, the values of the A and X register may be altered by calling an API function. It is the responsibility of the calling function to preserve the values of A and X prior to the call if those values are required after the call. This registers are volatile policy was selected for efficiency reasons and has been in force since version 1.0 of PSoC Designer. The C compiler automatically takes care of this requirement. Assembly language programmers must ensure their code observes the policy, too. Though some user module API function may leave A and X unchanged, there is no guarantee they will do so in the future. 8-Bit PRS API PRS8_Start Enables the PRS8 User Module for operation. Before the module is started, the polynomial and seed values should be initialized. void PRS8_Start(void) call PRS8_Start While the PRS8 is started, a seed value written to the Seed register will not be latched into the Shift register. The A and X registers may be modified by this or future implementations of this function. The same is true for all RAM page pointer registers in the Large Memory Model (CY8C29xxx). When necessary, it is the calling function's responsibility to preserve the values across calls to fastcall16 functions. PRS8_Stop Disables the PRS8 User Module. void PRS8_Stop(void) call PRS8_Stop Writing the seed value into the Seed register will latch the seed value into the Shift register. The A and X registers may be modified by this or future implementations of this function. The same is true for all RAM page pointer registers in the Large Memory Model (CY8C29xxx). When necessary, it is the calling function's responsibility to preserve the values across calls to fastcall16 functions. Document Number: Rev. *C Page 6 of 24

7 PRS8_WriteSeed Initializes the PRS8 Shift register with an initial seed value. The user module is stopped while updating the Shift register with the new seed value. Upon exit, the start state is restored. void PRS8_WriteSeed(BYTE bseed) mov A, [bseed] call PRS8_WriteSeed bseed: 8-bit seed value and is passed in the A register. The A and X registers may be modified by this or future implementations of this function. The same is true for all RAM page pointer registers in the Large Memory Model (CY8C29xxx). When necessary, it is the calling function's responsibility to preserve the values across calls to fastcall16 functions. PRS8_WritePolynomial Loads the Polynomial register with the LFSR function polynomial. The PRS8 User Module is stopped while the Polynomial register is updated. Upon exit, the start state is restored. void PRS8_WritePolynomial(BYTE bpolynomial) mov A, [bpolynomial] call PRS8_WritePolynomial bpolynomial: 8-bit polynomial value. See the PRS User Module description section for a discussion on how to set the polynomial value. It is passed in the A register. The A and X registers may be modified by this or future implementations of this function. The same is true for all RAM page pointer registers in the Large Memory Model (CY8C29xxx). When necessary, it is the calling function's responsibility to preserve the values across calls to fastcall16 functions. PRS8_bReadPRS Reads the computed LFSR resultant data. Calling this function while the PRS8 User Module is clocked, will give inaccurate results. BYTE PRS8_bReadPRS(void) call PRS8_bReadPRS mov [bprsvalue], A Document Number: Rev. *C Page 7 of 24

8 Value read from the Shift register. It is returned in Accumulator. The Seed register will be overwritten with the computed LFSR value. The A and X registers may be modified by this or future implementations of this function. The same is true for all RAM page pointer registers in the Large Memory Model (CY8C29xxx). When necessary, it is the calling function's responsibility to preserve the values across calls to fastcall16 functions. 16-Bit PRS API PRS16_Start Enables the PRS16 User Module for operation. Before the module is started, the polynomial and seed values should be initialized. void PRS16_Start(void) call PRS16_Start While the PRS16 is started, a seed value written to the Seed register will not be latched into the Shift register. The A and X registers may be modified by this or future implementations of this function. The same is true for all RAM page pointer registers in the Large Memory Model (CY8C29xxx). When necessary, it is the calling function's responsibility to preserve the values across calls to fastcall16 functions. PRS16_Stop Disables the PRS16 User Module. void PRS16_Stop(void) call PRS16_Stop Writing the seed value into the Seed register will latch the seed value into the Shift register. The A and X registers may be modified by this or future implementations of this function. The same is true for all RAM page pointer registers in the Large Memory Model (CY8C29xxx). When necessary, it is the call- Document Number: Rev. *C Page 8 of 24

9 ing function's responsibility to preserve the values across calls to fastcall16 functions. PRS16_WriteSeed Initializes the PRS16 Shift register with an initial seed value. The PRS16 User Module is stopped while updating the Shift register with the new seed value. Upon exit, the start state is restored. void PRS16_WriteSeed(WORD wseed) mov X, [wseed] mov A, [wseed+1] call PRS16_WriteSeed wseed: 16-bit seed value. MSB is passed in the X register and LSB is passed in the Accumulator. The A and X registers may be modified by this or future implementations of this function. The same is true for all RAM page pointer registers in the Large Memory Model (CY8C29xxx). When necessary, it is the calling function's responsibility to preserve the values across calls to fastcall16 functions. PRS16_WritePolynomial Loads the Polynomial register with the LFSR function polynomial. The PRS16 User Module is stopped while the Polynomial register is updated. Upon exit, the start state is restored. void PRS16_WritePolynomial(WORD wpolynomial) mov X, [wpolynomial] mov A, [wpolynomial+1] call PRS16_WritePolynomial wpolynomial: 16-bit polynomial value. See the PRS User Module description section for a discussion on how to set the polynomial value. MSB is passed in the X register and LSB is passed in the Accumulator. The A and X registers may be modified by this or future implementations of this function. The same is true for all RAM page pointer registers in the Large Memory Model (CY8C29xxx). When necessary, it is the calling function's responsibility to preserve the values across calls to fastcall16 functions. PRS16_wReadPRS Reads the computed LFSR resultant data. Calling this function while the PRS16 User Module is clocked, will give inaccurate results. Document Number: Rev. *C Page 9 of 24

10 WORD PRS16_wReadPRS(void) call PRS16_wReadPRS mov [wprsvalue], X mov [wprsvalue+1], A Value read from the Shift register. MSB is returned in the X registers and LSB is returned in the Accumulator. The Seed register will be overwritten with the computed LFSR value. The A and X registers may be modified by this or future implementations of this function. The same is true for all RAM page pointer registers in the Large Memory Model (CY8C29xxx). When necessary, it is the calling function's responsibility to preserve the values across calls to fastcall16 functions. 24-Bit PRS API PRS24_Start Enables the PRS24 User Module for operation. Before the module is started, the polynomial and seed values should be initialized. void PRS24_Start(void) call PRS24_Start While the PRS24 is started, a seed value written to the Seed register will not be latched into the Shift register. The A and X registers may be modified by this or future implementations of this function. The same is true for all RAM page pointer registers in the Large Memory Model (CY8C29xxx). When necessary, it is the calling function's responsibility to preserve the values across calls to fastcall16 functions. PRS24_Stop Disables the PRS24 User Module. void PRS24_Stop(void) call PRS24_Stop Document Number: Rev. *C Page 10 of 24

11 Writing the seed value into the Seed register will latch the seed value into the Shift register. The A and X registers may be modified by this or future implementations of this function. The same is true for all RAM page pointer registers in the Large Memory Model (CY8C29xxx). When necessary, it is the calling function's responsibility to preserve the values across calls to fastcall16 functions. PRS24_WriteSeed Initializes the PRS24 Shift register with an initial seed value. The PRS24 User Module is stopped while updating the Shift register with the new seed value. Upon exit, the start state is restored. void PRS24_WriteSeed(DWORD dwseed) mov X, dwseed call PRS24_WriteSeed dwseed: 24-bit seed value where MSB is always zero. The X register points to dwseed. Load address of the dwseed into the X register. The A and X registers may be modified by this or future implementations of this function. The same is true for all RAM page pointer registers in the Large Memory Model (CY8C29xxx). When necessary, it is the calling function's responsibility to preserve the values across calls to fastcall16 functions. PRS24_WritePolynomial Loads the Polynomial register with the LFSR function polynomial. The PRS24 User Module is stopped while the Polynomial register is updated. Upon exit, the start state is restored. void PRS24_WritePolynomial(DWORD dwpolynomial) mov X, dwpolynomial call PRS24_WritePolynomial dwpolynomial: 24-bit polynomial value. See the PRS User Module description section for a discussion on how to set the polynomial value. The X register points to dwpolynomial. Load address of the dwseed into the X register. The A and X registers may be modified by this or future implementations of this function. The same is Document Number: Rev. *C Page 11 of 24

12 true for all RAM page pointer registers in the Large Memory Model (CY8C29xxx). When necessary, it is the calling function's responsibility to preserve the values across calls to fastcall16 functions. PRS24_ReadPRS Reads the computed LFSR resultant data. Calling this function while the PRS24 User Module is clocked, will give inaccurate results. void PRS24_ReadPRS(DWORD * pdwprsvalue) mov X, [pdwprsvalue] call PRS24_ReadPRS pdwprsvalue: Pointer to the buffer to hold the PRS generated value. The X register is loaded with the address of the return buffer. PRS generated value is returned in the pdwprsvalue buffer pointed to by the X register. The Seed register will be overwritten with the computed LFSR value. The A and X registers may be modified by this or future implementations of this function. The same is true for all RAM page pointer registers in the Large Memory Model (CY8C29xxx). When necessary, it is the calling function's responsibility to preserve the values across calls to fastcall16 functions. Currently, only the IDX_PP page pointer register is modified. 32-Bit PRS API PRS32_Start Enables the PRS32 User Module for operation. Before the module is started, the polynomial and seed values should be initialized. void PRS32_Start(void) call PRS32_Start While the PRS32 is started, a seed value written to the Seed register will not be latched into the Shift register. The A and X registers may be modified by this or future implementations of this function. The same is true for all RAM page pointer registers in the Large Memory Model (CY8C29xxx). When necessary, it is the calling function's responsibility to preserve the values across calls to fastcall16 functions. Document Number: Rev. *C Page 12 of 24

13 PRS32_Stop Disables the PRS32 User Module. void PRS32_Stop(void) call PRS32_Stop Writing the seed value into the Seed register will latch the seed value into the Shift register. The A and X registers may be modified by this or future implementations of this function. The same is true for all RAM page pointer registers in the Large Memory Model (CY8C29xxx). When necessary, it is the calling function's responsibility to preserve the values across calls to fastcall16 functions. PRS32_WriteSeed Initializes the PRS32 Shift register with an initial seed value. The PRS32 User Module is stopped while updating the Shift register with the new seed value. Upon exit, the start state is restored. void PRS32_WriteSeed(DWORD dwseed) mov X, dwseed call PRS32_WriteSeed dwseed: 32-bit seed value. The X register points to dwseed. Load address of the dwseed into the X register. The A and X registers may be modified by this or future implementations of this function. The same is true for all RAM page pointer registers in the Large Memory Model (CY8C29xxx). When necessary, it is the calling function's responsibility to preserve the values across calls to fastcall16 functions. PRS32_WritePolynomial Loads the Polynomial register with the LFSR function polynomial. The PRS32 User Module is stopped while the Polynomial register is updated. Upon exit, the start state is restored. void PRS32_WritePolynomial(DWORD dwpolynomial) mov X, dwpolynomial call PRS32_WritePolynomial Document Number: Rev. *C Page 13 of 24

14 dwpolynomial: 32-bit polynomial value. See the PRS User Module description section for a discussion on how to set the polynomial value. The X register points to dwpolynomial. Load address of the dwseed into the X register. The A and X registers may be modified by this or future implementations of this function. The same is true for all RAM page pointer registers in the Large Memory Model (CY8C29xxx). When necessary, it is the calling function's responsibility to preserve the values across calls to fastcall16 functions. PRS32_ReadPRS Reads the computed LFSR resultant data. Calling this function while the PRS32 User Module is clocked, will give inaccurate results. void PRS32_ReadPRS(DWORD * pdwprsvalue) mov X, [pdwprsvalue] call PRS32_ReadPRS pdwprsvalue: Pointer to the buffer to hold the PRS generated value. The X register is loaded with the address of the return buffer. PRS generated value is returned in the pdwprsvalue buffer pointed to by the X register. The Seed register will be overwritten with the computed LFSR value. The A and X registers may be modified by this or future implementations of this function. The same is true for all RAM page pointer registers in the Large Memory Model (CY8C29xxx). When necessary, it is the calling function's responsibility to preserve the values across calls to fastcall16 functions. Currently, only the IDX_PP page pointer register is modified. Sample Code 8-Bit PRS Sample Firmware Source Code In the following examples, the correspondence between the C and assembly code is simple and direct. The values shown for period and compare value are each off-by-1 from the cardinal values because the registers are zero-based; i.e., zero is the terminal count in their down-count cycle. Passing a simple one byte parameter in the A register rather than on the stack is a performance optimization used by both the assembler and C compiler for user module APIs. The C compiler employs this mechanism for INT types instead of pushing the argument on the stack when it sees the #pragma fastcall declarations in the PRS8.h file. The following is assembly language source that illustrates the use of the APIs. ;********************************************************************** ; Setup the PRS8 to generate an 8-bit maximal sequence. ; ;********************************************************************** Document Number: Rev. *C Page 14 of 24

15 include "PRS8.inc" export SetupPRS255 bpoly_255: equ % ; Modular Polynomial = [8,6,5,4] bseed_255: equ % ; Seed value all bits set SetupPRS255: ; load the PRS polynomial mov A, bpoly_255 call PRS8_WritePolynomial ; load the PRS seed mov A, bseed_255 call PRS8_WriteSeed ;start the PRS8 call PRS8_Start ret The same code in C is as follows. #include "PRS8.h" #define bpoly_255 0xB8 // Modular Polynomial = [8,6,5,4] #define bseed_255 0xFF // Seed value void SetupPRS255(void) { // load the PRS polynomial PRS8_WritePolynomial(bPOLY_255); // load the PRS seed PRS8_WriteSeed(bSEED_255); } // start the PRS8 PRS8_Start(); 16-Bit PRS Sample Firmware Source Code In the following examples, the correspondence between the C and assembly code is simple and direct. The values shown for period and compare value are each off-by-1 from the cardinal values because the registers are zero-based; i.e., zero is the terminal count in their down-count cycle. Passing a simple one byte parameter in the A register rather than on the stack is a performance optimization used by both the assembler and C compiler for user module APIs. The C compiler employs this mechanism for INT types instead of pushing the argument on the stack when it sees the #pragma fastcall declarations in the PRS16.h file. The following is assembly language source that illustrates the use of the APIs. ;********************************************************************** ; ; Setup the PRS16 to generate a 12-bit maximal sequence. ; ;********************************************************************** include "PRS16.inc" export SetupPRS12Bit Document Number: Rev. *C Page 15 of 24

16 wpoly: equ % ; Modular Polynomial = [12,11,8,6] wseed: equ FFFFh ; Seed value all bits set SetupPRS12Bit: mov X, >wpoly ; load the PRS polynomial mov A, <wpoly call PRS16_WritePolynomial mov X, >wseed ; load the PRS seed mov A, <wseed call PRS16_WriteSeed call PRS16_Start ret ;start the PRS16 The same code in C is as follows. #include "PRS16.h" #define wpoly 0x0CA0 // Modular Polynomial = [12,11,8,6] #define wseed 0xFFFF // Seed value void SetupPRS12Bit(void) { // load the PRS polynomial PRS16_WritePolynomial(wPOLY); // load the PRS seed PRS16_WriteSeed(wSEED); } // start the PRS16 PRS16_Start(); 24-Bit PRS Sample Firmware Source Code In the following examples, the correspondence between the C and assembly code is simple and direct. The values shown for period and compare value are each off-by-1 from the cardinal values because the registers are zero-based; i.e., zero is the terminal count in their down-count cycle. Passing a simple one byte parameter in the A register rather than on the stack is a performance optimization used by both the assembler and C compiler for user module APIs. The C compiler employs this mechanism for INT types instead of pushing the argument on the stack when it sees the #pragma fastcall declarations in the PRS24.h file. The following is assembly language source that illustrates the use of the APIs. ;****************************************************************** ; ; Setup the PRS24 to generate a 24-bit maximal sequence. ; ;****************************************************************** include "PRS24.inc" export SetupPRS24Bit dwpoly: equ 00E10000h ; Modular Polynomial = [24,23,22,17] dwseed: equ 00FFFFFFh ; Seed value all bits set Document Number: Rev. *C Page 16 of 24

17 SetupPRS24Bit: ; load the PRS polynomial mov X, SP add SP, 4 mov [X], 0 mov [X+1], (dwpoly >> 16) & ffh mov [X+2], (dwpoly >> 8 ) & ffh mov [X+3], (dwpoly & ffh) call PRS24_WritePolynomial add SP, -4 ; load the PRS seed mov X, SP add SP, 4 mov [X], 0 mov [X+1], (dwseed >> 16) & ffh mov [X+2], (dwseed >> 8 ) & ffh mov [X+3], (dwseed & ffh) call PRS24_WriteSeed add SP, -4 ;start the PRS24 call PRS24_Start ret The same code in C is as follows. #include "PRS24.h" #define dwpoly 0xE10000 // Modular Polynomial = [24,23,22,17] #define dwseed 0xFFFFFF // Seed value void SetupPRS24Bit(void) { // load the PRS polynomial PRS24_WritePolynomial(dwPOLY); // load the PRS seed PRS24_WriteSeed(dwSEED); } // start the PRS24 PRS24_Start(); 32-Bit PRS Sample Firmware Source Code In the following examples, the correspondence between the C and assembly code is simple and direct. The values shown for period and compare value are each off-by-1 from the cardinal values because the registers are zero-based; i.e., zero is the terminal count in their down-count cycle. Passing a simple one byte parameter in the A register rather than on the stack is a performance optimization used by both the assembler and C compiler for user module APIs. The C compiler employs this mechanism for INT types instead of pushing the argument on the stack when it sees the #pragma fastcall declarations in the PRS32.h file. The following is assembly language source that illustrates the use of the APIs. ;*********************************************************************** Document Number: Rev. *C Page 17 of 24

18 ; ; Setup the PRS32 to generate a 32-bit maximal sequence. ; ;*********************************************************************** include "PRS32.inc" export SetupPRS32Bit dwpoly: equ E h ; Modular Polynomial = [32,31,30,10] dwseed: equ FFFFFFFFh ; Seed value all bits set SetupPRS32Bit: ; load the PRS polynomial mov X, SP add SP, 4 mov [X], (dwpoly >> 24) & ffh // MSB mov [X+1], (dwpoly >> 16) & ffh // ISB2 mov [X+2], (dwpoly >> 8 ) & ffh // ISB1 mov [X+3], (dwpoly & ffh) // LSB call PRS32_WritePolynomial add SP, -4 ; load the PRS seed mov X, SP add SP, 4 mov [X], (dwseed >> 24) & ffh mov [X+1], (dwseed >> 16) & ffh mov [X+2], (dwseed >> 8 ) & ffh mov [X+3], (dwseed & ffh) call PRS32_WriteSeed add SP, -4 ;start the PRS32 call PRS32_Start ret The same code in C is as follows. #include "PRS32.h" #define dwpoly 0xE // Modular Polynomial = [32,31,30,10] #define dwseed 0xFFFFFFFF // Seed value void SetupPRS12Bit(void) { // load the PRS polynomial PRS32_WritePolynomial(dwPOLY); // load the PRS seed PRS32_WriteSeed(dwSEED); } // start the PRS32 PRS32_Start(); Document Number: Rev. *C Page 18 of 24

19 Configuration Registers Except where noted, the register specifications given in this section apply to all PSoC device families. 8-Bit PRS Configuration Registers The 8-bit PRS uses a single digital PSoC block named PRS8. Each block is personalized and parameterized through 7 registers. The following tables give the personality values as constants and the parameters as named bit-fields with brief descriptions. Symbolic names for these registers are defined in the user module instance s C and assembly language interface files (the.h and.inc files). Function Register, Bank 1 Value Block PRS8 Register: Input Bit Value Clock Clock selects the input clock from one of 16 sources. This parameter is set in the Device Editor. Block PRS8 Register: Output Bit Value OutputBitStream OutputBitStream selects output from one of four global busses. This parameter is set in the Device Editor. Block PRS8 Shift Register: DR0 Bit Value Shift Register Shift Register is the PRS8 Shift register. It is read and configured using the PRS8 API. Block PRS8 Polynomial Register: DR1 Bit Value Polynomial Register Polynomial Register is the PRS8 Polynomial register. It is modified using the PRS8 API. Block PRS8 Seed Register: DR2 Bit Value Seed Register Seed Register is the PRS8 Seed register. It is modified using the PRS8 API. Document Number: Rev. *C Page 19 of 24

20 Block PRS8 Control Register: CR0 Bit Value Start/Stop Start/Stop indicates that the PRS8 is enabled when set. It is modified using the PRS8 API. 16-Bit PRS Configuration Registers The 16-bit PRS uses two digital PSoC blocks. In placement order from left to right they are named PRS16_LSB and PRS16_MSB. Each block is personalized and parameterized through 7 registers. The following tables give the personality values as constants and the parameters as named bit-fields with brief descriptions. Symbolic names for these registers are defined in the user module instance s C and assembly language interface files (the.h and.inc files). Function Register, Bank 1 MSB LSB Input Register, Bank 1 MSB Clock LSB Clock Clock selects the input clock from one of 16 sources. This parameter is set in the Device Editor. Output Register, Bank 1 MSB OutputBitStream LSB OutputBitStream selects output from one of four global busses. This parameter is set in the Device Editor. Shift Register (DR0), Bank 0 MSB Shift Register(MSB) LSB Shift Register(LSB) Shift Register is the PRS16 Shift register MSB and LSB. It is read and configured using the PRS16 API. Document Number: Rev. *C Page 20 of 24

21 Polynomial Register (DR1), Bank 0 MSB Polynomial Register(MSB) LSB Polynomial Register(LSB) Polynomial Register is the PRS16 Polynomial register MSB and LSB. It is modified using the PRS16 API. Seed Register (DR2), Bank 0 MSB Seed Register(MSB) LSB Seed Register(LSB) Seed Register is the PRS16 Seed register MSB and LSB. It is modified using the PRS16 API. Control Register (CR0), Bank 0 MSB LSB Start/Stop Start/Stop indicates that the PRS16 is enabled when set. It is modified using the PRS16 API. 24-Bit PRS Configuration Registers The 24-bit PRS uses three digital PSoC blocks. In placement order from left to right they are named PRS24_LSB, PRS24_ISB and PRS24_MSB. Each block is personalized and parameterized through 7 registers. The following tables give the personality values as constants and the parameters as named bit-fields with brief descriptions. Symbolic names for these registers are defined in the user module instance s C and assembly language interface files (the.h and.inc files). Function Register, Bank 1 MSB ISB LSB Input Register, Bank 1 MSB Clock ISB Clock LSB Clock Clock selects the input clock from one of 16 sources. This parameter is set in the Device Editor. Document Number: Rev. *C Page 21 of 24

22 Output Register, Bank 1 MSB OutputBitStream ISB LSB OutputBitStream selects output from one of four global busses. This parameter is set in the Device Editor. Shift Register (DR0), Bank 0 MSB ISB LSB Shift Register(MSB) Shift Register(ISB) Shift Register(LSB) Shift Register is the PRS24 Shift register MSB, ISB and LSB. It is read and configured using the PRS24 API. Polynomial Register (DR1), Bank 0 MSB ISB LSB Polynomial Register(MSB) Polynomial Register(ISB) Polynomial Register(LSB) Polynomial Register is the PRS24 Polynomial register MSB, ISB and LSB. It is modified using the PRS24 API. Seed Register (DR2), Bank 0 MSB Seed Register(MSB) ISB Seed Register(ISB) LSB Seed Register(LSB) Seed Register is the PRS24 Seed register MSB, ISB and LSB. It is modified using the PRS24 API. Control Register (CR0), Bank 0 MSB ISB LSB Start/Stop Start/Stop indicates that the PRS24 is enabled when set. It is modified using the PRS24 API. Document Number: Rev. *C Page 22 of 24

23 32-Bit PRS Configuration Registers The 32-bit PRS uses four digital PSoC blocks. In placement order from left to right they are named PRS32_LSB, PRS32_ISB1, PRS32_ISB2 and PRS32_MSB. Each block is personalized and parameterized through 7 registers. The following tables give the personality values as constants and the parameters as named bit-fields with brief descriptions. Symbolic names for these registers are defined in the user module instance s C and assembly language interface files (the.h and.inc files). Function Register, Bank 1 MSB ISB ISB LSB Input Register, Bank 1 MSB Clock ISB Clock ISB Clock LSB Clock Clock selects the input clock from one of 16 sources. This parameter is set in the Device Editor. Output Register, Bank 1 MSB OutputBitStream ISB ISB LSB OutputBitStream selects output from one of four global busses. This parameter is set in the Device Editor. Shift Register (DR0), Bank 0 MSB ISB2 ISB1 LSB Shift Register(MSB) Shift Register(ISB2) Shift Register(ISB2) Shift Register(LSB) Shift Register is the PRS32 Shift register MSB, ISB2, ISB1 and LSB. It is read and configured using the PRS32 API. Document Number: Rev. *C Page 23 of 24

24 Polynomial Register (DR1), Bank 0 MSB Polynomial Register(MSB) ISB2 Polynomial Register(ISB2) ISB1 Polynomial Register(ISB1) LSB Polynomial Register(LSB) Polynomial Register is the PRS32 Polynomial register MSB, ISB2, ISB1 and LSB. It is modified using the PRS32 API. Seed Register (DR2), Bank 0 MSB Seed Register(MSB) ISB2 Seed Register(ISB2) ISB1 Seed Register(ISB1) LSB Seed Register(LSB) Seed Register is the PRS32 Seed register MSB, ISB2, ISB1 and LSB. It is modified using the PRS32 API. Control Register (CR0), Bank 0 MSB ISB ISB LSB Start/Stop Start/Stop indicates that the PRS32 is enabled when set. It is modified using the PRS32 API. Document Number: Rev. *C Revised February 12, 2009 Page 24 of 24 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in lifesupport systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PSoC Designer, Programmable System-on-Chip, and PSoC Express are trademarks and PSoC is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.

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