Unit 1 8 BIT MICROPROCESSOR ARCHITECTURE

Transcription

1 Unit 1 8 BIT MICROPROCESSOR ARCHITECTURE Internal Architecture - Addressing modes - Instruction set -Timing diagrams -Interrupts-Assembly language Programming

2 1. Internal Architecture of 8085 Microprocessor Control Unit Generates signals within up to carry out the instruction, which has been decoded. In reality causes certain connections between blocks of the up to be opened or closed, so that data goes where it is required, and so that ALU operations occur. Arithmetic Logic Unit The ALU performs the actual numerical and logic operation such as add, subtract, AND, OR, etc. Uses data from memory and from Accumulator to perform arithmetic. Always stores result of operation in Accumulator. 2

3 Registers The 8085/8080A-programming model includes six registers, one accumulator, and one flag register, as shown in Figure. In addition, it has two 16-bit registers: the stack pointer and the program counter. They are described briefly as follows. The 8085/8080A has six general-purpose registers to store 8-bit data; these are identified as B,C,D,E,H, and L as shown in the figure. They can be combined as register pairs - BC, DE, and HL - to perform some 16-bit operations. The programmer can use these registers to store or copy data into the registers by using data copy instructions. Accumulator Flags The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU). This register is used to store 8-bit data and to perform arithmetic and logical operations. The result of an operation is stored in the accumulator. The accumulator is also identified as register A. The ALU includes five flip-flops, which are set or reset after an operation according to data conditions of the result in the accumulator and other registers. They are called Zero(Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags; they are listed in the Table and their bit positions in the flag register are shown in the Figure below. The most commonly used flags are Zero, Carry, and Sign. The microprocessor uses these flags to test data conditions. For example, after an addition of two numbers, if the sum in the accumulator id larger than eight bits, the flip-flop uses to indicate a carry -- called the Carry flag (CY) is set to one. When an arithmetic operation results in zero, the flip-flop called the Zero(Z) flag is set to one. The first Figure shows an 8-bit register, called the flag register, adjacent to the accumulator. However, it is not used as a register; five bit positions out of eight are used to store the outputs of the five flip-flops. 3

4 The flags are stored in the 8-bit register so that the programmer can examine these flags (data conditions) by accessing the register through an instruction. These flags have critical importance in the decision-making process of the microprocessor. The conditions (set or reset) of the flags are tested through the software instructions. For example, the instruction JC (Jump on Carry) is implemented to change the sequence of a program when CY flag is set. The thorough understanding of flag is essential in writing assembly language programs. Program Counter (PC) This 16-bit register deals with sequencing the execution of instructions. This register is a memory pointer. Memory locations have 16-bit addresses, and that is why this is a 16-bit register. The microprocessor uses this register to sequence the execution of the instructions. The function of the program counter is to point to the memory address from which the next byte is to be fetched. When a byte (machine code) is being fetched, the program counter is incremented by one to point to the next memory location Stack Pointer (SP) The stack pointer is also a 16-bit register used as a memory pointer. It points to a memory location in R/W memory, called the stack. The beginning of the stack is defined by loading 16-bit address in the stack pointer. The stack concept is explained in the chapter "Stack and Subroutines." Instruction Register/Decoder Temporary store for the current instruction of a program. Latest instruction sent here from memory prior to execution. Decoder then takes instruction and decodes or interprets the instruction. Decoded instruction then passed to next stage. Memory Address Register 4

5 Holds address, received from PC, of next program instruction. Feeds the address bus with addresses of location of the program under execution. Control Generator Generates signals within up to carry out the instruction which has been decoded. In reality causes certain connections between blocks of the up to be opened or closed, so that data goes where it is required, and so that ALU operations occur. Register Selector This block controls the use of the register stack in the example. Just a logic circuit which switches between different registers in the set will receive instructions from Control Unit. General Purpose Registers up requires extra registers for versatility. Can be used to store additional data during a program. More complex processors may have a variety of differently named registers. Microprogramming How does the µp knows what an instruction means, especially when it is only a binary number? The microprogram in a up/uc is written by the chip designer and tells the up/uc the meaning of each instruction up/uc can then carry out operation System Bus Typical system uses a number of busses, collection of wires, which transmit binary numbers, one bit per wire. A typical microprocessor communicates with memory and other devices (input and output) using three busses: Address Bus, Data Bus and Control Bus. Address Bus One wire for each bit, therefore 16 bits = 16 wires. Binary number carried alerts memory to open the designated box. Data (binary) can then be put in or taken out. The Address Bus consists of 16 wires, therefore 16 bits. Its "width" is 16 bits. A 16 bit binary number allows 216 different numbers, or different numbers, ie up to

6 Because memory consists of boxes, each with a unique address, the size of the address bus determines the size of memory, which can be used. To communicate with memory the microprocessor sends an address on the address bus, eg (3 in decimal), to the memory. The memory the selects box number 3 for reading or writing data. Address bus is unidirectional, ie numbers only sent from microprocessor to memory, not other way. Question?: If you have a memory chip of size 256 kilobytes (256 x 1024 x 8 bits), how many wires does the address bus need, in order to be able to specify an address in this memory? Note: the memory is organized in groups of 8 bits per location, therefore, how many locations must you be able to specify? Data Bus Data Bus: carries data, in binary form, between µp and other external units, such as memory. Typical size is 8 or 16 bits. Size determined by size of boxes in memory and µp size helps determine performance of µp. The Data Bus typically consists of 8 wires. Therefore, 28 combinations of binary digits. Data bus used to transmit "data", ie information, results of arithmetic, etc, between memory and the microprocessor. Bus is bi-directional. Size of the data bus determines what arithmetic can be done. If only 8 bits wide then largest number is (255 in decimal). Therefore, larger number have to be broken down into chunks of 255. This slows microprocessor. Data Bus also carries instructions from memory to the microprocessor. Size of the bus therefore limits the number of possible instructions to 256, each specified by a separate number. Control Bus Control Bus are various lines which have specific functions for coordinating and controlling up operations. Eg: Read/NotWrite line, single binary digit. Control whether memory is being written to (data stored in mem) or read from (data taken out of mem) 1 = Read, 0 = Write. May also include clock line(s) for timing/synchronising, interrupts, reset etc. Typically µp has 10 control lines. Cannot function correctly without these vital control signals. 6

7 The Control Bus carries control signals partly unidirectional, partly bi-directional. Control signals are things like "read or write". This tells memory that we are either reading from a location, specified on the address bus, or writing to a location specified. Various other signals to control and coordinate the operation of the system. Modern day microprocessors, like 80386, have much larger busses. Typically 16 or 32 bit busses, which allow larger number of instructions, more memory location, and faster arithmetic. Microcontrollers organized along same lines, except: because microcontrollers have memory etc inside the chip, the busses may all be internal. In the microprocessor the three busses are external to the chip (except for the internal data bus). In case of external busses, the chip connects to the busses via buffers, which are simply an electronic connection between external bus and the internal data bus Pin description. Properties Single + 5V Supply 4 Vectored Interrupts (One is Non Maskable) Serial In/Serial Out Port Decimal, Binary, and Double Precision Arithmetic Direct Addressing Capability to 64K bytes of memory The Intel 8085A is a new generation, complete 8 bit parallel central processing unit (CPU). 7

8 The 8085A uses a multiplexed data bus. The address is split between the 8bit address bus and the 8bit data bus. Figures are at the end of the document. Pin Description The following describes the function of each pin: A6 - A1s (Output 3 State) Address Bus; The most significant 8 bits of the memory address or the 8 bits of the I/0 address,3 stated during Hold and Halt modes. AD0-7 (Input/Output 3state) Multiplexed Address/Data Bus; Lower 8 bits of the memory address (or I/0 address) appear on the bus during the first clock cycle of a machine state. It then becomes the data bus during the second and third clock cycles. 3 stated during Hold and Halt modes. ALE (Output) Address Latch Enable: It occurs during the first clock cycle of a machine state and enables the address to get latched into the on chip latch of peripherals. The falling edge of ALE is set to guarantee setup and hold times for the address information. ALE can also be used to strobe the status information. ALE is never 3stated. SO, S1 (Output) Data Bus Status. Encoded status of the bus cycle: S1 S0 O O HALT 0 1 WRITE 1 0 READ 1 1 FETCH S1 can be used as an advanced R/W status. RD (Output 3state) READ; indicates the selected memory or 1/0 device is to be read and that the DataBus is available for the data transfer. WR (Output 3state) WRITE; indicates the data on the Data Bus is to be written into the selected memory or 1/0 location. Data is set up at the trailing edge of WR. 3stated during Hold and Halt modes. READY (Input) If Ready is high during a read or write cycle, it indicates that the memory or peripheral is ready to send or receive data. If Ready is low, the CPU will wait for Ready to go high before completing the read or write cycle. 8

9 HOLD (Input) HOLD; indicates that another Master is requesting the use of the Address and Data Buses. The CPU, upon receiving the Hold request. will relinquish the use of buses as soon as the completion of the current machine cycle. Internal processing can continue. The processor can regain the buses only after the Hold is removed. When the Hold is acknowledged, the Address, Data, RD, WR, and IO/M lines are 3stated. HLDA (Output) HOLD ACKNOWLEDGE; indicates that the CPU has received the Hold request and that it will relinquish the buses in the next clock cycle. HLDA goes low after the Hold request is removed. The CPU takes the buses one half clock cycle after HLDA goes low. INTR (Input) INTERRUPT REQUEST; is used as a general purpose interrupt. It is sampled only during the next to the last clock cycle of the instruction. If it is active, the Program Counter (PC) will be inhibited from incrementing and an INTA will be issued. During this cycle a RESTART or CALL instruction can be inserted to jump to the interrupt service routine. The INTR is enabled and disabled by software. It is disabled by Reset and immediately after an interrupt is accepted. INTA (Output) INTERRUPT ACKNOWLEDGE; is used instead of (and has the same timing as) RD during the Instruction cycle after an INTR is accepted. It can be used to activate the 8259 Interrupt chip or some other interrupt port. RST 5.5 RST (Inputs) RST 7.5 RESTART INTERRUPTS; These three inputs have the same timing as I NTR except 9

10 they cause an internal RESTART to be automatically inserted. RST 7.5 ~~ Highest Priority RST 6.5 RST 5.5 o Lowest Priority The priority of these interrupts is ordered as shown above. These interrupts have a higher priority than the INTR. TRAP (Input) Trap interrupt is a nonmaskable restart interrupt. It is recognized at the same time as INTR. It is unaffected by any mask or Interrupt Enable. It has the highest priority of any interrupt. RESET IN (Input) Reset sets the Program Counter to zero and resets the Interrupt Enable and HLDA flipflops. None of the other flags or registers (except the instruction register) are affected The CPU is held in the reset condition as long as Reset is applied. RESET OUT (Output) Indicates CPlJ is being reset. Can be used as a system RESET. The signal is synchronized to the processor clock. X1, X2 (Input) Crystal or R/C network connections to set the internal clock generator X1 can also be an external clock input instead of a crystal. The input frequency is divided by 2 to give the internal operating frequency. CLK (Output) Clock Output for use as a system clock when a crystal or R/ C network is used as an input to the CPU. The period of CLK is twice the X1, X2 input period. IO/M (Output) IO/M indicates whether the Read/Write is to memory or l/o Tristated during Hold and Halt modes. SID (Input) Serial input data line The data on this line is loaded into accumulator bit 7 whenever a RIM instruction is executed. SOD (output) Serial output data line. The output SOD is set or reset as specified by the SIM instruction. Vcc +5 volt supply. 10

11 Vss Ground Reference Functional Description The 8085A is a complete 8 bit parallel central processor. It requires a single +5 volt supply. Its basic clock speed is 3 MHz thus improving on the present 8080's performance with higher system speed. Also it is designed to fit into a minimum system of three IC's: The CPU, a RAM/ IO, and a ROM or PROM/IO chip. The 8085A uses a multiplexed Data Bus. The address is split between the higher 8bit Address Bus and the lower 8bit Address/Data Bus. During the first cycle the address is sent out. The lower 8bits are latched into the peripherals by the Address Latch Enable (ALE). During the rest of the machine cycle the Data Bus is used for memory or l/o data. The 8085A provides RD, WR, and lo/memory signals for bus control. An Interrupt Acknowledge signal (INTA) is also provided. Hold, Ready, and all Interrupts are synchronized. The 8085A also provides serial input data (SID) and serial output data (SOD) lines for simple serial interface. In addition to these features, the 8085A has three maskable, restart interrupts and one nonmaskable trap interrupt. The 8085A provides RD, WR and IO/M signals for Bus control. Status Information Status information is directly available from the 8085A. ALE serves as a status strobe The status is partially encoded, and provides the user with advanced timing of the type of bus transfer being done. IO/M cycle status signal is provided directly also. Decoded So, S1 Carries the following status information: 11

12 HALT, WRITE, READ, FETCH S1 can be interpreted as R/W in all bus transfers. In the 8085A the 8 LSB of addressare multiplexed with the data instead of status. The ALE line is used as a strobe to enter the lower half of the address into the memory or peripheral address latch. This also frees extra pins for expanded interrupt capability. Interrupt and Serial l/o The8085A has5 interrupt inputs: INTR, RST5.5, RST6.5, RST 7.5, and TRAP. INTR is identical in function to the 8080 INT. Each of the three RESTART inputs, 5.5, , has a programmable mask. TRAP is also a RESTART interrupt except it is nonmaskable. The three RESTART interrupts cause the internal execution of RST (saving the program counter in the stack and branching to the RESTART address) if the interrupts are enabled and if the interrupt mask is not set. The non-maskable TRAP causes the internal execution of a RST independent of the state of the interrupt enable or masks. The interrupts are arranged in a fixed priority that determines which interrupt is to be recognized if more than one is pending as follows: TRAP highest priority, RST 7.5,RST 6.5, RST 5.5, INTR lowest priority This priority scheme does not take into account the priority of a routine that was started by a higher priority interrupt. RST 5.5 can interrupt a RST 7.5 routine if the interrupts were reenabled before the end of the RST 7.5 routine. The TRAP interrupt is useful for catastrophic errors such as power failure or bus error. The TRAP input is recognized just as any other interrupt but has the highest priority. It is not affected by any flag or mask. The TRAP input is both edge and level sensitive. Basic System Timing The 8085A has a multiplexed Data Bus. ALE is used as a strobe to sample the lower 8bits of address on the Data Bus. 12

13 Figure 2 shows an instruction fetch, memory read and l/ O write cycle (OUT). Note that during the l/o write and read cycle that the l/o port address is copied on both the upper and lower half of the address. As in the 8080, the READY line is used to extend the read and write pulse lengths so that the 8085A can be used with slow memory. Hold causes the CPU to relingkuish the bus when it is through with it by floating the Address and Data Buses. System Interface 8085A family includes memory components, which are directly compatible to the 8085A CPU. For example, a system consisting of the three chips, 8085A, 8156, and 8355 will have the following features: 2K Bytes ROM 256 Bytes RAM 1 Timer/Counter 4 8bit l/o Ports 1 6bit l/o Port 4 Interrupt Levels Serial In/Serial Out Ports In addition to standard l/o, the memory mapped I/O offers an efficient l/o addressing technique. With this technique, an area of memory address space is assigned for l/o address, thereby, using the memory address for I/O manipulation. The 8085A CPU can also interface with the standard memory that does not have the multiplexed address/data bus. 13

14 5. The 8085 Programming Model In the previous tutorial we described the 8085 microprocessor registers in reference to the internal data operations. The same information is repeated here briefly to provide the continuity and the context to the instruction set and to enable the readers who prefer to focus initially on the programming aspect of the microprocessor. The 8085 programming model includes six registers, one accumulator, and one flag register, as shown in Figure. In addition, it has two 16-bit registers: the stack pointer and the program counter. They are described briefly as follows. Registers The 8085 has six general-purpose registers to store 8-bit data; these are identified as B,C,D,E,H, and L as shown in the figure. They can be combined as register pairs -BC, DE, and HL - to perform some 16-bit operations. The programmer can use these registers to store or copy data into the registers by using data copy instructions. Accumulator The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU). This register is used to store 8-bit data and to perform arithmetic and logical operations. The result of an operation is stored in the accumulator. The accumulator is also identified as register A. ACCUMULATOR A (8) FLAG REGISTER B (8) D (8) H (8) Stack Pointer (SP) (16) Program Counter (PC) (16) C (8) E (8) L (8) Data Bus Address Bus 8 Lines Bidirectional 16 Lines unidirectional Flags The ALU includes five flip-flops, which are set or reset after an operation according to data conditions of the result in the accumulator and other registers. They are called Zero(Z), Carry (CY), Sign (S), 14

15 Parity (P), and Auxiliary Carry (AC) flags; their bit positions in the flag register are shown in the Figure below. The most commonly used flags are Zero, Carry, and Sign. The microprocessor uses these flags to test data conditions. For example, after an addition of two numbers, if the sum in the accumulator id larger than eight bits, the flip-flop uses to indicate a carry -- called the Carry flag (CY) is set to one. When an arithmetic operation results in zero, the flip-flop called the Zero(Z) flag is set to one. The first Figure shows an 8-bit register, called the flag register, adjacent to the accumulator. However, it is not used as a register; five bit positions out of eight are used to store the outputs of the five flip-flops. The flags are stored in the 8-bit register so that the programmer can examine these flags (data conditions) by accessing the register through an instruction. These flags have critical importance in the decision-making process of the microprocessor. The conditions (set or reset) of the flags are tested through the software instructions. For example, the instruction JC (Jump on Carry) is implemented to change the sequence of a program when CY flag is set. The thorough understanding of flag is essential in writing assembly language programs. Program Counter (PC) This 16-bit register deals with sequencing the execution of instructions. This register is a memory pointer. Memory locations have 16-bit addresses, and that is why this is a 16-bit register. The microprocessor uses this register to sequence the execution of the instructions. The function of the program counter is to point to the memory address from which the next byte is to be fetched. When a byte (machine code) is being fetched, the program counter is incremented by one to point to the next memory location Stack Pointer (SP) 15

16 The stack pointer is also a 16-bit register used as a memory pointer. It points to a memory location in R/W memory, called the stack. The beginning of the stack is defined by loading 16-bit address in the stack pointer. This programming model will be used in subsequent tutorials to examine how these registers are affected after the execution of an instruction Instructions - Datatransfer DATA TRANSFER INSTRUCTIONS Opcode MOV Operand Rd, Rs M, Rs Rd, M Explanation of Instruction Copy from source(rs) to destination(rd) Description This instruction copies the contents of the source register into the destination register; the contents of the source register are not altered. If one of the operands is a memory location, its location is specified by the contents of the HL registers. Example: MOV B, C or MOV B, M MVI Rd, data M, data Move immediate 8- bit The 8-bit data is stored in the destination register or memory. If the operand is a memory location, its location is specified by the contents of the HL registers. Example: MVI B, 57H or MVI M, 57H LDA 16-bit address Load accumulator The contents of a memory location, specified by a 16-bit address in the operand, are copied to the accumulator. The contents of the source are not altered. Example: LDA 2034H LDAX B/D Reg. pair Load accumulator indirect The contents of the designated register pair point to a memory location. This instruction copies the contents of that memory location into the accumulator. The contents of either the register pair or the memory location are not altered. 16

17 LXI LHLD Reg. pair, 16- bit data 16-bit address Load register pair immediate Load H and L registers direct Example: LDAX B The instruction loads 16-bit data in the register pair designated in the operand. Example: LXI H, 2034H or LXI H, XYZ The instruction copies the contents of the memory location pointed out by the 16-bit address into register L and copies the contents of the next memory location into register H. The contents of source memory locations are not altered. Example: LHLD 2040H STA 16-bit address 16-bit address The contents of the accumulator are copied into the memory location specified by the operand. This is a 3-byte instruction, the second byte specifies the low-order address and the third byte specifies the high-order address. STAX SHLD Reg. pair 16-bit address Store accumulator indirect Store H and L registers direct Example: STA 4350H The contents of the accumulator are copied into the memory location specified by the contents of the operand (register pair). The contents of the accumulator are not altered. Example: STAX B The contents of register L are stored into the memory location specified by the 16-bit address in the operand and the contents of H register are stored into the next memory location by incrementing the operand. The contents of registers HL are not altered. This is a 3-byte instruction, the second byte specifies the low-order address and the third byte specifies the high-order address. Example: SHLD 2470H XCHG none Exchange H and L with D and E The contents of register H are exchanged with the contents of register D, and the contents of register L are exchanged with the contents of register E. Example: XCHG 17

18 SPHL none Copy H and L registers to the stack pointer The instruction loads the contents of the H and L registers into the stack pointer register, the contents of the H register provide the high-order address and the contents of the L register provide the loworder address. The contents of the H and L registers are not altered. Example: SPHL XTHL none Exchange H and L with top of stack The contents of the L register are exchanged with the stack location pointed out by the contents of the stack pointer register. The contents of the H register are exchanged with the next stack location (SP+1); however, the contents of the stack pointer register are not altered. Example: XTHL PUSH Reg. pair Push register pair onto stack The contents of the register pair designated in the operand are copied onto the stack in the following sequence. The stack pointer register is decremented and the contents of the highorder register (B, D, H, A) are copied into that location. The stack pointer register is decremented again and the contents of the low-order register (C, E, L, flags) are copied to that location. Example: PUSH B or PUSH A POP Reg. pair Pop off stack to register pair The contents of the memory location pointed out by the stack pointer register are copied to the low-order register (C, E, L, status flags) of the operand. The stack pointer is incremented by 1 and the contents of that memory location are copied to the high-order register (B, D, H, A) of the operand. The stack pointer register is again incremented by 1. OUT 8-bit port address Output data from accumulator to a port with 8- bit address Example: POP H or POP A The contents of the accumulator are copied into the I/O port specified by the operand. Example: OUT F8H 18

19 IN 8-bit port address Input data to accumulator from a port with 8-bit address The contents of the input port designated in the operand are read and loaded into the accumulator. Example: IN 8CH ARITHMETIC INSTRUCTIONS Opcode ADD Operand R M Explanation of Instruction Add register or memory, to accumulator Description The contents of the operand (register or memory) are added to the contents of the accumulator and the result is stored in the accumulator. If the operand is a memory location, its location is specified by the contents of the HL registers. All flags are modified to reflect the result of the addition. ADC ADI ACI LXI R M 8-bit data 8-bit data Reg. pair, 16- Add register to accumulator with carry Add immediate to accumulator Add immediate to accumulator with carry Load register pair Example: ADD B or ADD M The contents of the operand (register or memory) and M the Carry flag are added to the contents of the accumulator and the result is stored in the accumulator. If the operand is a memory location, its location is specified by the contents of the HL registers. All flags are modified to reflect the result of the addition. Example: ADC B or ADC M The 8-bit data (operand) is added to the contents of the accumulator and the result is stored in the accumulator. All flags are modified to reflect the result of the addition. Example: ADI 45H The 8-bit data (operand) and the Carry flag are added to the contents of the accumulator and the result is stored in the accumulator. All flags are modified to reflect the result of the addition. Example: ACI 45H The instruction loads 16-bit data in the register 19

20 bit data immediate pair designated in the operand. DAD SUB SBB SUI SBI INR Reg. pair R M R M 8-bit data 8-bit data R M Add register pair to H and L registers Subtract register or memory from accumulator Subtract source and borrow from accumulator Subtract immediate from accumulator Subtract immediate from accumulator with borrow Increment register or memory by Example: LXI H, 2034H or LXI H, XYZ The 16-bit contents of the specified register pair are added to the contents of the HL register and the sum is stored in the HL register. The contents of the source register pair are not altered. If the result is larger than 16 bits, the CY flag is set. No other flags are affected. Example: DAD H The contents of the operand (register or memory ) are subtracted from the contents of the accumulator, and the result is stored in the accumulator. If the operand is a memory location, its location is specified by the contents of the HL registers. All flags are modified to reflect the result of the subtraction. Example: SUB B or SUB M The contents of the operand (register or memory ) and M the Borrow flag are subtracted from the contents of the accumulator and the result is placed in the accumulator. If the operand is a memory location, its location is specified by the contents of the HL registers. All flags are modified to reflect the result of the subtraction. Example: SBB B or SBB M The 8-bit data (operand) is subtracted from the contents of the accumulator and the result is stored in the accumulator. All flags are modified to reflect the result of the subtraction. Example: SUI 45H The contents of register H are exchanged with the contents of register D, and the contents of register L are exchanged with the contents of register E. Example: XCHG The contents of the designated register or memory) are incremented by 1 and the result is stored in the same place. If the operand is a 20

21 INX DCR DCX DAA R R M R none 1 memory location, its location is specified by the contents of the HL registers. Increment register pair by 1 Decrement register or memory by 1 Decrement register pair by 1 Decimal adjust accumulator Example: INR B or INR M The contents of the designated register pair are incremented by 1 and the result is stored in the same place. Example: INX H The contents of the designated register or memory are M decremented by 1 and the result is stored in the same place. If the operand is a memory location, its location is specified by the contents of the HL registers. Example: DCR B or DCR M The contents of the designated register pair are decremented by 1 and the result is stored in the same place. Example: DCX H The contents of the accumulator are changed from a binary value to two 4-bit binary coded decimal (BCD) digits. This is the only instruction that uses the auxiliary flag to perform the binary to BCD conversion, and the conversion procedure is described below. S, Z, AC, P, CY flags are altered to reflect the results of the operation. If the value of the low-order 4-bits in the accumulator is greater than 9 or if AC flag is set, the instruction adds 6 to the low-order four bits. If the value of the high-order 4-bits in the accumulator is greater than 9 or if the Carry flag is set, the instruction adds 6 to the high-order four bits. Example: DAA BRANCHING INSTRUCTIONS Opcode Operand Explanation of Description 21

22 JMP 16-bit address Instruction Jump unconditionally The program sequence is transferred to the memory location specified by the 16-bit address given in the operand. Example: JMP 2034H or JMP XYZ Opcode Description Flag Status JC Jump on Carry CY = 1 JNC Jump on no Carry CY = 0 JP JM JZ JNZ Jump on positive Jump on minus Jump on zero Jump on no zero S = 0 S = 1 Z = 1 Z = 0 16-bit address Jump conditionally The program sequence is transferred to the memory location specified by the 16-bit address given in the operand based on the specified flag of the PSW as described below. Example: JZ 2034H or JZ XYZ JPE Jump on parity even P = 1 JPO Jump on parity odd P = 0 Opcode Description CC CNC CP CM CZ Call on Carry Call on no Carry Call on positive Call on minus Call on zero Flag Status CY = 1 CY = 0 S = 0 S = 1 Z = 1 16-bit address Unconditional subroutine call The program sequence is transferred to the memory location specified by the 16-bit address given in the operand. Before the transfer, the address of the next instruction after CALL (the contents of the program counter) is pushed onto the stack. Example: CALL 2034H or CALL XYZ 22

23 CNZ CPE CPO Call on no zero Call on parity even Call on parity odd Z = 0 P = 1 P = 0 RET none Return from subroutine unconditionally The program sequence is transferred from the subroutine to the calling program. The two bytes from the top of the stack are copied into the program counter,and program execution begins at the new address. Example: RET Opcode Description Flag Status RC Return on Carry CY = 1 RNC RP RM RZ RNZ RPE Return on no Carry Return on positive Return on minus Return on zero Return on no zero Return on parity even CY = 0 S = 0 S = 1 Z = 1 Z = 0 P = 1 none Return from subroutine conditionally The program sequence is transferred from the subroutine to the calling program based on the specified flag of the PSW as described below. The two bytes from the top of the stack are copied into the program counter, and program execution begins at the new address. Example: RZ RPO Return on parity odd P = 0 PCHL none Load program counter with HL contents The contents of registers H and L are copied into the program counter. The contents of H are placed as the high-order byte and the contents of L as the 23

24 low-order byte. Example: PCHL The RST instruction is equivalent to a 1-byte call instruction to one of eight memory locations depending upon the number. The instructions are generally used in conjunction with interrupts and inserted using external hardware. However these can be used as software instructions in a program to transfer program execution to one of the eight locations. The addresses are: RST 0-7 Restart Instruction Restart Address RST 0 RST1 RST 2 RST 3 RST 4 RST 5 RST 6 RST H 0008H 0010H 0018H 0020H 0028H 0030H 0038H The 8085 has four additional interrupts and these interrupts generate RST instructions internally and thus do not require any external hardware. These instructions and their Restart addresses are: Interrupt Restart Address TRAP RST H 002CH 24

25 RST 6.5 RST H 003CH LOGICAL INSTRUCTIONS Opcode Operand R CMP M Explanation of Instruction Compare register or memory with accumulator Description The contents of the operand (register or memory) are M compared with the contents of the accumulator. Both contents are preserved. The result of the comparison is shown by setting the flags of the PSW as follows: if (A) < (reg/mem): carry flag is set if (A) = (reg/mem): zero flag is set if (A) > (reg/mem): carry and zero flags are reset CPI ANA 8-bit data R M Compare immediate with accumulator Logical AND register or memory with accumulator Example: CMP B or CMP M The second byte (8-bit data) is compared with the contents of the accumulator. The values being compared remain unchanged. The result of the comparison is shown by setting the flags of the PSW as follows: if (A) < data: carry flag is set if (A) = data: zero flag is set if (A) > data: carry and zero flags are reset Example: CPI 89H The contents of the accumulator are logically ANDed with M the contents of the operand (register or memory), and the result is placed in the accumulator. If the operand is a memory location, its address is specified by the contents of HL registers. S, Z, P are modified to reflect the result of the operation. CY is 25

26 reset. AC is set. Example: ANA B or ANA M ANI 8-bit data Logical AND immediate with accumulator The contents of the accumulator are logically ANDed with the 8-bit data (operand) and the result is placed in the accumulator. S, Z, P are modified to reflect the result of the operation. CY is reset. AC is set. XRA XRI ORA ORI RLC R M 8-bit data R M 8-bit data none Exclusive OR register or memory with accumulator Exclusive OR immediate with accumulator Logical OR register or memory with accumulator Logical OR immediate with accumulator Rotate accumulator left Example: ANI 86H The contents of the accumulator are Exclusive ORed with M the contents of the operand (register or memory), and the result is placed in the accumulator. If the operand is a memory location, its address is specified by the contents of HL registers. S, Z, P are modified to reflect the result of the operation. CY and AC are reset. Example: XRA B or XRA M The contents of the accumulator are Exclusive ORed with the 8-bit data (operand) and the result is placed in the accumulator. S, Z, P are modified to reflect the result of the operation. CY and AC are reset. Example: XRI 86H The contents of the accumulator are logically ORed with M the contents of the operand (register or memory), and the result is placed in the accumulator. If the operand is a memory location, its address is specified by the contents of HL registers. S, Z, P are modified to reflect the result of the operation. CY and AC are reset. Example: ORA B or ORA M The contents of the accumulator are logically ORed with the 8-bit data (operand) and the result is placed in the accumulator. S, Z, P are modified to reflect the result of the operation. CY and AC are reset. Example: ORI 86H Each binary bit of the accumulator is rotated left by one position. Bit D7 is placed in the position of D0 as well as in the Carry flag. CY is modified according to bit D7. 26

27 RRC RAL RAR CMA CMC none none none none none Rotate accumulator right Rotate accumulator left through carry Rotate accumulator right through carry Complement accumulator Complement carry STC none Set Carry S, Z, P, AC are not affected. Example: RLC Each binary bit of the accumulator is rotated right by one position. Bit D0 is placed in the position of D7 as well as in the Carry flag. CY is modified according to bit D0. S, Z, P, AC are not affected. Example: RRC Each binary bit of the accumulator is rotated left by one position through the Carry flag. Bit D7 is placed in the Carry flag, and the Carry flag is placed in the least significant position D0. CY is modified according to bit D7. S, Z, P, AC are not affected. Example: RAL Each binary bit of the accumulator is rotated right by one position through the Carry flag. Bit D0 is placed in the Carry flag, and the Carry flag is placed in the most significant position D7. CY is modified according to bit D0. S, Z, P, AC are not affected. Example: RAR The contents of the accumulator are complemented. No flags are affected. Example: CMA The Carry flag is complemented. No other flags are affected. Set Carry Example: CMC Example: STC CONTROL INSTRUCTIONS Opcod e NOP Operan d none Explanatio n of Instruction No operation Description No operation is performed. The instruction is fetched and decoded. However no operation is executed. 27

28 Example: NOP HLT none Halt and enter wait state The CPU finishes executing the current instruction and halts any further execution. An interrupt or reset is necessary to exit from the halt state. Example: HLT DI none Disable interrupts The interrupt enable flip-flop is reset and all the interrupts except the TRAP are disabled. No flags are affected. Example: DI EI none Enable interrupts The interrupt enable flip-flop is set and all interrupts are enabled. No flags are affected. After a system reset or the acknowledgement of an interrupt, the interrupt enable flipflop is reset, thus disabling the interrupts. This instruction is necessary to reenable the interrupts (except TRAP). Example: EI This is a multipurpose instruction used to read the status of interrupts 7.5, 6.5, 5.5 and read serial data input bit. The instruction loads eight bits in the accumulator with the following interpretations. RIM none Read interrupt mas Example: RIM SIM none Set interrupt mask This is a multipurpose instruction and used to implement the 8085 interrupts 7.5, 6.5, 5.5, and serial data output. The instruction interprets the accumulator contents as follows. Example: SIM 28

29 7. The 8085 Addressing Modes The instructions MOV B, A or MVI A, 82H are to copy data from a source into a destination. In these instructions the source can be a register, an input port, or an 8-bit number (00H to FFH). Similarly, a destination can be a register or an output port. The sources and destination are operands. The various formats for specifying operands are called the ADDRESSING MODES. For 8085, they are: 1. Immediate addressing. 2. Register addressing. 3. Direct addressing. 4. Indirect addressing. Immediate addressing Data is present in the instruction. Load the immediate data to the destination provided. Example: MVI R,data 29

30 Register addressing Data is provided through the registers. Example: MOV Rd, Rs Direct addressing Used to accept data from outside devices to store in the accumulator or send the data stored in the accumulator to the outside device. Accept the data from the port 00H and store them into the accumulator or Send the data from the accumulator to the port 01H. Example: IN 00H or OUT 01H Indirect Addressing This means that the Effective Address is calculated by the processor. And the contents of the address (and the one following) is used to form a second address. The second address is where the data is stored. Note that this requires several memory accesses; two accesses to retrieve the 16-bit address and a further access (or accesses) to retrieve the data which is to be loaded into the register. Self check 1: how will you design your own REGISTER using the digital techniques which you have studied in digital electronics 1)Compare XRA A and MVI A,00 2)LDA 5000! which flag will be affected? 30

31 8.TIMING DIAGRAM OF 8085 INSTRUCTIONS MEMORY WRITE MACHINE CYCLE OF 8085: The memory write machine cycle is executed by the processor to write a data byte in a memory location. The processor takes 3T states to execute this machine cycle. I/O Read Cycle of 8085: Fig - Timing Diagram for Memory Write Machine Cycle The I/O Read cycle is executed by the processor to read a data byte from I/O port or from the peripheral, which is I/O, mapped in the system. The processor takes 3T states to execute this machine cycle. The IN instruction uses this machine cycle during the execution. I/O Write Cycle of 8085: Fig - Timing Diagram for I/O Read Machine Cycle 31

32 The I/O write machine cycle is executed by the processor to write a data byte in the I/O port or to a peripheral, which is I/O, mapped in the system. The processor takes, 3T states to execute this machine cycle. Timing diagram for MVI B, 43H. Fig - Timing Diagram for I/O Write Machine Cycle Fetching the Opcode 06H from the memory 2000H. (OF machine cycle) Read (move) the data 43H from memory 2001H. (memory read) Timing diagram for INR M 32

33 Fetching the Opcode 34H from the memory 4105H. (OF cycle) Let the memory address (M) be 4250H. (MR cycle -To read Memory address and data) Let the content of that memory is 12H. Increment the memory content from 12H to 13H. (MW machine cycle) The 8085 instructions consist of one to five machine cycles. Actually the execution of an instruction is the execution of the machine cycles of that instruction in the predefined order. The timing diagram of an instruction ate obtained by drawing the timing diagrams of the machine cycles of that instruction, one by one in the order of execution. Timing diagram for IN C0H. Fetching the Opcode DBH from the memory 4125H. Read the port address C0H from 4126H. Read the content of port C0H and send it to the accumulator. Let the content of port is 5EH. Timing diagram for STA 526AH. Fig - Timing Diagram for Opcode Fetch Machine Cycle STA means Store Accumulator -The contents of the accumulator is stored in the specified address(526a). The opcode of the STA instruction is said to be 32H. It is fetched from the memory 41FFH(see fig). - OF machine cycle Then the lower order memory address is read(6a). - Memory Read Machine Cycle Read the higher order memory address (52).- Memory Read Machine Cycle The combination of both the addresses are considered and the content from accumulator is written in 526A. - Memory Write Machine Cycle Assume the memory address for the instruction and let the content of accumulator is C7H. So, C7H from accumulator is now stored in 526A. 33

34 34

35 Self check 2: 1.What are the pins used for nterrupts in 8085, 2.Will the clock frequency change the machine cycle? 3.mention the machine cycles of sta 2506 and shld Sample Programs Write an assembly program to add two numbers Program MVI D, 8BH MVI C, 6FH MOV A, C ADD D OUT PORT1 HLT Write an assembly program to multiply a number by 8 35

36 Program MVI A, 30H RRC RRC RRC OUT PORT1 HLT Write an assembly program to find greatest between two numbers Program MVI B, 30H MVI C, 40H MOV A, B CMP C JZ EQU JC GRT OUT PORT1 HLT EQU: MVI A, 01H OUT PORT1 HLT GRT: MOV A, C OUT PORT1 HLT SELF CHECK 3 FOR THE ABOVE PROGRAMS,FIND THE TIME REQUIRED TO EXECUTE THE PROGRAM!! 1.RST 7.5 refers to 3.what is the clock frequency of 8085? 4.What is the maximum number of I/O devices can be connected with

37 Key Terms A Accumulator2 Addressing Modes29 Architecture2 Arithmetic instruction 19 ALE 8 B Branch instruction 21 C Control bus6 CLK 10 Control instruction 27 D DATA bus 6 Data transfer instruction 16 F FLAGS 3 KEY TERM QUIZ I Instructions16 Interrupts 9 INTA Interrupt Acknowledge5 L Logical instruction 25 P Pin description 7 Program Counter4 R REGISTERS3 RESTART INTERRUPTS9 RESET 10 S Stack Pointer 4 System Bus 5 System Timing12 T Timing Diagram 31 X X1,X What is the purpose of pin X1 and X2? 2.stack pointer is a bit register. 3. sign flag will be affected by data transfer instructions?yes/no 4. ldax b what type of addressing mode 5. HL register is a bit register? 6. The number of flags in 8085 is 7. ALE pin r s low during multiplexing of higher order address say yes/no 8. The SOD and SID are used for 9. The clock frequency of 8085 is 10. MVI B,20 no of bytes of the instruction is

38 OBJECTIVE TYPE QUESTIONS 1. In Synchronous data Transfer type both Transmitter and Receiver will operate in a) Same Clock pulse b) Different Clock pulse c) None of the above 2. The term PSW Program Status word refers a) Accumulator & Flag register b) H and L register c) Accumulator & Instruction register d) B and C register 3. In 8085 the MAR, or?.. register, latches the address from the program counter. A bit later the MAR applies this address to the??, where a read operations performed a) Memory address, ROM b) Memory address, RAM c) Memory address, PROM d) Memory address EPROM 4. In micro? processors like 8080 and the 8085, the?..cycle may have from one to live machine cycle a) micro? instruction b) source program c) instruction d) fetch cycle 5. Repeated addition is one way to do multiplication, programmed multiplication is used in most microprocessors because a) that ALU?s can only add and subtract b) this saves on memory c) a separate set of instructions is needed for the two d) None of the above. 6. A is used to isolate a bit, it does this because that ANI sets all other bits to Zero a) subroutine b) flag c) label d) mask 7. Interaction between a CPU and a peripheral device that takes place during and imput output operation is known as a) handshaking b) flagging 38

39 c) relocating d) sub?routine 8. Addressing in which the instructions contains the address of the data to the operated on is known as a) immediate addressing b) implied addressing c) register addressing d) direct addressing 9. Resart is a special type of CALL in which a) the address is programmed but not built into the hardware b) the address is programmed built into the hardware c) the address is not programmed but built into the hardware d) None of the above has?? software restarts and?.. hardware restarts a) 10, 5 b) 8,4 c) 7,5 d) 6,6 11. Serial input data of 8085 can be loaded into bit 7 of the accumulator by a) executing a RIM instruction b) executing RST1 c) using TRAP c) None of the above 12. The address to which a software or hardware restart branches is known as a) vector location b) SID c) SOD d) TRAP 13. TRAP is?..whereas RST 7.5, RST 6.5, RST 5.5 are?. a) maskable, non maskable b) maskable, maskable c) non - maskable, non? maskable d) non - maskable, maskable 14. micro processor with a 16? bit address bus is used in a linear memory selection configuration address bus lines are directly used as chip selects of memory chips with four memory chips. The maximum addressable memory space is a) 64K b) 16 K c) 8K 39

40 d) 4K 15. How many outputs are there in the output of a 10-bit D/A converter? a) 1000 b) 1023 c) 1024 d) The stack is a specialized temporary?? access memory during?.. and?? instructions a) random, store, load b) random, push, load c) sequential, store, pop d) sequential, push, pop 17. The memory address of the last location of a 1K byte memory chip is given as OFBFFH what will be the address of the first location? a) OF817H b) OF818H c) OF8OOH d) OF801H 18. What is the direction of address bus? a) Uni? directional into microprocessors b) Uni? directional out of microprocessors c) Bi? directional d) mixed direction is when lines into micro processor and some other out of micro processes. 19. The No. of control lines are The length of A? register is - bits 21. The length of program counter is bits 22. The length of stack pointer is bits 23. The length of status word is - bits 24. The length of temporary register - bits 25. The length of Data buffer register - bits 26. The No. of flags are The No. of interrupts are The memory word addressing capability is K 40