CS 251, Winter 2018, Assignment % of course mark

Transcription

1 CS 25, Winter 28, Assignment 3.. 3% of corse mark De onday, Febrary 26th, 4:3 P Lates accepted ntil : A, Febrary 27th with a 5% penalty. IEEE 754 Floating Point ( points): (a) (4 points) Complete the following table, showing the sign & magnitde and the corresponding biased representations with a bias of 27. Sign & agnitde 99 2 Biased (b) (6 points) the base 2 nmber. as a 32-bit, IEEE normalized floating point nmber with biased eponent

2 2. (5 points) Consider the single-cycle compter shown on page 6 of this assignment. Sppose the circit elements take the following times: Instr mem: 2ps, Register read: 3ps, Register write: 3ps, and all adders: 5ps, Data : 2ps, Control Unit: ps, Shift Left Units: 5 Assme that PC and UXes don t take any time. Compte the minimm eection time for each instrction type below: R-format: LW: SW: Branch: Jmp: 3. (8 points) Consider the assembly langage instrction at address 256: 256: add $3,$6,$4 In the figre on the net page, there are eight darks lines. On each line, write in the vale that travels along the corresponding wire(s) when eecting this assembly langage instrction. Note: yo shold write a decimal nmber on each dark line, and not an epression involving things like PC, etc. (Some nmbers are more natral to write in binary; for any binary nmbers yo se, yo shold sbscript them with a 2 like 2.) Assme that each register $i (with i > ) contains the decimal vale 4 + i. Frther assme that the shamt field of this R-format instrction is. 2

3 (Qestion 2, contined) PC Add 4 address Instrction Instrction [3 ] Instrction [3 26] Instrction [25 2] Instrction [2 6] Instrction [5 ] Instrction [5 ] Control RegDst Branch em emtoreg Op em Src Reg register register 2 register Registers Sign etend Instrction [5 ] Shift left 2 control Add reslt Zero reslt Address Data PCSrc 3

4 4. (5 pts) Consider the following IPS assembly langage instrctions: addi $, $2, : swr $, ($2): addi $rt, $rs, immediate # add immediate swr $rt, immediate($rs) # store word write register These instrctions are I-format instrctions similar to the load word and store word instrctions. The addi and swr instrctions store a compted vale to the destination register $rt. The instrctions do not reqire any physical hardware changes to the path. The effect of each instrction is given below. Fill in the table below indicating the vale of all eisting control lines necessary to eecte the addi and swr instrctions on the path. Yo mst se don t cares where appropriate. The swr instrction stores to and writes to the register file. It stores to at address [$rs+$rt] the vale contained in $rt. Also, it takes the sm of the $rs and $rt registers and writes the reslt to register $rt. The new vale of $rt is pdated at the end of the clock cycle. addi: $rt <= se immediate + $rs swr: E[$rs+$rt] <= $rt, $rt <= $rs + $rt Type Reg em Reg em em Branch Dst Src ToReg op op R-format lw sw X X beq X X addi swr 4

5 5. ( pts) We want to modify the single-cycle compter to implement a new instrction in the path. The mimm or immediate instrction is an I-format instrction. The form of this IPS instrction is mimm rt, offset(rs) This instrction comptes the sm of the signed etended offset and rs, and stores this at the address stored in rt. em[rt] <= se offset + rs (a) (6 pts) odify the Single Cycle path on the net page in order to implement the mimm instrction. Yo may add mltipleors, control bits and additional components as needed. arks will also be awarded for the efficiency of the soltion. Be sre that all other IPS instrctions eecting on the path will still work. Smmarize yor changes to the path below, and make the modifications to the path provided on the net page. (b) (4 pts) In the table below, give the settings of the control bits to implement the new mimm IPS instrction. Use Don t Cares where appropriate. If yo need an etra control line to implement this instrction or if yo need to increase the nmber of bits in a control line, add additional colmns to the table for the new control line, split a colmn to increase the nmber of bits in a control line, and in either case inclde a note below eplaining the effect of the new/increased control line(s) on the path and what its setting shold be for other instrctions. ake sre yo do not break any other instrctions. Yo shold be able to determine the prpose and effects of each of the control signals from the Single Cycle path on the net page. Type Reg em Reg em em Branch Dst Src ToReg op op mimm State the vale(s) of any new control signal(s) for other IPS instrctions: 5

6 PC Add 4 address Instrction Instrction [3 ] Instrction [25 ] Shift Jmp address [3 ] left PC+4 [3 28] Instrction [3 26] Control RegDst Jmp Branch em emtoreg Op em Src Reg Instrction [25 2] Instrction [2 6] Instrction [5 ] register register 2 register Registers 2 Instrction [5 ] 6 32 Sign etend Instrction [5 ] Shift left 2 control Add reslt Zero reslt Address Data 6

7 Additional eercises on single-cycle architectre: The rest of the corse will focs on improvements to the single-cycle architectre. Before proceeding, yo may wish to do some additional eercises from the tetbook (nmarked, soltions not provided): Eercise 3.2 Eercise 4. Eercise 4.2 Eercise 4.3 7