CO Computer Architecture and Programming Languages CAPL. Lecture 13 & 14

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1 CO Computer Architecture and Programming Languages CAPL Lecture 13 & 14 Dr. Kinga Lipskoch Fall 2017

2 Frame Pointer (1) The stack is also used to store variables that are local to function, but do not fit into registers local arrays, structures The segment of the stack containing function s saved registers is called procedure frame or function frame A frame pointer ($fp) points to the first word of the frame of a function $sp might change during function $fp is a stable base register within a function for local memory references CAPL Fall / 44

3 Frame Pointer (2) High address $fp $sp $fp $sp... $fp $sp Saved argument registers Saved return address Saved saved registers Local arrays and structures Low address a) b) c) CAPL Fall / 44

4 Memory: Heap Stack starts at high end and grows downwards First part of low end is reserved Then text segment executable machine code Above static data segment constants and variables Dynamic data such as arrays in lists are placed in the heap malloc(), free() Thus stack and heap grow towards each other $sp 0x7ffffffc $gp 0x x PC 0x Stack Heap (dynamic data) Static data Text 0 Reserved CAPL Fall / 44

5 MIPS assembly language Category Instruction Example Meaning Comments Arithmetic add add $s1, $s2, $s3 $s1 = $s2 + $s3 Three operands, data in register subtract sub $s1, $s2, $s3 $s1 = $s2 $s3 Three operands, data in register add immediate addi $s1, $s2, 100 $s1 = $s Used to add constants Data transfer Conditional Branch Unconditional Jump load word lw $s1, 100($s2) $s2 = Memory($s ) Data from memory to register store word sw $s1, 100($s2) Memory($s ) = $s2 Data from register to memory branch on equal beq $1, $2, L if ($1 == $2) goto L Equal test and branch branch on not eq. bne $1, $2, L if ($1!= $2) goto L Not equal test and branch set on less than slt $t0, $s2, $s3 if ($s2 < $s3) $t0 = 1 else $t0 = 0 Compare less than; for beq; bne jump j LABEL goto LABEL Jump to LABEL (target address) jump register jr $ra goto $ra For switch, procedure return jump and link jal LABEL $31 = PC + 4; goto LABEL For procedure call MIPS machine language Name Format Example Comments add R add $s1, $s2, $s3 sub R sub $s1, $s2, $s3 addi I addi $s1, $s2, 100 lw I lw $s1, 100($s2) sw I sw $s1, 100($s2) beq I beq $1, $2, 100 bne I bne $1, $2, 100 slt R slt $1, $2, $3 j J j jr R jr $31 jal J jal Field size 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits All MIPS instructions 32 bits R-format R op rs rt rd shamt funct Arithmetic instruction format I-format I op rs rt constant or 16 bit address Data transfer format J-format J op 26 bit address Jump format CAPL Fall / 44

6 Limitations in Addressing Jump register 32 bit register - 32 bit address Jump address 6 bits for the jump op-code 26 bits for the address Branch 16 bits for the branch op-code & registers 16 bits for the address First idea: limitation of branch space to the first 2 16 bits Word address instead of byte address additional 2 bits, rest comes from PC CAPL Fall / 44

7 Relative Addressing (1) Combination of a base register and the address in the branch operation PC = register + branch address Reference is the Program Counter, PC Relative jumps & branches No serious restriction High probability of the target being in the range of PC 50% of branch destinations in SPEC benchmark are less than 16 instructions away CAPL Fall / 44

8 Relative Addressing (2) Program Counter Memory Addressable space relative to PC For larger distances: Jump register required CAPL Fall / 44

9 Addressing in Branches and Jumps Branches use PC - relative addressing destination = PC word address Jump uses also word addressing first 4 bits of PC destination = PC[0 : 3] + word address (+=concatenate) Branching in machine language and machine code PC Machine Code Machine Language Comments Loop: sll $t1, $s3, 2 # reg $t1 = 4 * i add $t1, $t1, $s6 # $t1 = &save[i] lw $t0, 0($t1) # reg $t0 = save[i] bne $t0, $s5, Exit addi $s3, $s3, 1 # i = i j Loop # go to Loop Exit: # go to Exit # if save[i] k CAPL Fall / 44

10 Branching Far Away Replace 1 beq $s0, $s1, L1 By pair of instructions: 1 bne $s0, $s1, L2 2 j L1 3 L2: CAPL Fall / 44

11 Addressing Modes (1) Immediate addressing, addi Operand is constant Register addressing, e.g., add Operand is a register Base or Displacement addressing, e.g., lw Operand is in the memory Address is sum of register + address in instruction PC-relative addressing, e.g., beq (branch) address is sum of PC and constant of instruction (16-bit address shifted left 2 bits) Pseudo-direct addressing j jump address is the 26 bits shifted left 2 bits of the instruction concatenated with 4 upper bits of PC CAPL Fall / 44

12 Addressing Modes (2) Immediate addressing op rs rt Register Immediate Register addressing op rs rt rd... func Register Base or displacement addressing op rs rt Address Register + Memory Word CAPL Fall / 44

13 Addressing Modes (3) PC-relative addressing op rs rt Address PC + Memory Word Pseudo-direct addressing op Address PC : Memory Word CAPL Fall / 44

14 Non-MIPS Addressing Modes MIPS: add register register register add register register immediate Other: add register, register, memory add register, memory, memory add memory, memory, memory... Memory access: immediate relative indexed CAPL Fall / 44

15 Remarks Various instruction types (selection) Logical operations Arithmetic operations Branches & jumps Addressing modes Immediate Register Relative (register or PC) CAPL Fall / 44

16 Assembly Language vs. Machine Language Assembly provides convenient symbolic representation much easier than writing down numbers e.g., destination first Machine language is the underlying reality e.g., destination is no longer first Assembly can provide pseudo-instructions e.g., move $t0, $t1 exists only in assembly would be implemented using add $t0, $t1, $zero When considering performance you should count real instructions CAPL Fall / 44

17 Array vs. Pointers (1) 1 void clear_ 1 ( int array [], int size ) { 2 int i; 3 for ( i = 0; i < size ; i += 1) 4 array [i] = 0; 5 } 1 void clear_ 2 ( int * array, int size ) { 2 int *p; 3 for (p = & array [0]; p < & array [ size ]; p ++) { 4 *p = 0; 5 } CAPL Fall / 44

18 Array vs. Pointer (2) Code assumes size > 0 Array 1 move $t0, $zero # i = 0 2 loop1 : sll $t1, $t0, 2 # $t1 = i * 4 3 add $t2, $a0, $t1 # $t2 = & array [ i] 4 sw $zero, 0( $t2 ) # array [ i] = 0 5 addi $t0, $t0, 1 # i ++ 6 slt $t3, $t0, $a1 # $t3 = ( i < size ) 7 bne $t3, $zero, loop1 Pointer 1 move $t0, $a0 # p = & array [0] 2 sll $t1, $a1, 2 # $t1 = size * 4 3 add $t2, $a0, $t1 # $t2 = & array [ size ] 4 loop2 : sw $zero, 0( $t0 ) # Memory [ p] = 0 5 addi $t0, $t0, 4 # p ++ ( addr += 4) 6 slt $t3, $t0, $t2 # $t3 =(p < & array [ size ]) 7 bne $t3, $zero, loop2 CAPL Fall / 44

19 Array vs. Pointer (3) Array multiply and add inside loop address is recalculated from new index Pointer increments pointer directly less instructions inside loop Modern compilers might produce the same assembler code for both versions CAPL Fall / 44

20 Alternative Architectures Design alternative: provide more powerful operations goal is to reduce number of instructions executed danger is a slower cycle time and/or a higher CPI The path toward operation complexity is thus fraught with peril. To avoid these problems, designers have moved toward simpler instructions. Let s briefly look at IA-32 CAPL Fall / 44

21 IA : The Intel 8086 is announced (16 bit architecture) 1980: The 8087 floating point coprocessor is added 1982: The increases address space to 24 bits + instructions 1985: The extends to 32 bits, new addressing modes The 80486, Pentium, Pentium Pro add a few instructions (mostly designed for higher performance) 1997: 57 new MMX instructions are added, Pentium II 1999: The Pentium III added another 70 instructions (SSE) 2001: Another 144 instructions (SSE2) 2003: AMD extends the architecture to increase address space to 64 bits, widens all registers to 64 bits and other changes (AMD64) 2004: Intel capitulates and embraces AMD64 (calls it EM64T) and add more media extensions This history illustrates the impact of the golden handcuffs of compatibility adding new features as someone might add clothing to a packed bag an architecture that is difficult to explain and impossible to love CAPL Fall / 44

22 IA-32 Overview Complexity: Instructions from 1 to 17 bytes long One operand must act as both a source and destination One operand can come from memory Complex addressing modes, e.g., base or scaled index with 8 or 32 bit displacement Saving grace: The most frequently used instructions are not too difficult to build Compilers avoid the portions of the architecture that are slow what the 80x86 lacks in style is made up in quantity, making it beautiful from the right perspective CAPL Fall / 44

23 IA-32 Addressing (80386) 31 0 EAX GPR 0 ECX GPR 1 EDX GPR 2 EBX GPR 3 ESP GPR 4 EBP GPR 5 ESI GPR 6 EDI GPR 7 EIP EFLAGS CS Code segment pointer SS Stack segment pointer DS Data segment pointer 0 ES Data segment pointer 1 FS Data segment pointer 2 GS Data segment pointer 3 Instruction Pointer Condition Codes CAPL Fall / 44

24 IA-32 Register Restrictions Registers are not general purpose note the restrictions below IA32 register restriction Register Mode Description restrictions MIPS equivalent Register indirect Address is in a register not ESP or EBP lw $0, 0($s1) Based mode with 8- or 32-bit displacement Address is contents of base register plus displacement not ESP or EBP lw $s0, 100($s1) # 16 bit # displacement Base plus scaled index The address is Base + (2 Scale x Index) where Scale has the value 0, 1, 2, or 3. Base any GPR Index: not ESP mul $t0, $s2, 4 add $t0, $t0, $s1 lw $s0, 0($t0) Base plus scaled index with 8- or 32-bit displacement The address is Base + (2 Scale x Index) where Scale has the value 0, 1, 2, or 3. Base any GPR Index: not ESP mul $t0, $s2, 4 add $t0, $t0, $s1 lw $s0, 100($t0) # 16 bit # displacement CAPL Fall / 44

25 IA-32 Instruction Formats JE Cond ition Displacement CALL Offset MOV d w Postbyte Displacement PUSH Reg ADD Reg Immediate TEST Postbyte Immediate CAPL Fall / 44

26 IA-32 Typical Instructions Four major types of integer instructions: Data movement including move, push, pop Arithmetic and logical (destination register or memory) Control flow (use of condition codes/flags ) String instructions, including string move and string compare CAPL Fall / 44

27 IA-32 Instructions IA-32 Instructions Instructions Meaning Control Conditional and unconditional branches JNZ, JZ Jump if condition to EIP + 8- bit offset JMP Unconditionial jump 8-bit or 16-bit offset CALL Subroutine call 16-bit offset, return address pushed onto stack RET Pops return address from stack and jumps to it LOOP Loop branch decrement ECX, jump to EIP + 8-bit displacement if ECX!= 0 Data transfer Move data between registers or between register and memory MOV Move between registers or between register and memory PUSH, POP Push source operand onto the stack, pop operand from stack top to a register LES Load ES and one of the GPRs from memory Arithmetic, logical Arithmetic and logical operations using the data registers and memory ADD, SUB add source to destination; subtract source from destination; register-memory format CMP Compare source and destination, register memory format SHL, SHR, RCR Shift left; shift logical right; rotate right with carry condition code as fill CBW Convert byte in 8 rightmost bits of EAX to 16-bit word in right of EAX TEST Logical AND of source and destination set condition codes INC, DEC Increment destination, decrement destination OR, XOR Logical OR; exclusive OR; register memory-format String Move between string operands; length given by repeat prefix MOVS Copies from string source to destination by incrementing ESI and EDI LODS Loads a byte, word or double of a string into EAX register CAPL Fall / 44

28 Summary Instruction complexity is only one variable Lower instruction count vs. higher CPI/lower clock rate Design principles: Simplicity favors regularity Smaller is faster Good design demands compromise Make the common case fast Instruction set architecture A very important abstraction CAPL Fall / 44

29 MIPS Tools Sourcery CodeBench Lite Edition: sourcery-tools/sourcery-codebench/editions/ lite-edition/ Allows to cross-compile MIPS code Inspect MIPS assembler: mips-linux-gnu-gcc -S -o example.s example.c SPIM simulator: https: //sourceforge.net/p/spimsimulator/code/head/tree/ CAPL Fall / 44

30 32 Bit Integers in MIPS 32 bit signed numbers: = = = = + 2,147,483, = + 2,147,483, = 2,147,483, = 2,147,483, = 2,147,483, = = = 1 10 MAXINT MININT CAPL Fall / 44

31 Detecting Overflow No overflow when adding a positive and a negative number No overflow when signs are the same for subtraction Overflow occurs if the value affects the sign: Adding two positives yields a negative Adding two negatives gives a positive Subtract a negative from a positive and get a negative Subtract a positive from a negative and get a positive CAPL Fall / 44

32 Effects of Overflow Details based on software system/language C ignores integer overflow, Fortran requires program notification Example: flight control vs. homework assignment Computer designer should provide way to detect overflow and ignore overflow add, addi, sub cause exception new MIPS instructions: addu, addiu, subu do not cause exception note: addiu still sign-extends note: sltu, sltiu for unsigned comparisons An exception (interrupt) occurs Control jumps to predefined address for exception Interrupted address is saved for possible resumption CAPL Fall / 44

33 ALU: Arithmetic Logic Unit Brain of the computer We have built a simple ALU that adds Traditional Integer arithmetic (addition, subtraction) (multiplication, division) Support logic operations (and, nor, or, xor) Bit-shifting Extended for MIPS: Support the set-on-less-than instruction (slt) Support test for equality (bne, beq) Use subtraction: (a - b) == 0 implies a = b Detect overflow CAPL Fall / 44

34 Multiply for MIPS Separate pair of 32-bit registers to contain 64-bit product: hi and lo Two instructions: mult, multu Multiply produces a double precision product mult $s0, $s1 # hi lo = $s0 * $s1 Low-order word of the product is left in processor register lo and the high-order word is left in register hi Instructions mfhi rd and mflo rd are provided to move the product to (user accessible) registers in the register file mflo $s1 # $s1 = lo CAPL Fall / 44

35 Division for MIPS Divide generates the remainder in hi and the quotient in lo 1 div $s0, $s1 # lo = $s0 / $s1 2 # hi = $s0 mod $s1 Instructions mfhi rd and mflo rd are provided to move the quotient and remainder to (user accessible) registers in the register file As with multiply, divide ignores overflow so software must determine if the quotient is too large Software must also check the divisor to avoid division by 0 CAPL Fall / 44

36 Multiplication/Division Common hardware support for multiply and divide provides separate pair of 32-bit registers to contain 64-bit product or the remainder/quotient To fetch data from these hi and lo registers programmer uses mflo (move from low) MIPS multiply instructions ignore overflow, up to software to check. (No overflow if hi is 0), mfhi (move from hi) can be used to transfer hi to general-purpose register MIPS divide ignores overflow, up to software to check result and division by 0 CAPL Fall / 44

37 Real Numbers What if we want to encode the approximate age of the earth? 4, 600, 000, 000 or 4.6x10 9 or the weight in kg of one a.m.u. (atomic mass unit) or 1.6x10 27 There is no way we can encode either of the above in a 32-bit integer Floating point representation ( 1) sign x fraction x 2 exponent Still have to fit everything in 32 bits (single precision) CAPL Fall / 44

38 IEEE 754 Floating Point (1) s E (exponent) F (fraction) 1 bit 8 bit 23 bit The base (2, not 10) is hardwired in the design of the FPALU More bits in the fraction (F) or the exponent (E) is a trade-off between precision (accuracy of the number) and range (size of the number) To simplify sorting FP numbers, E comes before F in the word and E is represented in excess (biased) notation IEEE 754 floating point standard: single precision: 8 bit exponent, 23 bit fraction double precision: 11 bit exponent, 52 bit fraction CAPL Fall / 44

39 IEEE 754 Floating Point (2) Form Arbitrary Normalized Binary notation Normalized 1.xxxtwo 2 yy Standardized format IEEE 754 Single precision: 8 bit exp, 23 bit fraction Double precision: 11 bit exp, 52 bit fraction Both formats are supported by MIPS CAPL Fall / 44

40 IEEE 754 Floating Point Standard Leading 1 bit of fraction is implicit Exponent is biased to make sorting easier all 0s is smallest exponent all 1s is largest bias of 127 for single precision and 1023 for double precision summary: ( 1) sign (1 + fraction) 2 exponent bias Example: decimal:.75 = 3/4ten = 11 two /2 2 ten = 0.11 two binary:.11 = 1.1x2 1 floating point: exponent = 126 = IEEE 754 single precision: CAPL Fall / 44

41 Floating Point Complexities Operations are somewhat more complicated In addition to overflow we can have underflow Accuracy can be a big problem: IEEE 754 keeps two extra bits, guard and round four rounding modes positive divided by zero yields infinity zero divide by zero yields not a number other complexities Implementing the standard is difficult Not using the standard can be even worse see text for description of 80x86 and Pentium bug CAPL Fall / 44

42 IEEE 754 Most computers these days conform to the IEEE 754 floating point standard Some bit combinations have special meaning Single Precision E (8) F (23) nonzero anything nonzero Double Precision E (11) F (52) nonzero anything nonzero Object Represented true zero (0) ± denormalized number ± floating point number ± infinity not a number (NaN) CAPL Fall / 44

43 IEEE 754 Specialties Denormalized numbers exponent is 0, fraction non-zero no implicit 1 in front of floating point Example: is e 39 expands range for small numbers reduces risk of underflow CAPL Fall / 44

44 Two Simple Test Programs C construct union shares memory for different representations 1 union ieee754 { 2 float d; 3 unsigned int an_ integer ; 4 }; Allows to convert from one type to another read float and then test each single bit of the variable an_integer str2float.c converts a binary string to floating point number floating.c shows binary representation of floating point number CAPL Fall / 44

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