Federal Urdu University of Arts, Science and Technology, Islamabad VLSI SYSTEM DESIGN. Prepared By: Engr. Yousaf Hameed.

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1 VLSI SYSTEM DESIGN Prepared By: Engr. Yousaf Hameed Lab Engineer BASIC ELECTRICAL & DIGITAL SYSTEMS LAB DEPARTMENT OF ELECTRICAL ENGINEERING VLSI System Design 1

2 LAB 01 Schematic Introduction to DSCH and a simple Gate implementation in DSCH VLSI System Design 2

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7 LAB 02 Schematic CMOS Switch Level Modeling of Basic Gates (Nand, Nor, Xor,Xnor) and Complex Function in DSCH. VLSI System Design 7

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10 LAB 03 Schematic Implementation of Full adder in DSCH at switch level VLSI System Design 10

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12 LAB 04 Layout Introduction to Microwind and analysis of MOSFETS VLSI System Design 12

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19 LAB 05 Layout MOSFET Inverter Characteristics and layout in Microwind (Layer Level Modeling) VLSI System Design 19

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24 LAB 06 Layout Layout of basic gates using 0.25 micron technology in Microwind (Layer level modeling) VLSI System Design 24

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30 LAB 07 Layout Layout of Complex gate using 0.25 micron technology in Microwind (Layer level modeling) VLSI System Design 30

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33 LAB 08 Layout Design and implementation of full adder at layer level in Microwind. VLSI System Design 33

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37 LAB 09 Layout Design and implementation of Static RAM Cell layout using CMOS 0.12 micron technology in Microwind. VLSI System Design 37

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LAB 10 Introduction to Modelsim (Verilog Coding) implementation of Half Adder & Full Adder at gate level, data flow and behavior level A - GATE LEVEL DESIGN At gate level, the circuit is described in

41 LAB 10 Introduction to Modelsim (Verilog Coding) implementation of Half Adder & Full Adder at gate level, data flow and behavior level A - GATE LEVEL DESIGN At gate level, the circuit is described in terms of gates (e.g. and, nand). Hardware design at this level is intuitive for a user with a basic knowledge of digital logic design because it is possible to see a one-to-one correspondence between the logic circuit diagram and the Verilog description. Lab Overview In this lab you will: Learn modeling at gate level Half adder design Full adder design Multiplexer design Decoder design Background: The simplest form of adder is called a Half-Adder (HA). The HA performs bit-wise addition between two input bits. Depending on the result of the operation, the HA either sets or clears its Sum and Carry bit. A HA can be expanded to include the logic for carry in, and the modified unit is called the Full Adder (FA). VLSI System Design 41

42 The verilog code for the half adder is module HA(a,b,s,c); input a,b; output s,c; xor(s,a,b); and(c,a,b); endmodule The test bench of the half adder is module testbench_ha(); reg a,b; wire s,c; HA HA_inst(a,b,s,c); initial begin a=0; b=0; #10 a=0; b=1; #10 a=1; b=0; #10 a=1; b=1; end endmodule VLSI System Design 42

43 We can use the half adder to design a full adder as shown in figure 1.3. The full adder takes an extra bit as input for carry in. The verilog code of full adder is module FA(a,b,cin,s,cout); input a,b,cin; output s,cout; wire c0, s0, c1; HA HA_inst0(a,b,s0,c0); HA HA_inst1(cin,s0,s,c1); or(cout, c1,c0); endmodule VLSI System Design 43

44 B - DATAFLOW LEVEL DESIGN Dataflow modeling provides a powerful way to implement a design. Verilog allows a circuit to be designed in terms of the data flow between registers and how a design processes data rather than instantiation of individual gates. Lab Overview In this lab you will: Learn modeling at dataflow level Background: Half adder design (dataflow) Full adder design (dataflow) 4-bit adder design 12-bit Carry Select Adder (CSA) Multiplexer design (dataflow) Decoder design (dataflow) The simplest form of adder is called a Half-Adder (HA). The HA performs bit-wise addition between two input bits. Depending on the result of the operation, the HA either sets or clears its Sum and Carry bit. A HA can be expanded to include the logic for carry in, and the modified unit is called the Full Adder (FA). VLSI System Design 44

$The verilog code for the half adder at dataflow level is module HA(a,b,s,c); input a,b; output s,c; assign s = a^b; assign c = a&b; // assign {s,c} = a+b; endmodule The test bench of$

45 The verilog code for the half adder at dataflow level is module HA(a,b,s,c); input a,b; output s,c; assign s = a^b; assign c = a&b; // assign {s,c} = a+b; endmodule The test bench of the half adder is module testbench_ha(); reg a,b; wire s,c; HA HA_inst(a,b,s,c); initial begin a=0; b=0; #10 a=0; b=1; #10 a=1; b=0; #10 a=1; b=1; end endmodule VLSI System Design 45

46 We can use the half adder to design a full adder as shown in figure 2.3. The full adder takes an extra bit as input for carry in. The verilog code of full adder at dataflow level is module FA(a,b,cin,s,cout); input a,b,cin; output s,cout; wire c0, s0, c1; HA HA_inst0(a,b,s0,c0); HA HA_inst1(cin,s0,s,c1); assign cout = c1 c0; assign {s,cout} = a + b + cin; endmodule VLSI System Design 46

47 C. BEHAVIORAL LEVEL DESIGN With the increasing complexity of digital design, it has become vitally important to make wise design decisions early in a project. Designers need to be able to evaluate the trade-offs of various architectures and algorithms before they decide on the optimum architecture and algorithm to implement in hardware. Thus, architectural evaluation takes place at an algorithmic level where the designers do not necessarily think in terms of logic gates or data flow but in terms of the algorithm they wish to implement in hardware. They are more concerned about the behavior of the algorithm and its performance. Only after the high-level architecture and algorithm are finalized, do designers start focusing on building the digital circuit to implement the algorithm. Verilog provides designers the ability to describe design functionality in an algorithmic manner. In other words, the designer describes the behavior of the circuit. Thus, behavioral modeling represents the circuit at a very high level of abstraction. Lab Overview In this lab you will: Learn modeling at dataflow level Half adder design (dataflow) Full adder design (dataflow) 4-bit adder design 12-bit Carry Select Adder (CSA) Multiplexer design (dataflow) Decoder design (dataflow) Background: The simplest form of adder is called a Half-Adder (HA). The HA performs bit-wise addition between two input bits. Depending on the result of the operation, the HA either sets or clears its Sum and Carry bit. A HA can be expanded to include the logic for carry in, and the modified unit is called the Full Adder (FA). At behavioral level you don t need to know the structural model but you are only concerned with the behavioral of a circuit. Comments have been added in the code which give a feel for behavioral level coding. VLSI System Design 47

$The verilog code for the half adder at behavioral level is module HA(a,b,s,c); input a,b; output s,c; reg s,c; always @(a or b) begin s= a^b; c = a&b; //OR {s,c} = a+b;$

48 The verilog code for the half adder at behavioral level is module HA(a,b,s,c); input a,b; output s,c; reg s,c; or b) begin s= a^b; c = a&b; //OR {s,c} = a+b; end endmodule The test bench of the half adder is module testbench_ha(); reg a,b; wire s,c; HA HA_inst(a,b,s,c); initial begin a=0; b=0; #10 a=0; b=1; VLSI System Design 48

49 #10 a=1; b=0; #10 a=1; b=1; end endmodule You can use the half adder to design a full adder. The full adder takes an extra bit as input for carry in. The Verilog code of full adder at behavioral level is module FA(a,b,cin,s,cout); input a,b,cin; output s,cout; wire c0, s0, c1; HA HA_inst0(a,b,s0,c0); HA HA_inst1(cin,s0,s,c1); assign cout = c1 c0; // OR // or b or cin) //{s,cout} = a+b+cin; endmodule VLSI System Design 49

50 LAB 11 Implementation of 2 to 1 line MUX The Verilog code of 2 to 1 line multiplexer at dataflow level is module mux(i0,i1,selct,m,n,out); input i0,i1,selct; output m,n,out; assign m=i0&selct; assign n=i1&~selct; assign out=m n; endmodule The test bench of 2 to 1 line multiplexer is module testbench_mux; reg i0,i1,selct; wire m,n; mux ff(i0,i1,selct,m,n,out); initial begin i0=1'b0;i1=1'b1;selct=1'b1; //inputs a=0 and b=1 #10 i0=1'b0;i1=1'b1;selct=1'b0; #10 VLSI System Design 50

51 $finish; end endmodule Lab Tasks: 1. Write a verilog code for 2 to 1 line multiplexer in behavioral level 2. Write a verilog code for 4 to 1 line multiplexer in behavioral level. VLSI System Design 51

52 Lab 12 Implementation of 16 bit Ripple Carry Adder VLSI System Design 52

53 DESIGN HIERARCY OF A 16-BIT RIPPLE-CARRY ADDER module Add_rca_16 (sum, c_out, a, b, c_in); output [15: 0] sum; output c_out; input [15: 0] a, b; input c_in; wire c_in4, c_in8, c_in12; Add_rca_4 M4 (sum[3:0], c_in4, a[3:0], b[3:0], c_in); Add_rca_4 M3 (sum[7:4], c_in8, a[7:4], b[7:4], c_in4); Add_rca_4 M2 (sum[11:8], c_in12, a[11:8], b[11:8], c_in8); Add_rca_4 M1 (sum[15:12], c_out, a[15:12], b[15:12], c_in12); endmodule module Add_rca_4 (sum, c_out, a, b, c_in); output [3: 0] sum; output c_out; input [3: 0] a, b; input c_in; wire c_in2, c_in3, c_in4; Add_full M4 (sum[0], c_in2,a[0], b[0], c_in); Add_full M3 (sum[1], c_in3, a[1], b[1], c_in2); VLSI System Design 53

54 Add_full M2 (sum[2], c_in4, a[2], b[2], c_in3); Add_full M1 (sum[3], c_out, a[3], b[3], c_in4); endmodule module Add_full (sum, c_out, a, b, c_in); output sum, c_out; input a, b, c_in; wire w1, w2, w3; Add_half M2 (w1, w2, a, b); Add_half M1 (sum, w3, w1, c_in); or G1 (c_out, w2, w3); endmodule module Add_half (sum, c_out, a, b); output sum, c_out; input a, b; wire c_out_bar; xor M1 (sum, a, b); and M2 (c_out, a, b); endmodule Test Bench module test_add_rca_16 (); wire [15: 0] sum; wire c_out; reg [15: 0] a, b; reg c_in; Add_rca_16 M1 (sum, c_out, a, b, c_in); initial begin #10 a = 16'h0000; b = 16'h0000; c_in = 0; #10 a = 16'h000f; b = 16'h000c; c_in = 0; #10 a = 16'h000f; b = 16'h000c; c_in = 1; #10 a = 16'h0000; b = 16'h0000; c_in = 1; #10 a = 16'h000f; b = 16'h0001; c_in = 0; #10 a = 16'h000f; b = 16'h0001; c_in = 1; $finish; end endmodule VLSI System Design 54

55 LAB 13 SEQUENTIAL CIRCUITS I (FLIP FLOPS) Computers and other digital systems that have memory or that execute a sequence of operations under the direction of stored information are referred to as sequential machines and their circuitry is modeled by sequential logic. Sequential machines do not behave like combinational logic because the outputs of a sequential machine depend on the history of the applied inputs as well as on their present value. The history of the inputs applied to a sequential machine is represented by the state of the machine and requires hardware elements that store information; that is, it requires memory to store the state of the machine as an encoded binary word. Lab Overview In this lab you will: Flip flop designs D_FF JK_FF T_FF Sequential machine design using flip flop Background: There are two main types of sequential circuits and their classification depends on the timing of their signals. 1. A synchronous sequential circuit is a system whose behavior can be defind from the knowledge of its signals at discrete instant of time 2. The behavior of an asynchronous sequential circuit depends upon the input signals at any time and the order in which the inputs change. The storage elements used in clocked sequential circuit are called flip flops. A flip flop is a binary storage device capable of storing one bit of information. The state of a flip flop can change only during a clock pulse transition. Latches are used to model asynchronous circuits. A latch also holds one bit value but the state of the latch can change with changes in inputs and does not require synchronization with clock pulse. In this lab we will learn to model different flip flops using Verilog. D_FF, JK_FF and T_FF are the common flip flops used in synchronous sequential circuits. Function table are used to describe different flip flops. D_FF is the simplest of the flip-flops because its next state is equal to its present state D Table 1 D Flip-Flop Q(t+1) JK_FF has its next state equal to its present state when inputs J and K are both equal to 0. When K=1 and J=0, the clock resets the flip-flop and Q(t+1) = 0. With J=1 and K=0, the flip-flops sets and Q(t+1) =1. When both J and k are equal to 1, the next state changes to the complement of the present state. Table 2 JK Flip-Flop VLSI System Design 55

56 J K Q(t+1) 0 0 Q(t) Q (t+1) T_FF toggles when the T=1 otherwise the state of T_ff does not change. Table 3 T Flip-Flop T Q(t+1) 0 Q(t) 1 Q (t+1) Lab Tasks: 1. Write verilog code for D flip flop and write a test bench to verify the design. 2. Write verilog code for JK flip flop and write a test bench to verify the design. 3. Write verilog code for T flip flop and write a test bench to verify the design. Documentation Submit the codes along with the wave diagrams for the D, JK, T flip flops. VLSI System Design 56

57 LAB 14 SEQUENTIAL CIRCUITS II Unlike combinational logic, whose output is an immediate function of only its present inputs, sequential logic depends on the history of its inputs. This dependency is expressed by the concept of state The future behavior of a sequential machine is completely characterized by its input and its present state. Lab Overview In this lab you will learn: State machines State diagrams State machine design in Verilog Background: Finite State Machines are used to model Sequential circuits since the states of the sequential circuits change depending upon the inputs at the clock edge. A state diagram is used to describe the sequential behavior of the circuit showing the transition of states according to the inputs. Here a traffic light controller example is presented to show the Verilog coding of Finite state machine. Example: Traffic light controller The following specifications must be considered: 1. The traffic signal for the main highway gets highest priority because cars are continuously present on the main highway. Thus, the main highway signal remains green by default. 2. Occasionally, cars from the country road arrive at the traffic signal. The traffic signal for the country road must turn green only long enough to let the cars on the country road go. 3. As soon as there are no cars on the country road, the country road traffic signal turns yellow and then red and the traffic signal on the main highway turn green again. 4. There is a sensor to detect cars waiting on the country road. The sensor sends a signal X as input to the controller. X = 1 if there are cars on the country road; otherwise, X= 0. The state machine diagram and the state definitions for the traffic signal controller are shown in the following figure VLSI System Design 57

58 Figure 5.2 State diagram Table 5.1 State and output signals The traffic signal controller module can be designed with behavioral Verilog constructs module sig_control (hwy, cntry, X, clock, clear); //I/O ports output [1:0] hwy, cntry; //2-bit output for 3 states of signal //GREEN, YELLOW, RED; reg [1:0] hwy, cntry; //declared output signals are registers input X; //if TRUE, indicates that there is car on //the country road, otherwise FALSE input clock, clear; VLSI System Design 58

59 parameter RED = 2'd0, YELLOW = 2'd1, GREEN = 2'd2; //State definition HWY CNTRY parameter S0 = 3'd0, //GREEN RED S1 = 3'd1, //YELLOW RED S2 = 3'd2, //RED RED S3 = 3'd3, //RED GREEN S4 = 3'd4; //RED YELLOW //Internal state variables reg [2:0] state; reg [2:0] next_state; //state changes only at positive edge of clock clock) if (clear) state <= S0; //Controller starts in S0 state else state <= next_state; //State change //Compute values of main signal and country signal begin hwy = GREEN; //Default Light Assignment for Highway light cntry = RED; //Default Light Assignment for Country light case(state) S0: ; // No change, use default S1: hwy = YELLOW; S2: hwy = RED; S3: begin hwy = RED; cntry = GREEN; end S4: begin hwy = RED; cntry = YELLOW; end endcase end //State machine using case statements or X) VLSI System Design 59

60 begin case (state) S0: if(x) next_state = S1; else next_state = S0; S1: begin next_state = S2; end S2: begin next_state = S3; end S3: if(x) next_state = S3; else next_state = S4; S4: begin next_state = S0; end default: next_state = S0; endcase endmodule Federal Urdu University of Arts, Science and Technology, Islamabad Lab Tasks: 1. Write verilog code. 2. Write a test bench to verify the design Documentation Submit the code along with the wave diagrams for the sequence detector VLSI System Design 60

DIGITAL SYSTEM DESIGN

DIGITAL SYSTEM DESIGN Prepared By: Engr. Yousaf Hameed Lab Engineer BASIC ELECTRICAL & DIGITAL SYSTEMS LAB DEPARTMENT OF ELECTRICAL ENGINEERING Digital System Design 1 Name: Registration No: Roll No: Semester: