REALIZATION OF AN 8-BIT PROCESSOR USING XILINX

Transcription

1 REALIZATION OF AN 8-BIT PROCESSOR USING XILINX T.Deepa M.E (Applied Electronics) Department of Electronics and Communication Engineering, Sri Venkateswara College of Engineering, Sriperumbudur, Chennai, India. Dr. S. Muthukumar Professor Department of Electronics and Communication Engineering, Sri Venkateswara College of Engineering, Sriperumbudur, Chennai, India. Abstract: This project presents the design of soft processor by using verilog HDL in Xilinx ISE12.2 simulator. The soft processor consists of 8-bit ALU, 8-bit instruction register, 64-bit accumulator, 10-bit program counter, 1KB memory, control unit and temporary registers, which are 8-bit a register, 8-bit b register, 64-bit aa register, 64- bit bb register and 64-bit y register. It performs 22 different arithmetic and logical instructions such as addition, subtraction, increment, decrement, multiplication, square, and, nand, nor, or, not, ex-or, exnor, arithmetic shift left, arithmetic shift right, rotate left, rotate right, compare, logical shift left, logical shift right, add with carry, and subtract with borrow, 10 different floating point instructions such as 32-bit floating point addition, 32-bit floating point subtraction, 32-bit floating point multiplication, 32-bit floating point increment, 32-bit floating point decrement, 64-bit floating point addition, 64-bit floating point subtraction, 64-bit floating point multiplication, 64-bit floating point increment, 64-bit floating point decrement and 5 data transfer instructions. The control unit generates all the control signals needed for the coordination among the entire components of the soft processor. All the modules in the design were coded by using behavioral and structural modeling in verilog HDL language. The design entry, synthesis, and simulation of soft processor have been done by using Xilinx ISE 12.2 software. The soft processor is designed with 17% utilization and totally 1026 slices are used. Its frequency is 6.25 MHz which is obtained, with a minimum period of 160ns. Keywords: Soft processor (8-bit processor), veriloghdl, Xilinx ISE12.2, Arithmetic and logic unit (ALU), Floating Point (FP) unit, Register Transfer Level (RTL). I. INTRODUCTION In the mid-seventies it was easy to define a microprocessor. At that time one could say that a microprocessor is a central processing unit realized on a largescale integration (LSI) i.e. 50,000 or more transistors on a single integrated chip, operating at a clock frequency of 1 to 5 MHZ, constituting an 8-bit system, with two to seven generalpurpose CPU 8-bit registers. Most of the new microprocessor issue more than one instruction per cycle. Practically all modern microprocessor have on chip floating point (FP) unit. Most systems have a separate 32-register file for the integer unit, and a separate 32-register file for floating point unit. II. RELATED WORK Several papers regarding soft processor has been reviewed. The following papers have been surveyed. In [14] Sahdev D. Kanjariya, Rutarth Patel designed Generic IEEE- 754 Based Floating Point Adder, Subtractor and Multiplier. In this paper, architecture of floating point unit is proposed and discussed. This floating point unit is compatible with all three IEEE-754 binary representations. Further based on this architecture, floating point subtractor, adder and multiplier modules are designed and functionally verified in Virtex-4 FPGA. In [15] Sreehari Veeramachaneni, M. B. Srinivas designed arithmetic floating point unit. Floating point adder and subtractor units like fused floating point adder, triple path floating point (FP) adder, etc.., involve exponent comparison or subtraction, mantissa addition or subtraction and incrementing values while rounding as basic operations. To realize these operations, efficient arithmetic units like adders, subtractors, comparators and incrementers are vital. In this paper an efficient design of a floating point adder and a design methodology for 2 s complement block is proposed which helps in design of floating point units. In [16] Prateek Singh, Kalyani Bhole designed Optimized Floating Point Arithmetic Unit. In this paper an arithmetic unit based on IEEE-754 standard for floating point numbers has been implemented on Spartan3E XC3S500e FPGA Board. Here Floating Point Unit (FPU) follows IEEE single precision (32-bit) format. Various arithmetic operations such as, addition, multiplication, subtraction and division on floating point numbers have been performed on arithmetic unit. Novel approach of converting fixed to floating point saves around 30% of slices and can perform 50 Mega floating point operations per second on Spartan 3E FPGA at 50 MHz clock. 40

2 III. DESIGN METHODOLOGY A. ALU design An 8-bit ALU has been designed using verilog HDL. The Figure.1 shows the block diagram of 8-bit ALU. The input for 22 operations like addition, subtraction, multiplication, square, increment, decrement, AND, OR, NOT, NOR, etc., are fetched from registers a and b. The inputs for the 10 operations like single and double precision floating point addition, floating point subtraction, etc., are obtained from registers aa and bb. The inputs for the remaining 5 data transfer operations are obtained from registers aa and bb. The output of arithmetic unit and logic unit are given to 64:1 multiplexer. A 64:1 multiplexer requires 6 selection lines which are s0, s1, s2, s3, s4, s5. According to this selection lines logical and arithmetic operations will perform. Finally output from the ALU is stored in y register. After the execution of the arithmetic and logical instruction has performed, if the result of the ALU is zero, then the zero flag is set. The sign flag is set, when bit D7 of the result is 1. In a given byte, if D7 bit is 1, the result will be positive number; otherwise it will be negative value. This sign flag is used with signed numbers. Bias value for 32-bit FP unit = (2^e-1)-1=(2^8-1)-1= Algorithm for 32-bit FP adder The Figure.2 shows the block diagram of 32-bit FP adder. always be greater than exponent value of the operand bb, otherwise swap these operands. And then subtract the exponent of operand bb from operand aa i.e. e1-e2. 3. Normalize the mantissa of bb i.e represent the mantissa m2 in 1.m2 format. 4. According to the difference value obtained from e1- e2, left shift the normalized value (1.m2). Output of the right shifter is aligned mantissa. 5. Normalize the mantissa of aa i.e represent the 6. Add the normalized value of m1(1.m1) and output of right shifter by using 24-bit adder. 7. The output of the adder is 24-bit sum and 1-bit carry. if carry is 1, the outpu of the exponent is e1+1 i.e add 1 with first operand exponent and normalize the mantissa(1.m). Otherwise the output exponent is e1 8. If carry is 1 then the mantissa of the result will be same as [23:1] of the adder output, otherwise the mantissa is [22:0] of adder output. Figure.1 Block diagram of ALU B. Single precision floating point (FP) unit 32-bit FP addition, 32-bit subtraction and 32-bit multiplication unit has been designed using verilog HDL. Here, the inputs of the FP unit have been represented by using IEEE 754 format. Each 32-bit input has 3 fields which are 1- bit sign field, 8-bit exponent field and 23-bit mantissa field. Figure.2 Block diagram of 32-bit FP adder 2. Algorithm for 32-bit FP subtractor The Figure.3 shows the block diagram of 32-bit FP subtractor. 41

3 always be greater than exponent value of the operand bb, otherwise swap these operands. And then subtract the exponent of operand bb from operand aa i.e. e1-e2. 3. Normalize the mantissa of bb i.e. represent the mantissa m2 in 1.m2 format. 4. According to the difference value obtained from e1- e2, left shift the normalized value (1.m2). Output of the right shifter is aligned mantissa. 5. Normalize the mantissa of aa i.e. represent the 6. Add the normalized value of m1 (1.m1) and output of right shifter by using 24-bit subtractor. 7. The output of the subtactor is 24-bit difference and 1- bit borrow. if borrow is 1, the output of the exponent is e1+1 i.e. add 1 with first operand exponent and normalize the mantissa(1.m). Otherwise the output exponent is e1 and there is no need for normalization. 8. If borrow is 1 then the mantissa of the result will be same as [23:1] of the subtractor output, otherwise the mantissa is [22:0] of subtractor output. 4. Add the exponents of first and second operand by using 8-bit adder and subtract the bias value 127 from the adder output. Bias value for 32-bit FP unit = (2^e-1)-1= (2^8-1)-1= If carry is 1, the outpu of the exponent is e1+1 i.e. adds 1 with first operand exponent and normalize the mantissa (1.m). Otherwise the output exponent is e1 6. If carry is 1 then the mantissa of the result will be same as [46:24] of the multiplier output, otherwise the mantissa is [45:23] of multiplier output. Figure.4 Block diagram of 32-bit FP multiplier 4. Algorithm for 32-bit FP incrementer The Figure.5 shows the block diagram of 32-bit FP adder. Figure.3 Block diagram of 32-bit FP subtractor 3. Algorithm for 32-bit FP multiplier The Figure.4 shows the block diagram of 32-bit FP multiplier. 1. The EX-OR of first operand (s1) and second operand (s2) sign bits will be the sign bit (s3) of the output. 2. Normalize the mantissa of the first operand aa to 1.m1 format and second operand bb to 1.m2 format. 3. Multiply the normalized mantissass of both operands by using 24-bit multiplier. The output of the multiplier is 47-bit sum and 1-bit carry. Figure.5 Block diagram of 32-bit FP incrementer always be greater than 8' b , otherwise swap these operands. And then Subtract 8' b from operand aa i.e. e1-8' b

4 3. The input of the right shifter (RS) is 24'b According to the difference value obtained from e1-8' b , left shift the input of RS. Output of the right shifter (RS) is aligned mantissa. 4. Normalize the mantissa of aa i.e. represent the 5. Add the normalized value of m1(1.m1) and output of right shifter by using 24-bit adder. 6. The output of the adder is 24-bit sum and 1-bit carry. if carry is 1, the output of the exponent is e1+1 i.e add 1 with first operand exponent and normalize the mantissa(1.m). Otherwise the output exponent is e1 7. If carry is 1 then the mantissa of the result will be same as [23:1] of the adder output, otherwise the mantissa is [22:0] of adder output. 5. Algorithm for 32-bit FP decrementer The Figure.6 shows the block diagram of 32-bit FP adder. always be greater than 8' b , otherwise swap these operands. And then Subtract 8' b from operand aa i.e. e1-8' b The input of the right shifter (RS) is 24'b According to the difference value obtained from e1-8' b , left shift the input of RS. Output of the right shifter (RS) is aligned mantissa. 4. Normalize the mantissa of aa i.e represent the 5. Add the normalized value of m1(1.m1) and output of right shifter by using 24-bit adder. 6. The output of the adder is 24-bit sum and 1-bit carry. if carry is 1, the output of the exponent is e1+1 i.e add 1 with first operand exponent and normalize the mantissa(1.m). Otherwise the output exponent is e1 7. If carry is 1 then the mantissa of the result will be same as [23:1] of the adder output, otherwise the mantissa is [22:0] of adder output. Figure.6 Block diagram of 32-bit FP deccrementer C. Double precision floating point (FP) unit 64-bit FP addition, 64-bit subtraction and 64-bit multiplication unit has been designed using verilog HDL. Here, the inputs of the FP unit have been represented by using IEEE 754 format. Each 32-bit input has 3 fields which are 1- bit sign field, 11-bit exponent field and 52-bit mantissa field. Bias for 64-bit FP unit = (2^e-1)-1= (2^11-1)-1= Algorithm for 64-bit FP adder Consider first operand is aa and second operand is bb. The Figure.7 shows the block diagram of 64-bit FP adder. always be greater than exponent value of the operand bb, otherwise swap these operands. And then subtract the exponent of operand bb from operand aa i.e. e1-e2. 3. Normalize the mantissa of bb i.e represent the mantissa m2 in 1.m2 format. 4. According to the difference value obtained from e1- e2, left shift the normalized value (1.m2). Output of the right shifter is aligned mantissa. 5. Normalize the mantissa of aa i.e represent the 6. Add the normalized value of m1 (1.m1) and output of right shifter by using 53-bit adder. 7. The output of the adder is 53-bit sum and 1-bit carry. if carry is 1, the outpu of the exponent is e1+1 i.e add 1 with first operand exponent and normalize the mantissa(1.m). Otherwise the output exponent is e1 8. If carry is 1 then the mantissa of the result will be same as [52:1] of the adder output, otherwise the mantissa is [51:0] of adder output. 43

5 Figure.7 Block diagram of 64-bit FP adder 2. Algorithm for 64-bit FP subtractor Consider first operand is aa and second operand is bb. The Figure.8 shows the block diagram of 64-bit FP subtractor. always be greater than exponent value of the operand bb, otherwise swap these operands. And then subtract the exponent of operand bb from operand aa i.e. e1-e2. 3. Normalize the mantissa of bb i.e. represent the mantissa m2 in 1.m2 format. 4. According to the difference value obtained from e1- e2, left shift the normalized value (1.m2). Output of the right shifter is aligned mantissa. 5. Normalize the mantissa of aa i.e. represent the 6. Add the normalized value of m1 (1.m1) and output of right shifter by using 53-bit subtractor. 7. The output of the subtactor is 53-bit difference and 1- bit borrow. if borrow is 1, the output of the exponent is e1+1 i.e add 1 with first operand exponent and normalize the mantissa(1.m). Otherwise the output exponent is e1 and there is no need for normalization. 8. If borrow is 1 then the mantissa of the result will be same as [52:1] of the subtractor output, otherwise the mantissa is [51:0] of subtractor output. Figure.8 Block diagram of 64-bit FP subtractor 3. Algorithm for 64-bit FP multiplier The Figure.9 shows the block diagram of 64-bit FP multiplier. 1. The EX-OR of first operand (s1) and second operand (s2) sign bits will be the sign bit (s3) of the output. 2. Normalize the mantissa of the first operand aa to 1.m1 format and second operand bb to 1.m2 format. 3. Multiply the normalized mantissas of both operands by using 53-bit multiplier. The output of the multiplier is 105-bit sum and 1-bit carry. 4. Add the exponents of first and second operand by using 11-bit adder and subtract the bias value 127 from the adder output. Bias for 64-bit FP unit = (2^e-1)-1=(2^11-1)-1= If carry is 1, the outpu of the exponent is e1+1 i.e. adds 1 with first operand exponent and normalizes the mantissa (1.m). Otherwise the output exponent is e1 and there is no need for normalization. 6. If carry is 1 then the mantissa of the result will be same as [104:53] of the multiplier output, otherwise the mantissa is [103:52] of multiplier output. 44

6 Figure.9 Block diagram of 64-bit FP multiplier 4. Algorithm for 64-bit incrementer The operation of 64-bit incrementer is similar to 32-bit incrementer. Only the number of input bits increases according to double precision, it has 1-bit sign bit, 11-bit exponent and 52-bit mantissa. The Figure.10 shows the block diagram of 64-bit FP incrementer. Figure.11 Block diagram of 64-bit FP decrementer D. Data transfer instruction This soft processor performs 5 data transfer instruction, which are Move data between registers, Move immediate data to register, Move immediate data to memory, Store, Load. E. Proposed processor architecture The proposed system architecture is shown in Figure. 12. It executes 22 different arithmetic and logical instructions such as addition, subtraction, increment, decrement, multiplication, square, ex-or, ex-nor, not, arithmetic shift left, arithmetic shift right, etc., 10 floating point instructions such as single and double precision addition, subtraction, etc., and 5 data transfer instructions. The following steps are performed in order to fetch the instruction in memory location 87H Figure.10 Block diagram of 64-bit FP incrementer 5. Algorithm for 64-bit decrementer The operation of 64-bit decrementer is similar to 32-bit decrementer. Only the number of input bits increases according to double precision, it has 1-bit sign bit, 11-bit exponent and 52-bit mantissa. The Figure.11 shows the block diagram of 64-bit FP decrementer. 1. The address for the program counter has to be given. 2. Program counter places the 10-bit address 87H of the memory location on the address bus. 3. To enable read operation the control unit must send the memory read control signal (MEMRD=1) to memory. 4. The instruction (58H) stored in the memory location is placed on the data bus and transferred to instruction register (IR), after getting read signal from memory,. 5. The instruction present in the instruction register is decoded and executed according to the binary pattern of the instruction. 45

7 Figure. 15 Simulation result of 8-bit processor (64-bit FP addition operation) Figure. 16 RTL of 8-bit processor V. CONCLUSION Figure.12 Block diagram of 8-bit processor IV. SIMULATION RESULTS Figure. 13 Simulation result of 8-bit processor (64-bit FP addition operation) The soft processor has been designed using verilog HDL and it is simulated using Xilinx ISE 12.2 software. All the modules in the design were coded by using structural and behavioral modeling in verilog HDL language. It executes 22 different arithmetic and logicall instructions such as addition, subtraction, increment, decrement, multiplication, square, and, nand, nor, or, not, ex-or, ex-nor, arithmetic shift left, arithmetic shift right, rotate left, rotate right, compare, logical shift left, logical shift right, addd with carry, and subtract with borrow, 10 different floating point instructions such as 32-bit floating point addition, 32-bit floating point subtraction, 32-bit floating point multiplication, 32-bit floating point increment, 32-bit floating point decrement, 64-bit floating point addition, 64-bit floating point subtraction, 64-bit floating point multiplication, 64-bit floating point increment, 64-bit floating point decrement and 5 data transfer instructions. The soft processor which is designed operates at a frequency rate of 6.25 MHz with a minimum period of 160ns and totally 1026 slices were utilized. REFERENCES Figure. 14 Simulation result of 8-bit processor (64-bit FP addition operation) [1]Qasem Abu Al-Haija, Hasan Al-Amri, Mohamed Al- in An Engineering Design Nashri, and Sultan Al-Muhaisen of 4-Bit Special Purpose Microprogrammed Processor Elsevier, [2]Paul Metzgen in A High Performance 32-bit ALU for Programmable Logic, ACM, [3]Lafifa Jamal, Md. Masbaul Alam, Hafiz Md. Hasan Babu, An efficient approach to design a reversible control unit of a processor, Elsevier [4]Shridhar Devamane, Akshada Hanchate,Usha Vagare,Shalaka Ujagare,Pushpa Teggelli, Design and Implementation of FPGA based Barrel shifter, International Journal of Advanced Research in Computer Engineering & Technology (IJARCET),

8 [5]Suchita Kamble, Prof.N. N. Mhala, VHDL Implementation of 8-Bit ALU, IOSR Journal of Electronics and Communication Engineering (IOSRJECE), [6]E.Ayeh, K.Agbedanu, Y.Morita, O. Adamo, and P.Guturu, FPGA based Implementation of an 8-bit simple processor,ieee, [7]Prof.s.Kaliamurthy, Ms U.Sowmmiya, VHDL Design of FPGA Arithmetic Processor, Global Journal of researches in engineering, [8]Bishwajeet pandey, Jyotsana Yadav, Yogesh Kumar Singh, Rohit Kumar,Sourabh Patel, Energy efficient design and implementation of ALU on 40nm FPGA, IEEE, [9]William stallings, Computer organization and architecture designing for performance, eight edition, pearson, [10]Shashank Kaithwas, Pramod Kumar Jain, Design of 16- bit Data Processor Using Finite State Machine in Verilog, International Journal of Engineering Research and General Science, [11]Disha Malik1, Richa Singh Rathore, 32 bit Arithmetic Logical Unit (ALU) using VHDL, International Journal of Science, Engineering and Technology, [12]Józef Kulisz, Mirosław Chmiel, Adrian Krzyżyk, Marcin Rosół, A Hardware Implementation of Arithmetic Operations for an FPGA-based Programmable Logic Controller, Elsevier, 2015 [13]Galani Tina G., Riya Saini and R.D.Daruwala, Design and Implementation of 32 bit RISC Processor using Xilinx,International Journal of Emerging Trends in Electrical and Electronic, [14] Sahdev D. Kanjariya, Rutarth Patel, Architecture and Design of Generic IEEE-754 Based Floating Point Adder, Subtractor and Multiplier, International Journal on Recent and Innovation Trends in Computing and Communication, [15] Sreehari Veeramachaneni, M. B. Srinivas, Floating Point Adder/Subtractor Units Realization by Efficient Arithmetic Circuits, IEEE, [16] Prateek Singh, Kalyani Bhole, Optimized Floating Point Arithmetic Unit, Annual IEEE India Conference,