CS61C : Machine Structures

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1 inst.eecs.berkeley.edu/~csc CSC : Machine Structures Lecture Caches II -9-9 Instructor: Miki Lustig August : IBM Unveils a Brain-Like Chip With, Processor Cores TrueNorth comes packed with,9 processor cores, and it mimics one million human neurons and million synapses. The chip is meant to run neural-net processing for recognition. CSC L : Caches II() Garcia, Lustig Fall UCB

2 Review: Direct-Mapped Cache Terminology Index specifies the cache index ( row /block) Offset Specifies which byte within the block we want Distinguish between all the memory addresses that map to the same location ttttttttttttttttt iiiiiiiiii oooo tag index byte to check to if have select within correct block block block Garcia,Lustig Fall UCB

3 Review: Direct-Mapped Cache bit Memory Address 8 A C E 8 A C E Memory E D E F 8 E D E F D A B E F 9 D A B E F F Index add. 8 9 tag F D A E D F tag index tt ii o hit hit hit miss Garcia,Lustig Fall UCB

4 Review: TIO Dan s great cache mnemonic AREA (cache size, B) = HEIGHT (# of blocks) * WIDTH (size of one block, B/block) (H+W) = H * W Index Offset WIDTH (size of one block, B/block) tag F D A E D F HEIGHT (# of blocks) AREA (cache size, B) Garcia,Lustig Fall UCB

5 How to Split Cache? Small or large block sizes? Large Better spatial locality Too large, misses increase with large penalty many small blocks one large block Garcia,Lustig Fall UCB

6 Memory Access without Cache Load word instruction: lw $t, ($t) $t contains ten, Memory[] = 99. Processor issues address ten to Memory. Memory reads word at address ten (99). Memory sends 99 to Processor. Processor loads 99 into register $t Garcia,Lustig Fall UCB

7 Memory Access with Cache Load word instruction: lw $t, ($t) $t contains ten, Memory[] = 99 With cache (similar to a hash). Processor issues address ten to Cache. Cache checks to see if has copy of data at address ten a.if finds a match (Hit): cache reads 99, sends to processor b.no match (Miss): cache sends address to Memory I. Memory reads 99 at address ten II. Memory sends 99 to Cache III. Cache replaces word with new 99 IV. Cache sends 99 to processor. Processor loads 99 into register $t Garcia,Lustig Fall UCB

8 Caching Terminology When reading memory, things can happen: cache hit: cache block is valid and contains proper address, so read desired word cache miss: nothing in cache in appropriate block, so fetch from memory cache miss, block replacement: wrong data is in cache at appropriate block, so discard it and fetch desired data from memory (cache always copy) Garcia,Lustig Fall UCB

9 Cache Terms Hit rate: fraction of access that hit in the cache [.-.] Miss rate: Hit rate Miss penalty: time to replace a block from lower level in memory hierarchy to cache Hit time: time to access cache memory (including tag comparison) Abbreviation: $ = cache Garcia,Lustig Fall UCB

10 Accessing data in a direct mapped cache Ex.: KiB of data, direct-mapped, word blocks Can you work out height, width, area? Address (hex) 8 C Memory Value of Word a b c d Read addresses. x. xc. x. x8 Memory vals here: 8 C C e f g h i j k l Garcia,Lustig Fall UCB

11 Accessing data in a direct mapped cache Addresses: x, xc, x, x8 Addresses divided (for convenience) into, Index, Byte Offset fields Index Offset Garcia,Lustig Fall UCB

12 KiB Direct Mapped Cache, B blocks Valid bit: determines whether anything is stored in that row (when computer initially turned on, all entries invalid) Index Valid xc-f x8-b x- x- Garcia,Lustig Fall UCB

13 . Read x Index Field Index Valid xc-f x8-b x- x- Garcia,Lustig Fall UCB

14 So we read block () Index Field Index Valid xc-f x8-b x- x- Garcia,Lustig Fall UCB

15 No valid data Index Field Index Valid xc-f x8-b x- x- Garcia,Lustig Fall UCB

16 So load that data into cache, setting tag, valid Index Field Index Valid xc-f x8-b x- x- d c b a Garcia,Lustig Fall UCB

17 Read from cache at, return word b Index Field Index Valid xc-f x8-b x- x- d c b a Garcia,Lustig Fall UCB

18 . Read xc =.. Index Field Index Valid xc-f x8-b x- x- d c b a Garcia,Lustig Fall UCB

19 Index is Valid Index Field Index Valid xc-f x8-b x- x- d c b a Garcia,Lustig Fall UCB

20 Index valid, Matches Index Field Index Valid xc-f x8-b x- x- d c b a Garcia,Lustig Fall UCB

21 Index Valid, Matches, return d Index Field Index Valid xc-f x8-b x- x- d c b a Garcia,Lustig Fall UCB

22 . Read x =.. Index Field Index Valid xc-f x8-b x- x- d c b a Garcia,Lustig Fall UCB

23 So read block Index Field Index Valid xc-f x8-b x- x- d c b a Garcia,Lustig Fall UCB

24 No valid data Index Field Index Valid xc-f x8-b x- x- d c b a Garcia,Lustig Fall UCB

25 Load that cache block, return word f Index Field Index Valid xc-f x8-b x- x- d c b a h g f e Garcia,Lustig Fall UCB

26 . Read x8 =.. Index Field Index Valid xc-f x8-b x- x- d c b a h g f e Garcia,Lustig Fall UCB

27 So read Cache Block, Data is Valid Index Field Index Valid xc-f x8-b x- x- d c b a h g f e Garcia,Lustig Fall UCB

28 Cache Block does not match (!= ) Index Field Index Valid xc-f x8-b x- x- d c b a h g f e Garcia,Lustig Fall UCB

29 Miss, so replace block with new data & tag Index Field Index Valid xc-f x8-b x- x- l k j i h g f e Garcia,Lustig Fall UCB

30 And return word J Index Field Index Valid xc-f x8-b x- x- l k j i h g f e Garcia,Lustig Fall UCB

31 Do an example yourself. What happens? Chose from: Cache: Hit, Miss, Miss w. replace Values returned:a,b, c, d, e,, k, l Read address x? Read address xc? Index Valid xc-f x8-b x- x- l k j i h g f e Memory Address (hex) Value of Word 8 C 8 C C a b c d e f g h i j k l Garcia,Lustig Fall UCB

32 Answers x a hit Index =, matches, Offset =, value = e xc a miss Index =, mismatch, so replace from memory, Offset = xc, value = d Since reads, values must = memory values whether or not cached: x = e xc = d Address (hex) 8 C 8 C C Memory Value of Word a b c d e f g h i j k l Garcia,Lustig Fall UCB

33 Multiword-Block Direct-Mapped Cache Four words/block, cache size = K words Hit Byte Data 8 Index Block Index Valid... 8 Data AND MUX à Multiplexor What kind of locality are we taking advantage of? Garcia,Lustig Fall UCB

34 Peer Instruction ) Mem hierarchies were invented before 9. (UNIVAC I wasn t delivered til 9) ) All caches take advantage of spatial locality. ) All caches take advantage of temporal locality. a) FFF a) FFT b) FTF b) FTT c) TFF d) TFT e) TTF e) TTT Garcia,Lustig Fall UCB

35 Peer Instruction A. For a given cache size: a larger block size can cause a lower hit rate than a smaller one. B. If you know your computer s cache size, you can often make your code run faster. C. Memory hierarchies take advantage of spatial locality by keeping the most recent data items closer to the processor. ABC : FFF : FFT : FTF : FTT : TFF : TFT : TTF : TTT Garcia,Lustig Fall UCB

36 And in Conclusion Mechanism for transparent movement of data among levels of a storage hierarchy set of address/value bindings address index to set of candidates compare desired address with tag service hit or miss load new block and binding on miss address: tag index Valid!!! xc-f! x8-b! x-! x-!!!!!!!! d! c! b! a! Garcia,Lustig Fall UCB

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