SmartSpice Verilog-A Interface. Behavioral and Structural Modeling Tool - Device Model Development

Transcription

1 SmartSpice Verilog-A Interface Behavioral and Structural Modeling Tool - Device Model Development

2 Verilog-A Models and Features Agenda Overview Design Capability Compact Modeling Verilog-A Inteface - 2 -

3 Verilog-A - As an Extension of SmartSpice Verilog-A Verilog HDL Behavioral Higher level of abstraction Circuit Compact Model Development Switch Gate Verilog-A Inteface - 3 -

4 Verilog-A Integration into SmartSpice SmartSpice and Verilog-A integration provides designers with an easy to use environment for the design and verification of complex analog and mixed-signal circuits This integration provides the designer the capability to create executable specifications for the system design and, A powerful optimization capability for achieving those specifications VERILOG-A SUPPORTS A TOP-DOWN DESIGN METHODOLOGY Verilog-A Inteface - 4 -

5 SmartSpice - Verilog-A: Design Capability Circuit designers can control level of design abstraction All abstraction levels can be combined in one hierarchical implementation: Verilog-A Inteface - 5 -

6 Analog System Description and Simulation with Verilog-A Environment Behavioral Description Description in a programmatic fashion with the Verilog-A language The Behavioral module is defined in terms of the values for each signal Structural Description A Structural module is hierarchically comprised of other child modules Mixed-level Description Combines both Structural and Behavioral module descriptions with SPICE for execution Verilog-A Inteface - 6 -

7 Single Kernal SmartSpice Simulator Accepts SPICE netlist, C, and Verliog-A in any hierarchy Compatible with Verilog-AMS 2.1 Capability to create symbols for Verilog-A modules for use in schematic capture SmartSpice Optimizer supports dataflow of curves and parameters from Verilog-A behavioral and/or structural modules to an actual circuit architecture Optimization targets can be a combination of.ac,.dc, and.tran curves with target parameter specifications such as propagation delay, rise/fall time, power dissipation, etc. A typical good example is finding ideal transistor lengths and widths and/ or optimal bias voltages and currents Verilog-A Inteface - 7 -

8 Analog Flow Verilog-A Inteface - 8 -

9 Application 1: Analog to Digital Converter sampling clock analog in delay time ADC digital out rise/fall time Verilog-A Inteface - 9 -

10 ADC - Module Description module adc (in, clk, out) ; parameter integer bits=8 ; parameter real fullscale=1.0, dly=5n, ttime=0.2n ; input in, clk ; output [bits-1:0] out ; electrical in, clk ; electrical [bits-1:0] out ; real sample, thresh ; integer result[bits-1:0] ; integer i ; analog begin thresh = fullscale/2.0 cross( V(clk)-2.5, +1 ) ) begin sample = V(in) ; for( i=bits-1;i>=0;i=i-1 ) begin if( sample>thresh ) begin result[i] = 1 ; sample = sample - thresh ; end else result[i] = 0 ; sample = 2.0 * sample ; end end for( i=0;i<bits;i=i+1 ) begin V(out[i]) <+ transition( 5.0*result[i], dly, ttime ) ; end end endmodule Key features variable input scale variable bit width adjustable output waveform Verilog-A Inteface

11 ADC - Simulation Circuit and Results Verilog-A Inteface

12 Application 2: Shift Register Reduce simulation time while maintain the accuracy out0 out1 out255 data D Q D Q D Q D-FF D-FF D-FF CL clock clear Verilog-A Inteface

13 D-FF Modeling Techniques (1) Delay time is modeled in the following form ; td = td_0 + td_l*fanout + coef*delta_ramp the second term represents fanout-dependency the third term is introduced to take into account ramp-time of clock pulse Rise/Fall time are modeled in the same form as above except the inclusion of third term; tr = tr_0 + tr_l*fanout tf = tf_0 + tf_l*fanout Verilog-A Inteface

14 D-FF Modeling Techniques (2) Instantiate SPICE primitives to represent input capacitor. parameter real c_d = 9f, c_clk = 9f, c_clr = 12f ; capacitor #(.c(c_d)) c1(d,gnd) ; capacitor #(.c(c_clk)) c2(clk,gnd) ; capacitor #(.c(c_clr)) c3(clr,gnd) ; d clk q clr Verilog-A Inteface

15 Shift Register - Simulation Circuit Verilog-A Inteface

16 Shift Register - Simulation Results Good agreement in output waveforms compared with transistor level simulation V(CLK) Verilog-A V(O0) - rise V(O0) - fall transistor level Verilog-A Inteface

17 Application 3: PLL When designing CP block, remaining blocks can be replaced by Verilog-A module reference clock feedback clock Phase Detector (PD) up down Charge Pump (CP) Loop Filter (LPF) Divider /4 Voltage Controlled Oscillator (VCO) VCO in Verilog-A Inteface

18 PPL - VCO Modeling module pll_vco ( in, out ) ; inout in, out ; electrical in, out ; parameter real vdd = 3.3, // operational voltage amp = vdd/2, // amplitude of vout offset = vdd/2, // offset of vout gain = 464e6, // gain [Hz/V] vnom = 1.27, // nominal vin fc = 400e6; // center frequency at vnom real freq ; adjust voltage-freq gain adjust nominal input voltage adjust center-frequency analog begin freq = fc + gain*(v(in) - vnom) ; V(out) <+ amp*sin(2*`m_pi*idt(freq)) + offset ; end endmodule Verilog-A Inteface

19 PLL - Simulation Result (1) t = 0 t = 1.5us reference clock Feedback clock VCO in Verilog-A Inteface

20 PLL - Simulation Result (2) Good agreement in phase-lock characteristic compared with fulltransistor level simulation CP output voltage; full-transistor sim. Verilog-A mixed sim. Verilog-A Inteface

21 PLL - Simulation Statistics Simulation run is 15 times faster The number of transient analysis points can be reduced to half Total simulation time transient analysis time transient analysis points Case1 Verilog-A mixed 50 MOSFET 191s 186 s pts Case2 full-transistor 347 MOSFET 2951 s 2949 s pts Verilog-A Inteface

22 Compact Model Development Issues Complexity in model development and model implementation as they try to handle all processes Limited number of models are available Common platform for sharing model information between model developers and circuit designers Addressing proprietary model development ( by foundries and large IC companies) and the distribution of those models to their customers (in source or encrypted format) Verilog-A Inteface

23 SPICE Models in Analog Flow Verilog-A Inteface

24 Compact Model Development SmartSpice Verilog-A Environment allows compact model engineer to easily develop complete (.DC,.TRAN,.AC,.NOISE,.TEMP) compiled proprietary models for specific technology behavior such as leakage, weak / sub-threshold operation, TFT transistors Verilog-A Inteface

25 SmartSpice-Verilog-A Model Architecture A Verilog-A device model development and SmartSpice run-time environment Verilog-A Editor & Debugger Verilog-A Model Source Interpreter SmartSpice Circuit Simulator Compiler Verilog-A Inteface

26 Available Verilog-A Compact Model Code Three BIPOLAR and three MOS models are available for distribution free of charge to SmartSpice users to understand and improve models through their own customization BIPOLAR Gummel-Poon VBIC MEXTRAM MOS Level 3 MOS EKV 3.0 BSIM 4 Verilog-A Inteface

27 Summary SmartSpice and Verilog-A integration provides designers with an easy to use environment for the design and verification of complex analog and mixed-signal circuits Verilog-A has the capability to support complex compact model development Model implementation and distribution can be greatly simplified (Proprietary or Public) Example compact models are available Verilog-A Inteface