Sequential Logic Implementation. Mealy vs. Moore Machines. Specifying Outputs for a Mealy Machine. Specifying Outputs for a Moore Machine

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1 uential Logic Implementation! Models for representing sequential circuits " bstraction of sequential elements " Finite state machines and their state diagrams " Inputs/ " Mealy, Moore, and synchronous Mealy machines! Finite state machine design procedure " Verilog specification " eriving state diagram " eriving state transition table " etermining next state and put functions " Implementing combinational logic Mealy vs. Moore Machines! Moore: dep on current state only! Mealy: dep on current state and inputs! nt brain is a Moore Machine " Output does not react immediately to input change! We could have specified a Mealy FSM " Outputs have immediate reaction to inputs " s inputs change, so does next state, doesn t commit until ing event L / TL L R / TL, F react right away to leaving the wall L R / TR, F CS 5 - Spring 27 Lec #7: uential Implementation CS 5 - Spring 27 Lec #7: uential Implementation 2 Specifying Outputs for a Moore Machine! Output is only function of state " Specify in state bubble in state diagram " Example: sequence detector for or reset / / C/ / E/ current next reset input state state put C C E C C E C E E Specifying Outputs for a Mealy Machine! Output is function of state and inputs " Specify put on transition arc between states " Example: sequence detector for or reset/ / / / / C / / current next reset input state state put C C C C C CS 5 - Spring 27 Lec #7: uential Implementation 3 CS 5 - Spring 27 Lec #7: uential Implementation 4 Comparison of Mealy and Moore Machines Mealy and Moore Examples! Mealy Machines t to have less states " ifferent on arcs (n^2) rather than states (n)! Moore Machines are safer to use " Outputs change at edge (always one cycle later) " In Mealy machines, input change can cause put change as soon as logic is done a big problem when two machines are interconnected asynchronous feedback! Mealy Machines react faster to inputs " React in same cycle don't need to wait for " In Moore machines, more logic may be necessary to decode state into more gate delays after! Recognize, =, " Mealy or Moore? inputs Combinational logic for ext State reg Logic for inputs Logic for Combinational logic for ext State reg state feedback CS 5 - Spring 27 Lec #7: uential Implementation 5 state feedback CS 5 - Spring 27 Lec #7: uential Implementation 6

2 Mealy and Moore Examples Registered Mealy Machine (Really Moore)! Recognize, =, then, " Mealy or Moore?! Synchronous (or registered) Mealy Machine " Registered state " voids glitchy " Easy to implement in programmable logic! Moore Machine with no put decoding " Outputs computed on transition to next state rather than after entering " View as expanded state vector Inputs put logic next state logic Outputs CS 5 - Spring 27 Lec #7: uential Implementation 7 Current State CS 5 - Spring 27 Lec #7: uential Implementation 8 Verilog FSM - Reduce s Example Moore Verilog FSM! Change the first to in each string of s " Example Moore machine implementation // State assignment parameter =, one =, twos = 2; module reduce (, clk, reset, in); put ; input clk, reset, in; reg ; reg [:] state; // state register reg [:] next_state; [] one [] twos [] or state) : begin // last input was a = ; if (in) next_state = one; one: begin // we've seen one = ; if (in) next_state = twos; twos: begin // we've seen at least 2 ones = ; if (in) next_state = twos; default: begin // in case we reach a bad state = ; next_state = ; case [] include all signals that are input to state and put equations one [] twos [] CS 5 - Spring 27 Lec #7: uential Implementation 9 CS 5 - Spring 27 Lec #7: uential Implementation Moore Verilog FSM Mealy Verilog FSM for Reduce-s Example // Implement the state register if (reset) state <= ; else state <= next_state; module [] one [] twos [] module reduce (clk, reset, in, ); input clk, reset, in; put ; reg ; reg state; // state register reg next_state; parameter =, one = ; or state) : begin // last input was a if (in) next_state = one; = ; one: // we've seen one if (in) begin next_state = one; = ; next_state = ; = ; case / / one / / if (reset) state <= ; else state <= next_state; CS 5 - Spring 27 Lec #7: uential Implementation module CS 5 - Spring 27 Lec #7: uential Implementation 2

3 Synchronous Mealy Verilog FSM for Reduce-s Example module reduce (clk, reset, in, ); input clk, reset, in; put ; reg ; reg state; // state register reg next_state; reg next_; parameter =, one = ; or state) : begin // last input was a if (in) next_state = one; next_ = ; one: // we've seen one if (in) begin next_state = one; next_ = ; next_state = ; next_ = ; case if (reset) begin state <= ; <= ; state <= next_state; <= next_; module / CS 5 - Spring 27 Lec #7: uential Implementation 3 one / / / nnouncements! Review Session nnouncement! First Midterm, Thursday, 5 February, 2-3:3 PM, 25 Cory Hall "??? uiz-like uestions -- Please Read Them Carefully! They are not inted to be tricky; they should contain all the information you need to answer the question correctly " o calculators or other gadgets are necessary! on t bring them! o blue books! ll work on the sheets handed! " o bring pencil and eraser please! If you like to unstaple the exam pages, then bring a stapler with you! Write your name and student I on EVERY page in case they get separated -- it has happened! " on t forget your two-sided 8.5 x crib sheet! CS 5 - Spring 27 Lec #7: uential Implementation 4 nnouncements Example: Ving Machine! Examination, Th, 2-3:3 PM, 25 Cory Hall " Topics likely to be covered # Combinational logic: design and optimization (K-maps up to and including 6 variables) # Implementation: Simple gates (minimum wires and gates), PL structures (minimum unique terms), Muxes, ecoders, ROMs, (Simplified) Xilinx CL # uential logic: R-S latches, flip-flops, transparent vs. edge-triggered behavior, master/slave concept # asic Finite State Machines: Representations (state diagrams, transition tables), Moore vs. Mealy Machines, Shifters, Registers, Counters # Structural and ehavioral Verilog for combinational and sequential logic # Labs, 2, 3 # K&: Chapters, 2 (2.-2.5), 3 (3., 3.6), 4 (4., 4.2, 4.3), 6 (6., 6.2., 6.3), 7 (7., 7.2, 7.3)! Release item after 5 cents are deposited! Single coin slot for dimes, nickels! o change Coin Sensor Ving Machine FSM Release Mechanism Clock CS 5 - Spring 27 Lec #7: uential Implementation 5 CS 5 - Spring 27 Lec #7: uential Implementation 6 Example: Ving Machine Example: Ving Machine! Suitable bstract Representation " Tabulate typical input sequences: # 3 nickels # nickel, dime # dime, nickel # two dimes " raw state diagram: # Inputs:,, reset # Output: open chute " ssumptions: # ssume and asserted for one cycle # Each state has a self loop for = = (no coin) S3 S7 S S4 S S2 S5 S6! Minimize number of states - reuse states whenever possible + present inputs next put state state open symbolic state table CS 5 - Spring 27 Lec #7: uential Implementation 7 CS 5 - Spring 27 Lec #7: uential Implementation 8

4 Example: Ving Machine Example: Ving Machine! Uniquely Encode States present state inputs next state put open! Mapping to Logic X X X X X X X X X X X X = + + = OPE = CS 5 - Spring 27 Lec #7: uential Implementation 9 CS 5 - Spring 27 Lec #7: uential Implementation 2 Example: Ving Machine! One-hot Encoding Equivalent Mealy and Moore State iagrams! Moore machine " associated with state Mealy machine associated with transitions present state inputs next state put open = = + 2 = = OPE = 3 [] + [] [] + / ( + )/ / / / / / / / +/ [] / CS 5 - Spring 27 Lec #7: uential Implementation 2 CS 5 - Spring 27 Lec #7: uential Implementation 22 Moore Verilog FSM for Ving Machine Mealy Verilog FSM for Ving Machine module ving (open, Clk,,, ); input Clk,,, ; put open; reg open; reg state; // state register reg next_state; parameter =, five =, ten = 2, fifteen = 3; or or state) : begin if () next_state = five; else if () next_state = ten; case else open = ; fifteen: begin next_state = ; if (!) next_state = fifteen; open = ; [] + [] [] [] + module ving (open, Clk,,, ); input Clk,,, ; put open; reg open; reg state; // state register reg next_state; reg next_open; parameter =, five =, ten = 2, fifteen = 3; or or state) : begin if () begin next_state = ten; next_open = ; else if () begin next_state = five; next_open = ; next_state = ; next_open = ; case / / / / / +/ ( + )/ / / / / if ( (! &&!)) state <= ; else state <= next_state; module if ( (! &&!)) begin state <= ; open <= ; state <= next_state; open <= next_open; module CS 5 - Spring 27 Lec #7: uential Implementation 23 CS 5 - Spring 27 Lec #7: uential Implementation 24

5 ! busy highway is intersected by a little used farmroad! etectors C sense the presence of cars waiting on the farmroad " with no car on farmroad, light remain green in highway direction " if vehicle on farmroad, highway lights go from Green to Yellow to Red, allowing the farmroad lights to become green " these stay green only as long as a farmroad car is detected but never longer than a set interval " when these are met, farm lights transition from Green to Yellow to Red, allowing highway to return to green " even if farmroad vehicles are waiting, highway gets at least a set interval as green! ssume you have an interval timer that generates: " a short time pulse (TS) and " a long time pulse (TL), " in response to a set (ST) signal. " TS is to be used for timing yellow lights and TL for green lights! Highway/farm road intersection farm road car sensors highway CS 5 - Spring 27 Lec #7: uential Implementation 25 CS 5 - Spring 27 Lec #7: uential Implementation 26! Tabulation of Inputs and Outputs inputs description description reset place FSM in initial state HG, HY, HR assert green/yellow/red highway lights C detect vehicle on the farm road FG, FY, FR assert green/yellow/red highway lights TS short time interval expired ST start timing a short or long interval TL long time interval expired! Tabulation of unique states some light configurations imply others state description S highway green (farm road red) S highway yellow (farm road red) S2 farm road green (highway red) S3 farm road yellow (highway red)! State iagram (TL C)' S S: HG TL C / ST S: HY S2: FG S3: FY TS' S S3 TL+C' / ST S2 (TL+C')' TS' CS 5 - Spring 27 Lec #7: uential Implementation 27 CS 5 - Spring 27 Lec #7: uential Implementation 28! Generate state table with symbolic states! Consider state assignments Inputs Present State ext State Outputs C TL TS ST H F HG HG Green Red HG HG Green Red HG HY Green Red HY HY Yellow Red HY FG Yellow Red FG FG Red Green FG FY Red Green FG FY Red Green FY FY Red Yellow FY HG Red Yellow S: HG = HY = FG = FY = S2: HG = HY = FG = FY = S3: HG = HY = FG = FY = (one-hot) CS 5 - Spring 27 Lec #7: uential Implementation 29 put encoding similar problem to state assignment (Green =, Yellow =, Red = ) Traffic Light Controller Verilog module traffic (ST, Clk,, C, TL, TS); input Clk,, C, TL, TS; put ST; reg ST; reg state; reg next_state; reg next_st; parameter S =, S =, S2 = 2, S3 = 3; or TL or TS or state) S: if (!(TL && C)) begin next_state = S; next_st = ; else if (TL C) begin next_state = S; next_st = ; case Clk) if () begin state <= S; ST <= ; state <= next_state; ST <= next_st; module TS' TL C S (TL C)' CS 5 - Spring 27 Lec #7: uential Implementation 3 S TL+C / ST S2 (TL+C')' S3 TL+C' / ST TS'

6 Logic for ifferent State ssignments Ving Machine Example Revisted (PL mapping)! S S = C TL' PS PS + TS PS' PS + TS PS PS' + C' PS PS + TL PS PS S = C TL PS' PS' + C TL' PS PS + PS' PS OPE = reset'(' + ' + + ) = reset'( + + ) = CLK ST = C TL PS' PS' + TS PS' PS + TS PS PS' + C' PS PS + TL PS PS H = PS H = PS' PS F = PS' F = PS PS'! S2 S = C TL PS' + TS' PS + C' PS' PS S = TS PS PS' + PS' PS + TS' PS PS ST = C TL PS' + C' PS' PS + TS PS H = PS H = PS PS' F = PS' F = PS PS! S3 S3 = C' PS2 + TL PS2 + TS' PS3 S2 = TS PS + C TL' PS2 S = C TL PS + TS' PS S = C' PS + TL' PS + TS PS3 ST = C TL PS + TS PS + C' PS2 + TL PS2 + TS PS3 H = PS3 + PS2 H = PS F = PS + PS F = PS3 Com CS 5 - Spring 27 Lec #7: uential Implementation 3 CS 5 - Spring 27 Lec #7: uential Implementation 32 Ving Machine Ving Machine (Retimed PL Mapping)! OPE = creates a combinational delay after and change! This can be corrected by retiming, i.e., move flip-flops and logic through each other to improve delay! OPE = reset'( + + )(' + ' + + ) = reset'(' ' + ')! Implementation now looks like a synchronous Mealy machine " Common for programmable devices to have FF at of logic OPE = reset'(' ' + ') CLK OPE CS 5 - Spring 27 Lec #7: uential Implementation 33 CS 5 - Spring 27 Lec #7: uential Implementation 34 uential Logic Implementation Summary! Models for representing sequential circuits " bstraction of sequential elements " Finite state machines and their state diagrams " Inputs/ " Mealy, Moore, and synchronous Mealy machines! Finite state machine design procedure " Verilog specification " eriving state diagram " eriving state transition table " etermining next state and put functions " Implementing combinational logic CS 5 - Spring 27 Lec #7: uential Implementation 35

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