Imperative Programming 2: Circuit simulation
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1 Imperative Programming 2: Circuit simulation Hongseok Yang University of Oxford
2 Scala is a general purpose programming language designed to express common programming patterns in a concise, elegant, type-safe way. It smoothly integrates features of object-oriented functional languages... From
3 Scala is a general purpose programming language designed to express common programming patterns in a concise, elegant, type-safe way. It smoothly integrates features of object-oriented functional languages... object, class, From inheritance, mutable state (var)
4 Scala is a general purpose programming language designed to express common programming patterns in a concise, elegant, type-safe way. It smoothly integrates features of object-oriented functional languages... From pattern matching, high-order function, lazy evaluation
5 Today we will study programming idioms that use features of OO FP together. Scala is a general purpose programming language designed to express common programming patterns in a concise, elegant, type-safe way. It smoothly integrates features of object-oriented functional languages... From
6 Today s lecture We will develop a circuit simulator that uses both OO FP features. Expected outcome: Students can use the prog. idioms in the simulator for solving new problems. Based on Chapter 8.
7 Has anyone written a even-driven program such as a GUI program or an Android app before?
8 What about a scheduler?
9 Two programming idioms In their basic form, both idioms use an object that stores a list of functions in its var field: var l : List[() => Unit] First idiom : To schedule process dynamically generated tasks. Second idiom : To manage tasks that should be triggered when a certain event happens.
10 First idiom: Work-list algorithm class Scheduler { var worklist : List[() => Unit] = Nil def add(work: () => Unit) { worklist ::= work def run() { while (!worklist.isempty) { val item::rest = worklist worklist = rest item()
11 First idiom: Work-list algorithm class Scheduler { var worklist : List[() => Unit] = Nil def add(work: () => Unit) { worklist ::= work def run() { while (!worklist.isempty) { val item::rest = worklist worklist = rest item(). item() can call add modify worklist. 2. A more sophisticated scheduling policy.
12 First idiom: Work-list algorithm class Scheduler { var worklist : List[() => Unit] = Nil def add(work: () => Unit) { worklist ::= work def run() { while (!worklist.isempty) { val item::rest = worklist worklist = rest item(). item() can call add modify worklist. 2. A more sophisticated scheduling policy.
13 Second idiom: Observer pattern (Scala version) class Counter { var observers : List[() => Unit] = Nil var x : Int = 0 def add(work: () => Unit) { observers ::= work def inc() { x += observers foreach (_ ()) def get : Int = x
14 Second idiom: Observer pattern (Scala version) class Counter { var observers : List[() => Unit] = Nil var x : Int = 0 def add(work: () => Unit) { observers ::= work work() def inc() { x += observers foreach (_ ()) def get : Int = x
15 Second idiom: Observer pattern (Scala version) class Counter { var observers : List[() => Unit] = Nil var x : Int = 0 def add(work: () => Unit) { observers ::= work work() def inc() { x += observers foreach (_ ()) def get : Int = x
16 Second idiom: Observer pattern (Scala version) class Counter { var observers : List[() => Unit] = Nil var x : Int = 0 def add(o: () => Unit) { observers ::= o o() def inc() { x += observers foreach (_ ()) def get : Int = x
17 Programming challenge: Circuit simulator The simulator should allow us to describe a circuit to run it.
18 Programming challenge: Circuit simulator The simulator should allow us to describe a circuit to run it. or not
19 Programming challenge: Circuit simulator The simulator should allow us to describe a circuit to run it. 0 or not
20 Programming challenge: Circuit simulator The simulator should allow us to describe a circuit to run it. or 0 0 not 0
21 Programming challenge: Circuit simulator The simulator should allow us to describe a circuit to run it. or 0 0 not 0
22 Programming challenge: Circuit simulator The simulator should allow us to describe a circuit to run it. or 0 0 not 0
23 Programming challenge: Circuit simulator The simulator should allow us to describe a circuit to run it. or 0 0 not 0
24 Programming challenge: Circuit simulator The simulator should allow us to describe a circuit to run it. or 0 not 0
25 Programming challenge: Circuit simulator The simulator should allow us to describe a circuit to run it. or not
26 Programming challenge: Circuit simulator The simulator should allow us to describe a circuit to run it. or not 0
27 Programming challenge: Circuit simulator The simulator should allow us to describe a circuit to run it. or 0 not 0
28 Programming challenge: Circuit simulator The simulator should allow us to describe a circuit to run it. or 0 not 0
29 Programming challenge: Circuit simulator The simulator should allow us to describe a circuit to run it. or not val a,b = new Wire val d,e = new Wire val s,c = new Wire orgate(a,b,d) Gate(a,b,c) inverter(c,e) Gate(d,e,s) a setsignal true b setsignal false run
30 Programming challenge: Circuit simulator The simulator should allow us to describe a circuit to run it. 0 or not val a,b = new Wire val d,e = new Wire val s,c = new Wire orgate(a,b,d) Gate(a,b,c) inverter(c,e) Gate(d,e,s) a setsignal true b setsignal false run()
31 Programming challenge: [Q] Would you model wires as observables (corresponding to counters) or observers? Circuit simulator What about gates? The simulator should allow us to describe a circuit to run it. 0 or not val a,b = new Wire val d,e = new Wire val s,c = new Wire orgate(a,b,d) Gate(a,b,c) inverter(c,e) Gate(d,e,s) a setsignal true b setsignal false run()
32 MySim curtime = 2 worklist = [(3,t), (5,t2), (9,t3)] MySim schedules tasks. Work-list algorithm. (3,t) represents a task that should run function t at time 3.
33 MySim curtime = 2 worklist = [(3,t), (5,t2), (9,t3)] MySim schedules tasks. Work-list algorithm. (3,t) represents a task that should run function t at time 3. wire2 sigval = false obs = [f] wire wire3 sigval = false obs = [g] sigval = true obs = [h, h2] wiren uses the observer pattern. Logic gates are functions, observers of wires.
34 MySim curtime = 2 worklist = [(3,t), (5,t2), (9,t3)] MySim schedules tasks. Work-list algorithm. (3,t) represents a task that should run function t at time 3. wire2 wire sigval = false wire3 obs = [f] sigval = false wire2 wire obs = [g] gate sigval = true wire3 obs = [h, h2] wiren uses the observer pattern. Logic gates are functions, observers of wires.
35 MySim curtime = 3 worklist = [(5,t2), (9,t3)] MySim schedules tasks. Work-list algorithm. (3,t) represents a task that should run function t at time 3. wire2 wire sigval = true wire3 obs = [f] sigval = false wire2 wire obs = [g] gate sigval = true wire3 obs = [h, h2] wiren uses the observer pattern. Logic gates are functions, observers of wires.
36 MySim curtime = 3 worklist = [(5,t2), (9,t3)] MySim schedules tasks. Work-list algorithm. (3,t) represents a task that should run function t at time 3. wire2 wire sigval = true wire3 obs = [f] sigval = false wire2 wire obs = [g] gate sigval = true wire3 obs = [h, h2] wiren uses the observer pattern. Logic gates are functions, observers of wires.
37 MySim curtime = 3 worklist = [(4,t4), (5,t2), (9,t3)] MySim schedules tasks. Work-list algorithm. (3,t) represents a task that should run function t at time 3. wire2 wire sigval = true wire3 obs = [f] sigval = false wire2 wire obs = [g] gate sigval = true wire3 obs = [h, h2] wiren uses the observer pattern. Logic gates are functions, observers of wires.
38 MySim curtime = 4 worklist = [(5,t2), (9,t3)] MySim schedules tasks. Work-list algorithm. (3,t) represents a task that should run function t at time 3. wire2 wire sigval = true wire3 obs = [f] sigval = true wire2 wire obs = [g] gate sigval = true wire3 obs = [h, h2] wiren uses the observer pattern. Logic gates are functions, observers of wires.
39 Class hierarchy Work-list algo. Simulation Class & methods for wires & gates. MySim. Circuit Wire Nested class. wire, wire2,... Observer pattern.
40 Class hierarchy Work-list algo. Simulation Class & methods for wires & gates. MySim. Circuit Wire Nested class. wire, wire2,... Observer pattern.
41 abstract class Simulation { type Work = (Int, ()=>Unit) var curtime = 0 var worklist: List[Work] = Nil Work-list algo. Tasks sorted by time. private def insert(l:list[work], w:work): List[Work] = if (l.isempty w._ < l.head._) w::l else l.head :: insert(l.tail, w) def afterdelay(delay: Int)(block: => Unit) { val work = (curtime + delay, () => block) worklist = insert(worklist, work) def run() { afterdelay(0){ println( *** simulation start *** ) while (!worklist.isempty) { val (time, task) :: rest = worklist worklist = rest; curtime = time task()
42 abstract class Simulation { type Work = (Int, ()=>Unit) var curtime = 0 var worklist: List[Work] = Nil Work-list algo. Tasks sorted by time. private def insert(l:list[work], w:work): List[Work] = if (l.isempty w._ < l.head._) w::l else l.head :: insert(l.tail, w) def afterdelay(delay: Int)(block: => Unit) { val work = (curtime + delay, () => block) worklist = insert(worklist, work) def run() { afterdelay(0){ println( *** simulation start *** ) while (!worklist.isempty) { val (time, task) :: rest = worklist worklist = rest; curtime = time task()
43 abstract class Simulation { type Work = (Int, ()=>Unit) var curtime = 0 var worklist: List[Work] = Nil Work-list algo. Tasks sorted by time. private def insert(l:list[work], w:work): List[Work] = if (l.isempty w._ < l.head._) w::l else l.head :: insert(l.tail, w) def afterdelay(delay: Int)(block: => Unit) { val work = (curtime + delay, () => block) worklist = insert(worklist, work) def run() { afterdelay(0){ println( *** simulation start *** ) while (!worklist.isempty) { val (time, task) :: rest = worklist worklist = rest; curtime = time task() afterdelay adds a new work item. block is a by-name parameter. run executes items in worklist.
44 abstract class Simulation { type Work = (Int, ()=>Unit) var curtime = 0 var worklist: List[Work] = Nil Work-list algo. Tasks sorted by time. private def insert(l:list[work], w:work): List[Work] = if (l.isempty w._ < l.head._) w::l else l.head :: insert(l.tail, w) def afterdelay(delay: Int)(block: => Unit) { val work = (curtime + delay, () => block) worklist = insert(worklist, work) def run() { afterdelay(0){ println( *** simulation start *** ) while (!worklist.isempty) { val (time, task) :: rest = worklist worklist = rest; curtime = time task() afterdelay adds a new work item. block is a by-name parameter. run executes items in worklist.
45 abstract class Simulation { type Work = (Int, ()=>Unit) var curtime = 0 var worklist: List[Work] = Nil Work-list algo. Tasks sorted by time. private def insert(l:list[work], w:work): List[Work] = if (l.isempty w._ < l.head._) w::l else l.head :: insert(l.tail, w) def afterdelay(delay: Int)(block: => Unit) { val work = (curtime + delay, () => block) worklist = insert(worklist, work) [Q] Complete the def n of run. def run() { afterdelay(0){ println( *** simulation start *** ) while (!worklist.isempty) { val (time, task) :: rest = worklist worklist = rest; curtime = time task() afterdelay adds a new work item. block is a by-name parameter. run executes items in worklist.
46 abstract class Simulation { type Work = (Int, ()=>Unit) var curtime = 0 var worklist: List[Work] = Nil Work-list algo. Tasks sorted by time. private def insert(l:list[work], w:work): List[Work] = if (l.isempty w._ < l.head._) w::l else l.head :: insert(l.tail, w) def afterdelay(delay: Int)(block: => Unit) { val work = (curtime + delay, () => block) worklist = insert(worklist, work) [Q] Complete the def n of run. def run() { afterdelay(0){ println( *** simulation start *** ) while (!worklist.isempty) { val (time, task) :: rest = worklist worklist = rest; curtime = time task() afterdelay adds a new work item. block is a by-name parameter. run executes items in worklist.
47 abstract class Simulation { type Work = (Int, ()=>Unit) var curtime = 0 var worklist: List[Work] = Nil Work-list algo. Tasks sorted by time. private def insert(l:list[work], w:work): List[Work] = if (l.isempty w._ < l.head._) w::l else l.head :: insert(l.tail, w) def afterdelay(delay: Int)(block: => Unit) { val work = (curtime + delay, () => block) worklist = insert(worklist, work) [Q2] Find a resource invariant. def run() { afterdelay(0){ println( *** simulation start *** ) while (!worklist.isempty) { val (time, task) :: rest = worklist worklist = rest; curtime = time task() afterdelay adds a new work item. block is a by-name parameter. run executes items in worklist.
48 Class hierarchy Work-list algo. Simulation Class & methods for wires & gates. MySim. Circuit Wire Nested class. wire, wire2,... Observer pattern.
49 abstract class Circuit extends Simulation { def InverterDelay: Int def AndGateDelay: Int def OrGateDelay: Int Inheritance enables code reuse. Delays to be specified later. class Wire { private var sigval = false var observers: List[Work] = List() def getsignal = sigval def setsignal(s: Boolean) = if (s!= sigval) { sigval = s; observers foreach (_()) def addobs(o: ()=>Unit) { observers = o :: observers; o() def inverter(input: Wire, output: Wire) { def invertaction() { val inputsig = input.getsignal afterdelay(inverterdelay) { output setsignal!inputsig input addobs invertaction() def Gate(a: Wire, a2: Wire, output: Wire)... def orgate(a: Wire, a2: Wire, output: Wire)...
50 abstract class Circuit extends Simulation { def InverterDelay: Int def AndGateDelay: Int def OrGateDelay: Int Inheritance enables code reuse. Delays to be specified later. class Wire { private var sigval = false var observers: List[Work] = List() def getsignal = sigval def setsignal(s: Boolean) = if (s!= sigval) { sigval = s; observers foreach (_()) def addobs(o: ()=>Unit) { observers = o :: observers; o() def inverter(input: Wire, output: Wire) { def invertaction() { val inputsig = input.getsignal afterdelay(inverterdelay) { output setsignal!inputsig input addobs invertaction() def Gate(a: Wire, a2: Wire, output: Wire)... def orgate(a: Wire, a2: Wire, output: Wire)...
51 abstract class Circuit extends Simulation { def InverterDelay: Int def AndGateDelay: Int def OrGateDelay: Int Inheritance enables code reuse. Delays to be specified later. class Wire { private var sigval = false Nested class. var observers: List[Work] = Nil def getsignal = sigval def setsignal(s: Boolean) = if (s!= sigval) { sigval = s; observers foreach (_()) def addobs(o: ()=>Unit) { observers = o :: observers; o() Observer pattern. def inverter(input: Wire, output: Wire) { def invertaction() { val inputsig = input.getsignal afterdelay(inverterdelay) { output setsignal!inputsig input addobs invertaction() def Gate(a: Wire, a2: Wire, output: Wire)... def orgate(a: Wire, a2: Wire, output: Wire)...
52 abstract class Circuit extends Simulation { def InverterDelay: Int def AndGateDelay: Int def OrGateDelay: Int Inheritance enables code reuse. Delays to be specified later. class Wire { private var sigval = false var observers: List[()=>Unit] = Nil def getsignal = sigval def setsignal(s: Boolean) = if (s!= sigval) { sigval = s; observers foreach (_()) def addobs(o: ()=>Unit) { observers ::= o; o() Nested class. Observer pattern. def inverter(input: Wire, output: Wire) { def invertaction() { val inputsig = input.getsignal afterdelay(inverterdelay) { output setsignal!inputsig input addobs invertaction() def Gate(a: Wire, a2: Wire, output: Wire)... def orgate(a: Wire, a2: Wire, output: Wire)...
53 abstract class Circuit extends Simulation { def InverterDelay: Int def AndGateDelay: Int def OrGateDelay: Int Inheritance enables code reuse. Delays to be specified later. class Wire { private var sigval = false var observers: List[()=>Unit] = Nil def getsignal = sigval def setsignal(s: Boolean) = if (s!= sigval) { sigval = s; observers foreach (_()) def addobs(o: ()=>Unit) { observers ::= o; o() Nested class. Observer pattern. def inverter(input: Wire, output: Wire)... def invertaction() { val inputsig = input.getsignal afterdelay(inverterdelay) { output setsignal!inputsig input addobs invertaction() def Gate(a: Wire, a2: Wire, output: Wire)... def orgate(a: Wire, a2: Wire, output: Wire)...
54 abstract class Circuit extends Simulation { def InverterDelay: Int def AndGateDelay: Int def OrGateDelay: Int Inheritance enables code reuse. Delays to be specified later. class Wire { private var sigval = false var observers: List[()=>Unit] = Nil def getsignal = sigval def setsignal(s: Boolean) = if (s!= sigval) { sigval = s; observers foreach (_()) def addobs(o: ()=>Unit) { observers ::= o; o() Nested class. Observer pattern. Register an obs., def inverter(input: Wire, output: Wire) { def invertaction()... { val inputsig = input.getsignal afterdelay(inverterdelay) { output setsignal!inputsig input addobs invertaction def Gate(a: Wire, a2: Wire, output: Wire)... def orgate(a: Wire, a2: Wire, output: Wire)... which adds a task.
55 abstract class Circuit extends Simulation { def InverterDelay: Int def AndGateDelay: Int def OrGateDelay: Int Inheritance enables code reuse. Delays to be specified later. class Wire { private var sigval = false var observers: List[()=>Unit] = Nil def getsignal = sigval def setsignal(s: Boolean) = if (s!= sigval) { sigval = s; observers foreach (_()) def addobs(o: ()=>Unit) { observers ::= o; o() Nested class. Observer pattern. Register an obs., def inverter(input: Wire, output: Wire) { def invertaction() { val inputsig = input.getsignal afterdelay(inverterdelay) { output setsignal!inputsig input addobs invertaction def Gate(a: Wire, a2: Wire, output: Wire)... def orgate(a: Wire, a2: Wire, output: Wire)... which adds a task.
56 abstract class Circuit extends Simulation { def InverterDelay: Int def AndGateDelay: Int def OrGateDelay: Int Inheritance enables code reuse. Delays to be specified later. class Wire { private var sigval = false var observers: List[()=>Unit] = Nil def getsignal = sigval def setsignal(s: Boolean) = if (s!= sigval) { sigval = s; observers foreach (_()) def addobs(o: ()=>Unit) { observers ::= o; o() Nested class. Observer pattern. Register an obs., def inverter(input: Wire, output: Wire) { def invertaction() { val inputsig = input.getsignal afterdelay(inverterdelay) { output setsignal!inputsig input addobs invertaction def Gate(a: Wire, a2: Wire, output: Wire)... def orgate(a: Wire, a2: Wire, output: Wire)... which adds a task. [Q] Complete the def ns of Gate orgate.
57 abstract class Circuit extends Simulation { def InverterDelay: Int def AndGateDelay: Int def OrGateDelay: Int Inheritance enables code reuse. Delays to be specified later. class Wire { private var sigval = false var observers: List[Work] = Nil def getsignal = sigval def setsignal(s: Boolean) = def if Gate(a: (s!= sigval) Wire, { sigval a2: Wire, = s; output: observers Wire) foreach { (_()) def def addobs(o: Action() ()=>Unit) = { { observers ::= o; o() val asig = a.getsignal val a2sig = a2.getsignal def inverter(input: afterdelay(andgatedelay) Wire, output: { Wire) { def invertaction() output setsignal { (asig && a2sig) val inputsig = input.getsignal afterdelay(inverterdelay) { output setsignal!inputsig a addobs Action input a2 addobs Action invertaction def Gate(a: Wire, a2: Wire, output: Wire)... def orgate(a: Wire, a2: Wire, output: Wire)... Nested class. Observer pattern. Register an obs., which adds a task. [Q] Complete the def ns of Gate orgate.
58 Creating MySim object MySim extends Circuit { def InverterDelay = def AndGateDelay = 3 def OrGateDelay = 5 Creates a singleton object MySim that inherits specialises the abstract class Circuit. Simpler than the usual alternative.
59 Creating MySim object MySim extends Circuit { def InverterDelay = def AndGateDelay = 3 def OrGateDelay = 5 Creates a singleton object MySim that inherits specialises the abstract class Circuit. Simpler than the usual alternative. class MySimClass extends Circuit { def InverterDelay = def AndGateDelay = 3 def OrGateDelay = 5 val MySim = new MySimClass
60 Summary Two idioms for using high-order function mutable state together.. Work-list algorithm. 2. Observer pattern. I presented a simpler version of circuit simulation. Look at the textbook for a full version. Read Chapter 8.
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