MIPS-Lite Single-Cycle Control

Transcription

1 MIPS-Lite Single-Cycle Control COE68: Computer Organization and Architecture Dr. Gul N. Khan Electrical and Computer Engineering Ryerson University Overview Single cycle Data path Review Data path Analysis for different instructions Data path Control Signals. ALU control Signals Decoding Control Signals Single-cycle Control and its Performance Part of section 4.4 from the Tetbook G.Khan Computer Organization & Architecture-COE68: MIPS-Lite Control Page:

2 Overview 5 steps to design a processor. Analyze instruction set => data path requirements 2. Select set of data path components & establish clock methodology 3. Assemble data path meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that affects the register transfer. 5. Assemble the control logic MIPS makes it easier Single cycle data path CPI= G.Khan Computer Organization & Architecture-COE68: MIPS-Lite Control Page:2

3 A Single Cycle Data path We have everything ecept control signals (underline). How to generate the control signals? Instruction<3:> npc_sel Instruction Fetch Unit RegDst Mu Rs Rs Imm6 RegWr ALUctr busa Zero MemWr MemtoReg Rw Ra Rb busw -bit Registers busb WrEn Adr Data In imm6 Data 6 Memory ALUSrc Etender EtOp Mu ALU <2:25> <6:2> <:5> <:5> Mu G.Khan Computer Organization & Architecture-COE68: MIPS-Lite Control Page:3

4 The Add Instruction 3 add op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits mem[pc] rd, rs, rt R[rd] <= R[rs] + R[rt] PC <= PC + 4 Fetch the instruction from memory Actual operation Calculate the net instruction s address Instruction Fetch Unit at the Beginning npc_sel Inst Memory Adr Instruction<3:> 4 imm6 PC Et Adder Adder Mu PC G.Khan Computer Organization & Architecture-COE68: MIPS-Lite Control Page:4

5 Data path during Add R[rd] <= R[rs] + R[rt] npc_sel= +4 Instruction Fetch Unit RegDst = Mu Rs ALUctr = Add RegWr = busa Zero Rw Ra Rb busw -bit Registers busb imm6 6 EtOp = Etender Mu ALU Data In ALUSrc = <2:25> <6:2> WrEn Adr Data Memory <:5> <:5> Rs Imm6 MemtoReg = MemWr = Mu Memory Read when MemWr = G.Khan Computer Organization & Architecture-COE68: MIPS-Lite Control Page:5

6 IFU at the end of Add PC <= PC + 4 This is the same for all instructions ecept: Branch and Jump npc_sel Inst Memory Adr Instruction<3:> 4 Adder PC Mu imm6 Adder G.Khan Computer Organization & Architecture-COE68: MIPS-Lite Control Page:6

7 Data path during ori R[rt] <= R[rs] or ZeroEt[Imm6] Instruction<3:> npc_sel= +4 Instruction Fetch Unit RegDst = Mu Rs ALUctr = Or Rs Imm6 RegWr = MemtoReg = busa Zero MemWr = Rw Ra Rb busw -bit Registers busb WrEn Adr Data In imm6 Data 6 Memory ALUSrc = Etender EtOp = Zero Etend Mu ALU <2:25> <6:2> <:5> <:5> Mu The Rs field is fed to Ra address port: R[rs] is placed on busa. Other ALU operand will come from the immediate field. G.Khan Computer Organization & Architecture-COE68: MIPS-Lite Control Page:7

8 Data path during Load R[rt] <= Data Memory {R[rs] + SignEt[imm6]} RegDst = Mu RegWr = busw Rs busa Rw Ra Rb -bit Registers busb imm6 6 Etender EtOp = npc_sel= +4 Mu Instruction Fetch Unit ALUctr = Add ALU Data In ALUSrc = Instruction<3:> <2:25> <6:2> <:5> WrEn Adr Data Memory <:5> Rs Imm6 MemtoReg = Zero MemWr = Addres Mu Sign Etend Add R[rs] to Sign Etended Immediate field to form memory address. Use memory address to access memory and write data back to R[rt]. G.Khan Computer Organization & Architecture-COE68: MIPS-Lite Control Page:8

9 Data path during Store Data Memory {R[rs] + SignEt[imm6]} <= R[rt] Instruction<3:> npc_sel= +4 Instruction Fetch Unit RegDst = Mu Rs ALUctr Rs Imm6 RegWr = = Add MemtoReg = busa Zero MemWr = Rw Ra Rb busw -bit Registers busb WrEn Adr Data In imm6 Data 6 Memory ALUSrc = Etender EtOp = Mu ALU <2:25> <6:2> <:5> <:5> Mu Store sends the contents of register specified by to data memory. G.Khan Computer Organization & Architecture-COE68: MIPS-Lite Control Page:9

10 Data path during Branch if (R[rs] - R[rt] == ) then Zero <= ; else Zero <= Instruction<3:> npc_sel= Br Instruction Fetch Unit RegDst = Mu ALUctr = RegWr = Rs Rs Subtract busa Zero MemWr = Rw Ra Rb busw -bit Registers busb WrEn Adr Data In imm6 Data 6 Memory ALUSrc = Etender EtOp = Don t care Mu ALU <2:25> <6:2> <:5> <:5> Imm6 MemtoReg = Mu Subtracts the register specified in the field from the register specified in the Rs field and set Zero condition accordingly. G.Khan Computer Organization & Architecture-COE68: MIPS-Lite Control Page:

11 IFU at the End of Branch npc_sel Inst Memory Adr Instruction<3:> 4 Adder PC Mu imm6 Adder Sign Etend PC = PC Imm6 When the branch condition Zero is true (Zero = ). G.Khan Computer Organization & Architecture-COE68: MIPS-Lite Control Page:

12 Given Data path: RTL => Control Instruction<3:> Inst Memory Adr Op <2:25> Fun <2:25> <6:2> <:5> <:5> Rs Imm6 Control npc_sel RegWr RegDst EtOp ALUSrc ALUctr MemWr MemtoReg Equal DATA PATH 4 Add Instruction [3 26] Control RegDst Branch MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite Shift left 2 Add ALU result M u PC Read address Instruction memory Instruction [3 ] Instruction [25 2] Instruction [2 6] Instruction [5 ] M u Read register Read data Read register 2 Registers Read Write data 2 register Write data M u Zero ALU ALU result Address Write data Data memory Read data M u Instruction [5 ] 6 Sign etend ALU control Instruction [5 ] G.Khan Computer Organization & Architecture-COE68: MIPS-Lite Control Page:2

13 Summary of Control Signals inst Register Transfer ADD R[rd] <= R[rs] + R[rt]; PC <= PC + 4 ALUsrc = busb, ALUctr = add, RegDst = rd, RegWr, npc_sel = +4 SUB R[rd] <= R[rs] R[rt]; PC <= PC + 4 ALUsrc = busb, ALUctr = sub, RegDst = rd, RegWr, npc_sel = +4 ORi R[rt] <= R[rs] + zero_et(imm6); PC <= PC + 4 ALUsrc = Imm, Etop = Z, ALUctr = or, RegDst = rt, RegWr, npc_sel = +4 LOAD R[rt] <= MEM[ R[rs] + sign_et(imm6)]; PC <= PC + 4 ALUsrc = Imm, Etop = Sn, ALUctr = add, MemWr =, MemtoReg, RegDst = rt, RegWr, npc_sel = +4 STORE MEM[ R[rs] + sign_et(imm6)] <= R[rt]; PC <= PC + 4 ALUsrc = Imm, Etop = Sn, ALUctr = add, MemWr =, npc_sel = +4 BEQ if ( R[rs] == R[rt] ) then PC <= PC + sign_et(imm6)] else PC <= PC + 4 npc_sel = Br, ALUctr = sub G.Khan Computer Organization & Architecture-COE68: MIPS-Lite Control Page:3

14 Summary of Control Signals See func Don t Care op add sub ori lw sw beq jump RegDst ALUSrc MemtoReg RegWr MemWr npcsel Jump EtOp ALUctr <2:> Add Subtract Or Add Add Subtract R-type op rs rt rd shamt funct add, sub I-type op rs rt immediate ori, lw, sw, beq J-type op target address jump G.Khan Computer Organization & Architecture-COE68: MIPS-Lite Control Page:4

15 Local Decoding op R - type ori lw sw beq jump RegDst ALUSrc MemtoReg RegWrite MemWrite Branch Jump EtOp ALUop <N:> R - type Or Add Add Subtract func op ALU ALUctr Main 6 Control 6 Control ALUop 3 (Local) N ALU G.Khan Computer Organization & Architecture-COE68: MIPS-Lite Control Page:5

16 The Encoding of ALUop ALUop has to be 2 bits wide to represent: () R-type instructions I-type instructions that require the ALU to perform: - (2) Or, (3) Add, and (4) Subtract For full MIPS, ALUop has to be 3 bits to represent: () R-type instructions I-type instructions that require the ALU to perform: (2) Or, (3) Add, (4) Subtract, and (5) And (e.g. andi) R-type ori lw sw beq jump ALUop (Symbolic) R-type Or Add Add Subtract ALUop<2:> funct<5:> Instruction Operation ALUctr<2:> ALU Operation add Add subtract Subtract and And or Or set-on-less-than Set-on-less-than G.Khan Computer Organization & Architecture-COE68: MIPS-Lite Control Page:6

17 The Truth Table for ALUctr ALUop R-type ori lw sw beq (Symbolic) R-type Or Add Add Subtract ALUop<2:> funct<3:> Instruction Op. add subtract and or set-on-less-than ALUop func ALU ALUctr bit<2> bit<> bit<> bit<3> bit<2> bit<> bit<> Operation bit<2> bit<> bit<> Add Subtract Or Add Subtract And Or Set on < G.Khan Computer Organization & Architecture-COE68: MIPS-Lite Control Page:7

18 The Logic Equation for ALUctr<2> ALUop func bit<2> bit<> bit<> bit<3> bit<2> bit<> bit<> ALUctr<2> This makes func<3> a don t care ALUctr<2> = ALUop<2> & ALUop<> + ALUop<2> & func<2> & func<> & func<> The Logic Equation for ALUctr<> ALUop func bit<2> bit<> bit<> bit<3> bit<2> bit<> bit<> ALUctr<> ALUctr<> = ALUop<2> & ALUop<> + ALUop<2> & func<2> & func<> G.Khan Computer Organization & Architecture-COE68: MIPS-Lite Control Page:8

19 ALU Control Block The Logic Equation for ALUctr<> ALUop func bit<2> bit<> bit<> bit<3> bit<2> bit<> bit<> ALUctr<> ALUctr<> = ALUop<2> & ALUop<> + ALUop<2> & func<3> & func<2> & func<> & func<> + ALUop<2> & func<3> & func<2> & func<> & func<> func 6 ALUop 3 ALU Control (Local) ALUctr 3 G.Khan Computer Organization & Architecture-COE68: MIPS-Lite Control Page:9

20 Logic for each control signal npc_sel <= if (OP == BEQ) then EQUAL else ALUsrc <= if (OP == R-type ) then busb else immed ALUctr <= if (OP == R-type ) then funct elseif (OP == ORi) then OR elseif (OP == BEQ) then sub else add EtOp <= if (OP == ORi) then zero else sign MemWr <= (OP == Store) MemtoReg <= (OP == Load) RegWr <= if ((OP == Store) (OP == BEQ)) then else RegDst <= if ((OP == Load) (OP == ORi)) then else G.Khan Computer Organization & Architecture-COE68: MIPS-Lite Control Page:2

21 Truth Table for Main Control op Main 6 Control RegDst ALUSrc : ALUop 3 func ALU ALUctr 6 Control 3 (Local) op R - type ori lw sw beq jump RegDst ALUSrc MemtoReg RegWr MemWr Branch Jump EtOp ALUop (Symbolic) R - type Or Add Add Subtract ALUop <2> ALUop <> ALUop <> G.Khan Computer Organization & Architecture-COE68: MIPS-Lite Control Page:2

22 The Truth Table for RegWrite op R-type ori lw sw beq jump RegWrite RegWrite = R-type + ori + lw = op<5> & op<4> & op<3> & op<2> & op<> & op<> + op<5> & op<4> & op<3> & op<2> & op<> & op<> + op<5> & op<4> & op<3> & op<2> & op<> & op<> op<5>.. <> op<5>.. <> op<5>.. op<5>.. op<5>.. op<5>.. <> <> <> op<> R - type ori lw sw beq jump RegWr G.Khan Computer Organization & Architecture-COE68: MIPS-Lite Control Page:22

23 op<5>.. <> op<5>.. PLA Implementation <> op<5>.. <> op<5>.. op<5>.. op<5>.. <> <> op<> R - type ori lw sw beq jump RegWr ALUSrc RegDst MemtoReg MemWr Branch Jump EtOp ALUop <2> ALUop <> ALUop <> G.Khan Computer Organization & Architecture-COE68: MIPS-Lite Control Page:23

24 A Single Cycle Processor ALUop ALU 3 ALUctr RegDst func Control op Main 3 6 Control ALUSrc Instr<5:> 6 Instr<3:26> : Instruction<3:> npc_sel Instruction Fetch Unit RegDst Mu Rs Rs Imm6 RegWr ALUctr busa Zero MemWr MemtoReg Rw Ra Rb busw -bit Registers busb WrEn Adr Data In imm6 Data Instr<5:> 6 Memory ALUSrc Etender Mu ALU <2:25> <6:2> <:5> <:5> Mu G.Khan Computer Organization & Architecture-COE68: MIPS-Lite Control Page:24

25 Worst Case Timing (Load) PC Old Value Rs,,, Op, Func ALUctr -to-q New Value Old Value Old Value Instruction Memoey Access Time New Value Delay through Control Logic New Value EtOp Old Value New Value ALUSrc Old Value New Value MemtoReg Old Value New Value Register RegWr Old Value New Value Write Occurs Register File Access Time busa Old Value New Value Delay through Etender & Mu busb Old Value New Value ALU Delay Address Old Value New Value Data Memory Access Time busw Old Value New G.Khan Computer Organization & Architecture-COE68: MIPS-Lite Control Page:25

26 Single Cycle Processor: Drawback Long cycle time: Cycle time must be long enough for the load instruction: PC s Clock -to-q + Instruction Memory Access Time + Register File Access Time + ALU Delay (address calculation) + Data Memory Access Time + Register File Setup Time + Clock Skew Cycle time for load is much longer than needed for all other instructions. More Problems what if we had a more complicated instruction like floating point? wasteful of area One Solution: Use a smaller cycle time Different instructions take different numbers of cycles a multi-cycle data path G.Khan Computer Organization & Architecture-COE68: MIPS-Lite Control Page:26

27 Single-cycle CPU Performance Eample: CPU-units operation time Memory: 2ps, ALU/Adder:ps Reg-File: 5ps Assume other hardware units have zero delay and following instruction mi. Loads: 25%, Stores: %, ALU instructions: 45% Branches: 5%, Jumps: 5% Compare the following two implementations. Each instruction operates in clock cycle of a fied length. (CPI = ) Each instruction eecutes in clock cycle using a variable-length clock, which for each instruction is only as long as it needs to be (Impractical approach) For both Implementations: Instruction Count and CPI are same. When CPI = : CPU EXE-Time = Inst. Count Clock-Cycle Time G.Khan Computer Organization & Architecture-COE68: MIPS-Lite Control Page:27

28 Single-cycle CPU Performance Critical Path for Variable-Length clock CPU Instructions CPU units used by the Inst. Class R-type IF Reg Access ALU Reg Access Load IF Reg Access ALU Mem Access Reg-Wr Store IF Reg Access ALU Mem Access Branch IF Reg Access ALU Jump IF Instruction Inst. Reg. ALU Data Reg. Total Class Mem Read Op Mem Write R-type ps Load ps Store ps Branch ps Jump ps For Variable Clock machine, clock cycle varies from 2ps to 6ps. Average-time/instruction = 6*.25+55*.+4*.45+35*.5+2*.5 = 447.5ps Performance Ratio = 6/447.5 =.34 G.Khan Computer Organization & Architecture-COE68: MIPS-Lite Control Page:28

29 Multi-cycle Approach We will be reusing functional units. ALU used to compute address and to increment PC Memory used for instruction and data. Our control signals will not be determined solely by instruction e.g., what should the ALU do for a subtract instruction? We ll use a finite state machine for control G.Khan Computer Organization & Architecture-COE68: MIPS-Lite Control Page:29