# Week 10: Assembly Programming

Save this PDF as:

Size: px
Start display at page:

## Transcription

1 Week 10: Assembly Programming

2 Arithmetic instructions Instruction Opcode/Function Syntax Operation add \$d, \$s, \$t \$d = \$s + \$t addu \$d, \$s, \$t \$d = \$s + \$t addi \$t, \$s, i \$t = \$s + SE(i) addiu \$t, \$s, i \$t = \$s + SE(i) div \$s, \$t lo = \$s / \$t; hi = \$s % \$t divu \$s, \$t lo = \$s / \$t; hi = \$s % \$t mult \$s, \$t hi:lo = \$s * \$t multu \$s, \$t hi:lo = \$s * \$t sub \$d, \$s, \$t \$d = \$s - \$t subu \$d, \$s, \$t \$d = \$s - \$t Note: hi and lo refer to the high and low bits referred to in the register slide. SE = sign extend.

3 Logical instructions Instruction Opcode/Function Syntax Operation and \$d, \$s, \$t \$d = \$s & \$t andi \$t, \$s, i \$t = \$s & ZE(i) nor \$d, \$s, \$t \$d = ~(\$s \$t) or \$d, \$s, \$t \$d = \$s \$t ori \$t, \$s, i \$t = \$s ZE(i) xor \$d, \$s, \$t \$d = \$s ^ \$t xori \$t, \$s, i \$t = \$s ^ ZE(i) Note: ZE = zero extend (pad upper bits with 0 value).

4 Shift instructions Instruction Opcode/Function Syntax Operation sll \$d, \$t, a \$d = \$t << a sllv \$d, \$t, \$s \$d = \$t << \$s sra \$d, \$t, a \$d = \$t >> a srav \$d, \$t, \$s \$d = \$t >> \$s srl \$d, \$t, a \$d = \$t >>> a srlv \$d, \$t, \$s \$d = \$t >>> \$s Note: srl = shift right logical, and sra = shift right arithmetic. The v denotes a variable number of bits, specified by \$s.

5 Data movement instructions Instruction Opcode/Function Syntax Operation mfhi \$d \$d = hi mflo \$d \$d = lo mthi \$s hi = \$s mtlo \$s lo = \$s These are instructions for operating on the HI and LO registers described earlier.

6 QtSpim MIPS Simulator ú Allow us to run & test assembly code ú Can run program or step-by-step ú Can view registers in binary/decimal/hex ú Not particularly well documented May need to fiddle with settings to get it working properly Main thing: want a simple (not a bare) machine

7 Formatting Assembly Code 3 columns ú Labels ú Code ú Comments Start with.text (we ll see other options later) First line of code to run = label: main

8 Time to write our first assembly program

9 Time for more instructions!

10 Control flow in assembly Not all programs follow a linear set of instructions. ú Some operations require the code to branch to one section of code or another (if/else). ú Some require the code to jump back and repeat a section of code again (for/while). For this, we have labels on the left-hand side that indicate the points that the program flow might need to jump to. ú References to these points in the assembly code are resolved at compile time to offset values for the program counter.

11 Branch instructions Instruction Opcode/Function Syntax Operation beq \$s, \$t, label if (\$s == \$t) pc ß label bgtz \$s, label if (\$s > 0) pc ß label blez \$s, label if (\$s <= 0) pc ß label bne \$s, \$t, label if (\$s!= \$t) pc ß label Branch operations are key when implementing if statements and while loops. The labels are memory locations, assigned to each label at compile time.

12 Jump instructions Instruction Opcode/Function Syntax Operation j label pc ß label jal label \$ra = pc; pc ß label jalr \$s \$ra = pc; pc = \$s jr \$s pc = \$s jal = jump and link. ú Register \$31 (aka \$ra) stores the address that s used when returning from a subroutine. Note: jr and jalr are not j-type instructions.

13 Comparison instructions Instruction Opcode/Function Syntax Operation slt \$d, \$s, \$t \$d = (\$s < \$t) sltu \$d, \$s, \$t \$d = (\$s < \$t) slti \$t, \$s, i \$t = (\$s < SE(i)) sltiu \$t, \$s, i \$t = (\$s < SE(i)) Note: Comparison operation stores a one in the destination register if the less-than comparison is true, and stores a zero in that location otherwise.

14 If/Else statements in MIPS if ( i == j ) i++; else j--; j += i; Strategy for if/else statements: ú Test condition, and jump to if logic block whenever condition is true. ú Otherwise, perform else logic block, and jump to first line after if logic block.

15 Translated if/else statements # \$t1 = i, \$t2 = j main: beq \$t1, \$t2, IF # branch if ( i == j ) addi \$t2, \$t2, -1 # j-- j END # jump over IF IF: addi \$t1, \$t1, 1 # i++ END: add \$t2, \$t2, \$t1 # j += i Alternately, you can branch on the else condition first: # \$t1 = i, \$t2 = j main: bne \$t1, \$t2, ELSE # branch if! ( i == j ) addi \$t1, \$t1, 1 # i++ j END # jump over ELSE ELSE: addi \$t2, \$t2, -1 # j-- END: add \$t2, \$t2, \$t1 # j += i

16 A trick with if statements Use flow charts to help you sort out the control flow of the code: if ( i == j ) i++; else j--; j += i; false beq else block true # \$t1 = i, \$t2 = j main: beq \$t1, \$t2, IF addi \$t2, \$t2, -1 j END IF: addi \$t1, \$t1, 1 END: add \$t2, \$t2, \$t1 jump if block end

17 Break

18 Multiple if conditions if ( i == j or i == k ) i++ ; // if-body else j-- ; // else-body j = i + k ;

19 Multiple if conditions if ( i == j or i == k ) i++ ; // if-body else j-- ; // else-body j = i + k ; Branch statement for each condition: # \$t1 = i, \$t2 = j, \$t3 = k main: beq \$t1, \$t2, IF # cond1: branch if ( i == j ) bne \$t1, \$t3, ELSE # cond2: branch if ( i!= k ) IF: addi \$t1, \$t1, 1 # if (i==j i==k) à i++ j END # jump over else ELSE: addi \$t2, \$t2, -1 # else-body: j-- END: add \$t2, \$t1, \$t3 # j = i + k

20 main: START: END: add \$t0, \$zero, \$zero addi \$t1, \$zero, 100 beq \$t0, \$t1, END addi \$t0, \$t0, 1 j START

21 Loops in MIPS Example of a simple loop, in assembly: main: START: END: add \$t0, \$zero, \$zero addi \$t1, \$zero, 100 beq \$t0, \$t1, END addi \$t0, \$t0, 1 j START which is the same as saying (in C): int i = 0; while (i < 100) { i++; }

22 Loops in MIPS for ( <init> ; <cond> ; <update> ) { <for body> } For loops (such as above) are usually implemented with the following structure: main: START: <init> if (!<cond>) branch to END <for-body> UPDATE: <update> jump to START END:

23 Loop example in MIPS for ( i=0 ; i<100 ; i++ ) { j = j + i; } This translates to: # \$t0 = i, \$t1 = j main: add \$t0, \$zero, \$zero # set i to 0 add \$t1, \$zero, \$zero # set j to 0 addi \$t9, \$zero, 100 # set \$t9 to 100 START: beq \$t0, \$t9, EXIT # branch if i==100 add \$t1, \$t1, \$t0 # j = j + i UPDATE: addi \$t0, \$t0, 1 # i++ j START EXIT: while loops are the same, without the initialization and update sections.

24 Homework Fibonacci sequence: ú How would you convert this into assembly? int n = 10; int f1 = 1, f2 = 1; while (n!= 0) { f1 = f1 + f2; f2 = f1 f2; n = n 1; } # result is f1

### Programming the processor

CSC258 Week 9 Logistics This week: Lab 7 is the last Logisim DE2 lab. Next week: Lab 8 will be assembly. For assembly labs you can work individually or in pairs. No matter how you do it, the important

### Question 0. Do not turn this page until you have received the signal to start. (Please fill out the identification section above) Good Luck!

CSC B58 Winter 2017 Final Examination Duration 2 hours and 50 minutes Aids allowed: none Last Name: Student Number: UTORid: First Name: Question 0. [1 mark] Read and follow all instructions on this page,

### MIPS Instruction Reference

Page 1 of 9 MIPS Instruction Reference This is a description of the MIPS instruction set, their meanings, syntax, semantics, and bit encodings. The syntax given for each instruction refers to the assembly

### ECE Exam I February 19 th, :00 pm 4:25pm

ECE 3056 Exam I February 19 th, 2015 3:00 pm 4:25pm 1. The exam is closed, notes, closed text, and no calculators. 2. The Georgia Tech Honor Code governs this examination. 3. There are 4 questions and

### F. Appendix 6 MIPS Instruction Reference

F. Appendix 6 MIPS Instruction Reference Note: ALL immediate values should be sign extended. Exception: For logical operations immediate values should be zero extended. After extensions, you treat them

### ECE 2035 Programming HW/SW Systems Fall problems, 7 pages Exam Two 23 October 2013

Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

### MIPS Reference Guide

MIPS Reference Guide Free at PushingButtons.net 2 Table of Contents I. Data Registers 3 II. Instruction Register Formats 4 III. MIPS Instruction Set 5 IV. MIPS Instruction Set (Extended) 6 V. SPIM Programming

### Q1: /30 Q2: /25 Q3: /45. Total: /100

ECE 2035(A) Programming for Hardware/Software Systems Fall 2013 Exam One September 19 th 2013 This is a closed book, closed note texam. Calculators are not permitted. Please work the exam in pencil and

### ECE 2035 Programming HW/SW Systems Spring problems, 6 pages Exam One 4 February Your Name (please print clearly)

Your Name (please print clearly) This exam will be conducted according to the Georgia Tech Honor Code. I pledge to neither give nor receive unauthorized assistance on this exam and to abide by all provisions

### EEM 486: Computer Architecture. Lecture 2. MIPS Instruction Set Architecture

EEM 486: Computer Architecture Lecture 2 MIPS Instruction Set Architecture EEM 486 Overview Instruction Representation Big idea: stored program consequences of stored program Instructions as numbers Instruction

### ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam One 19 September 2012

Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

### ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam One 22 September Your Name (please print clearly) Signed.

Your Name (please print clearly) This exam will be conducted according to the Georgia Tech Honor Code. I pledge to neither give nor receive unauthorized assistance on this exam and to abide by all provisions

### MIPS Instruction Set

MIPS Instruction Set Prof. James L. Frankel Harvard University Version of 7:12 PM 3-Apr-2018 Copyright 2018, 2017, 2016, 201 James L. Frankel. All rights reserved. CPU Overview CPU is an acronym for Central

### Computer Architecture. The Language of the Machine

Computer Architecture The Language of the Machine Instruction Sets Basic ISA Classes, Addressing, Format Administrative Matters Operations, Branching, Calling conventions Break Organization All computers

### TSK3000A - Generic Instructions

TSK3000A - Generic Instructions Frozen Content Modified by Admin on Sep 13, 2017 Using the core set of assembly language instructions for the TSK3000A as building blocks, a number of generic instructions

### ECE 2035 Programming HW/SW Systems Spring problems, 6 pages Exam Two 11 March Your Name (please print) total

Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

### ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam Two 23 October Your Name (please print clearly) Signed.

Your Name (please print clearly) This exam will be conducted according to the Georgia Tech Honor Code. I pledge to neither give nor receive unauthorized assistance on this exam and to abide by all provisions

### MIPS Instruction Format

MIPS Instruction Format MIPS uses a 32-bit fixed-length instruction format. only three different instruction word formats: There are Register format Op-code Rs Rt Rd Function code 000000 sssss ttttt ddddd

### Arithmetic for Computers

MIPS Arithmetic Instructions Cptr280 Dr Curtis Nelson Arithmetic for Computers Operations on integers Addition and subtraction; Multiplication and division; Dealing with overflow; Signed vs. unsigned numbers.

### The MIPS Instruction Set Architecture

The MIPS Set Architecture CPS 14 Lecture 5 Today s Lecture Admin HW #1 is due HW #2 assigned Outline Review A specific ISA, we ll use it throughout semester, very similar to the NiosII ISA (we will use

### ECE 2035 Programming HW/SW Systems Spring problems, 6 pages Exam Three 10 April 2013

Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

### ECE 2035 A Programming Hw/Sw Systems Fall problems, 8 pages Final Exam 8 December 2014

Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

### Examples of branch instructions

Examples of branch instructions Beq rs,rt,target #go to target if rs = rt Beqz rs, target #go to target if rs = 0 Bne rs,rt,target #go to target if rs!= rt Bltz rs, target #go to target if rs < 0 etc.

### Assembly Programming

Designing Computer Systems Assembly Programming 08:34:48 PM 23 August 2016 AP-1 Scott & Linda Wills Designing Computer Systems Assembly Programming In the early days of computers, assembly programming

### MIPS ISA. 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support

Components of an ISA EE 357 Unit 11 MIPS ISA 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support SUBtract instruc. vs. NEGate + ADD instrucs. 3. Registers accessible

### ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam Two 21 October 2016

Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

### Overview. Introduction to the MIPS ISA. MIPS ISA Overview. Overview (2)

Introduction to the MIPS ISA Overview Remember that the machine only understands very basic instructions (machine instructions) It is the compiler s job to translate your high-level (e.g. C program) into

### Midterm. Sticker winners: if you got >= 50 / 67

CSC258 Week 8 Midterm Class average: 4.2 / 67 (6%) Highest mark: 64.5 / 67 Tests will be return in office hours. Make sure your midterm mark is correct on MarkUs Solution posted on the course website.

### Flow of Control -- Conditional branch instructions

Flow of Control -- Conditional branch instructions You can compare directly Equality or inequality of two registers One register with 0 (>,

### ECE 2035 A Programming Hw/Sw Systems Fall problems, 8 pages Final Exam 9 December 2015

Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

### 101 Assembly. ENGR 3410 Computer Architecture Mark L. Chang Fall 2009

101 Assembly ENGR 3410 Computer Architecture Mark L. Chang Fall 2009 What is assembly? 79 Why are we learning assembly now? 80 Assembly Language Readings: Chapter 2 (2.1-2.6, 2.8, 2.9, 2.13, 2.15), Appendix

### M2 Instruction Set Architecture

M2 Instruction Set Architecture Module Outline Addressing modes. Instruction classes. MIPS-I ISA. High level languages, Assembly languages and object code. Translating and starting a program. Subroutine

### Reduced Instruction Set Computer (RISC)

Reduced Instruction Set Computer (RISC) Reduced Instruction Set Computer (RISC) Focuses on reducing the number and complexity of instructions of the machine. Reduced number of cycles needed per instruction.

### SPIM Instruction Set

SPIM Instruction Set This document gives an overview of the more common instructions used in the SPIM simulator. Overview The SPIM simulator implements the full MIPS instruction set, as well as a large

### Reduced Instruction Set Computer (RISC)

Reduced Instruction Set Computer (RISC) Focuses on reducing the number and complexity of instructions of the ISA. RISC Goals RISC: Simplify ISA Simplify CPU Design Better CPU Performance Motivated by simplifying

### ECE 2035 A Programming Hw/Sw Systems Spring problems, 8 pages Final Exam 29 April 2015

Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

### CSc 256 Midterm 2 Spring 2012

CSc 256 Midterm 2 Spring 2012 NAME: 1a) You are given this MIPS assembly language instruction (i.e., pseudo- instruction): ble \$12, 0x20004880, there Translate this MIPS instruction to an efficient sequence

### ECE 2035 Programming Hw/Sw Systems Fall problems, 10 pages Final Exam 9 December 2013

Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

### CSc 256 Midterm 2 Fall 2011

CSc 256 Midterm 2 Fall 2011 NAME: 1a) You are given a MIPS branch instruction: x: beq \$12, \$0, y The address of the label "y" is 0x400468. The memory location at "x" contains: address contents 0x40049c

### Mips Code Examples Peter Rounce

Mips Code Examples Peter Rounce P.Rounce@cs.ucl.ac.uk Some C Examples Assignment : int j = 10 ; // space must be allocated to variable j Possibility 1: j is stored in a register, i.e. register \$2 then

EE 357 Unit 11 MIPS ISA Components of an ISA 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support SUBtract instruc. vs. NEGate + ADD instrucs. 3. Registers accessible

### ECE232: Hardware Organization and Design. Computer Organization - Previously covered

ECE232: Hardware Organization and Design Part 6: MIPS Instructions II http://www.ecs.umass.edu/ece/ece232/ Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Computer Organization

### Lec 10: Assembler. Announcements

Lec 10: Assembler Kavita Bala CS 3410, Fall 2008 Computer Science Cornell University Announcements HW 2 is out Due Wed after Fall Break Robot-wide paths PA 1 is due next Wed Don t use incrementor 4 times

### Outline. EEL-4713 Computer Architecture Multipliers and shifters. Deriving requirements of ALU. MIPS arithmetic instructions

Outline EEL-4713 Computer Architecture Multipliers and shifters Multiplication and shift registers Chapter 3, section 3.4 Next lecture Division, floating-point 3.5 3.6 EEL-4713 Ann Gordon-Ross.1 EEL-4713

### Project Part A: Single Cycle Processor

Curtis Mayberry Andrew Kies Mark Monat Iowa State University CprE 381 Professor Joseph Zambreno Project Part A: Single Cycle Processor Introduction The second part in the three part MIPS Processor design

### ECE 2035 A Programming Hw/Sw Systems Fall problems, 10 pages Final Exam 14 December 2016

Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

### CSc 256 Midterm (green) Fall 2018

CSc 256 Midterm (green) Fall 2018 NAME: Problem 1 (5 points): Suppose we are tracing a C/C++ program using a debugger such as gdb. The code showing all function calls looks like this: main() { bat(5);

### Computer Architecture Experiment

Computer Architecture Experiment Jiang Xiaohong College of Computer Science & Engineering Zhejiang University Architecture Lab_jxh 1 Topics 0 Basic Knowledge 1 Warm up 2 simple 5-stage of pipeline CPU

### CS 61c: Great Ideas in Computer Architecture

MIPS Functions July 1, 2014 Review I RISC Design Principles Smaller is faster: 32 registers, fewer instructions Keep it simple: rigid syntax, fixed instruction length MIPS Registers: \$s0-\$s7,\$t0-\$t9, \$0

### 5/17/2012. Recap from Last Time. CSE 2021: Computer Organization. The RISC Philosophy. Levels of Programming. Stored Program Computers

CSE 2021: Computer Organization Recap from Last Time load from disk High-Level Program Lecture-2 Code Translation-1 Registers, Arithmetic, logical, jump, and branch instructions MIPS to machine language

### Recap from Last Time. CSE 2021: Computer Organization. Levels of Programming. The RISC Philosophy 5/19/2011

CSE 2021: Computer Organization Recap from Last Time load from disk High-Level Program Lecture-3 Code Translation-1 Registers, Arithmetic, logical, jump, and branch instructions MIPS to machine language

### Computer Architecture. MIPS Instruction Set Architecture

Computer Architecture MIPS Instruction Set Architecture Instruction Set Architecture An Abstract Data Type Objects Registers & Memory Operations Instructions Goal of Instruction Set Architecture Design

### CISC 662 Graduate Computer Architecture. Lecture 4 - ISA

CISC 662 Graduate Computer Architecture Lecture 4 - ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,

### Assembly Language. Prof. Dr. Antônio Augusto Fröhlich. Sep 2006

Sep 2006 Prof. Antônio Augusto Fröhlich (http://www.lisha.ufsc.br) 33 Assembly Language Prof. Dr. Antônio Augusto Fröhlich guto@lisha.ufsc.br http://www.lisha.ufsc.br/~guto Sep 2006 Sep 2006 Prof. Antônio

### Number Systems and Their Representations

Number Representations Cptr280 Dr Curtis Nelson Number Systems and Their Representations In this presentation you will learn about: Representation of numbers in computers; Signed vs. unsigned numbers;

### CSc 256 Final Fall 2016

CSc 256 Final Fall 2016 NAME: Problem 1 (25 points) Translate the C/C++ function func() into MIPS assembly language. The prototype is: void func(int arg0, int *arg1); arg0-arg1 are in \$a0- \$a1 respectively.

### CISC 662 Graduate Computer Architecture. Lecture 4 - ISA MIPS ISA. In a CPU. (vonneumann) Processor Organization

CISC 662 Graduate Computer Architecture Lecture 4 - ISA MIPS ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,

### INSTRUCTION SET COMPARISONS

INSTRUCTION SET COMPARISONS MIPS SPARC MOTOROLA REGISTERS: INTEGER 32 FIXED WINDOWS 32 FIXED FP SEPARATE SEPARATE SHARED BRANCHES: CONDITION CODES NO YES NO COMPARE & BR. YES NO YES A=B COMP. & BR. YES

### CSc 256 Final Spring 2011

CSc 256 Final Spring 2011 NAME: Problem1: Convertthedecimalfloatingpointnumber 4.3toa32 bitfloat(inbinary)inieee 754standardrepresentation.Showworkforpartialcredit.10points Hint:IEEE754formatfor32 bitfloatsconsistsofs

### A General-Purpose Computer The von Neumann Model. Concocting an Instruction Set. Meaning of an Instruction. Anatomy of an Instruction

page 1 Concocting an Instruction Set Nerd Chef at work. move flour,bowl add milk,bowl add egg,bowl move bowl,mixer rotate mixer... A General-Purpose Computer The von Neumann Model Many architectural approaches

### EE108B Lecture 3. MIPS Assembly Language II

EE108B Lecture 3 MIPS Assembly Language II Christos Kozyrakis Stanford University http://eeclass.stanford.edu/ee108b 1 Announcements Urgent: sign up at EEclass and say if you are taking 3 or 4 units Homework

### Computer Organization & Design

Computer Organization & Design Peng Liu ( 刘鹏 ) College of Information Science & Electronic Engineering Zhejiang University, Hangzhou 310027, China liupeng@zju.edu.cn Lecture 2 MIPS Instruction Set Architecture

Adventures in Assembly Land What is an Assembler ASM Directives ASM Syntax Intro to SPIM Simple examples L6 Simulator 1 A Simple Programming Task Add the numbers 0 to 4 10 = 0 + 1 + 2 + 3 + 4 In C : int

### Concocting an Instruction Set

Concocting an Instruction Set Nerd Chef at work. move flour,bowl add milk,bowl add egg,bowl move bowl,mixer rotate mixer... Read: Chapter 2.1-2.7 L03 Instruction Set 1 A General-Purpose Computer The von

### MIPS%Assembly% E155%

MIPS%Assembly% E155% Outline MIPS Architecture ISA Instruction types Machine codes Procedure call Stack 2 The MIPS Register Set Name Register Number Usage \$0 0 the constant value 0 \$at 1 assembler temporary

### MIPS Assembly Language. Today s Lecture

MIPS Assembly Language Computer Science 104 Lecture 6 Homework #2 Midterm I Feb 22 (in class closed book) Outline Assembly Programming Reading Chapter 2, Appendix B Today s Lecture 2 Review: A Program

### Today s Lecture. MIPS Assembly Language. Review: What Must be Specified? Review: A Program. Review: MIPS Instruction Formats

Today s Lecture Homework #2 Midterm I Feb 22 (in class closed book) MIPS Assembly Language Computer Science 14 Lecture 6 Outline Assembly Programming Reading Chapter 2, Appendix B 2 Review: A Program Review:

### Review. Lecture #9 MIPS Logical & Shift Ops, and Instruction Representation I Logical Operators (1/3) Bitwise Operations

CS6C L9 MIPS Logical & Shift Ops, and Instruction Representation I () inst.eecs.berkeley.edu/~cs6c CS6C : Machine Structures Lecture #9 MIPS Logical & Shift Ops, and Instruction Representation I 25-9-28

### Final Project: MIPS-like Microprocessor

Final Project: MIPS-like Microprocessor Objective: The objective of this project is to design, simulate, and implement a simple 32-bit microprocessor with an instruction set that is similar to a MIPS.

### MIPS Assembly Language

MIPS Assembly Language Chapter 15 S. Dandamudi Outline MIPS architecture Registers Addressing modes MIPS instruction set Instruction format Data transfer instructions Arithmetic instructions Logical/shift/rotate/compare

### Concocting an Instruction Set

Concocting an Instruction Set Nerd Chef at work. move flour,bowl add milk,bowl add egg,bowl move bowl,mixer rotate mixer... Read: Chapter 2.1-2.6 L04 Instruction Set 1 A General-Purpose Computer The von

### RTL Model of a Two-Stage MIPS Processor

RTL Model of a Two-Stage MIPS Processor 6.884 Laboratory February 4, 5 - Version 45 Introduction For the first lab assignment, you are to write an RTL model of a two-stage pipelined MIPS processor using

### ECE 15B Computer Organization Spring 2010

ECE 15B Computer Organization Spring 2010 Dmitri Strukov Lecture 7: Procedures I Partially adapted from Computer Organization and Design, 4 th edition, Patterson and Hennessy, and classes taught by and

### CPS311 - COMPUTER ORGANIZATION. A bit of history

CPS311 - COMPUTER ORGANIZATION A Brief Introduction to the MIPS Architecture A bit of history The MIPS architecture grows out of an early 1980's research project at Stanford University. In 1984, MIPS computer

### Review: MIPS Organization

1 MIPS Arithmetic Review: MIPS Organization Processor Memory src1 addr 5 src2 addr 5 dst addr 5 write data Register File registers (\$zero - \$ra) bits src1 data src2 data read/write addr 1 1100 2 30 words

### CS61C Machine Structures. Lecture 12 - MIPS Procedures II & Logical Ops. 2/13/2006 John Wawrzynek. www-inst.eecs.berkeley.

CS61C Machine Structures Lecture 12 - MIPS Procedures II & Logical Ops 2/13/2006 John Wawrzynek (www.cs.berkeley.edu/~johnw) www-inst.eecs.berkeley.edu/~cs61c/ CS 61C L12 MIPS Procedures II / Logical (1)

### The MIPS R2000 Instruction Set

The MIPS R2000 Instruction Set Arithmetic and Logical Instructions In all instructions below, Src2 can either be a register or an immediate value (a 16 bit integer). The immediate forms of the instructions

### Instruction Set Architecture of. MIPS Processor. MIPS Processor. MIPS Registers (continued) MIPS Registers

CSE 675.02: Introduction to Computer Architecture MIPS Processor Memory Instruction Set Architecture of MIPS Processor CPU Arithmetic Logic unit Registers \$0 \$31 Multiply divide Coprocessor 1 (FPU) Registers

### MIPS Assembly Language Programming

MIPS Assembly Language Programming Bob Britton Chapter 1 The MIPS Architecture My objective in teaching assembly language is to introduce students to the fundamental concepts of contemporary computer architecture.

### ece4750-parc-isa.txt

========================================================================== PARC Instruction Set Architecture ========================================================================== # Author : Christopher

### MACHINE LANGUAGE. To work with the machine, we need a translator.

LECTURE 2 Assembly MACHINE LANGUAGE As humans, communicating with a machine is a tedious task. We can t, for example, just say add this number and that number and store the result here. Computers have

### Digital System Design II

Digital System Design II 数字系统设计 II Peng Liu ( 刘鹏 ) Dept. of Info. Sci. & Elec. Engg. Zhejiang University liupeng@zju.edu.cn Lecture 2 MIPS Instruction Set Architecture 2 Textbook reading MIPS ISA 2.1-2.4

### ECE468 Computer Organization & Architecture. MIPS Instruction Set Architecture

ECE468 Computer Organization & Architecture MIPS Instruction Set Architecture ECE468 Lec4.1 MIPS R2000 / R3000 Registers 32-bit machine --> Programmable storage 2^32 x bytes 31 x 32-bit GPRs (R0 = 0) 32

### CPU Design for Computer Integrated Experiment

CPU Design for Computer Integrated Experiment Shan Lu, Guangyao Li, Yijianan Wang CEIE, Tongji University, Shanghai, China Abstract - Considering the necessity and difficulty of designing a CPU for students,

### Chapter 2. Computer Abstractions and Technology. Lesson 4: MIPS (cont )

Chapter 2 Computer Abstractions and Technology Lesson 4: MIPS (cont ) Logical Operations Instructions for bitwise manipulation Operation C Java MIPS Shift left >>> srl Bitwise

### ECE260: Fundamentals of Computer Engineering

MIPS Instruction Set James Moscola Dept. of Engineering & Computer Science York College of Pennsylvania Based on Computer Organization and Design, 5th Edition by Patterson & Hennessy MIPS Registers MIPS

### software hardware Which is easier to change/design???

CS152 Computer Architecture and Engineering Lecture 2 Review of MIPS ISA and Performance January 27, 2003 John Kubiatowicz (http.cs.berkeley.edu/~kubitron) lecture slides: http://inst.eecs.berkeley.edu/~cs152/

### Midterm. CS64 Spring Midterm Exam

Midterm LAST NAME FIRST NAME PERM Number Instructions Please turn off all pagers, cell phones and beepers. Remove all hats & headphones. Place your backpacks, laptops and jackets at the front. Sit in every

### Computer Architecture Instruction Set Architecture part 2. Mehran Rezaei

Computer Architecture Instruction Set Architecture part 2 Mehran Rezaei Review Execution Cycle Levels of Computer Languages Stored Program Computer/Instruction Execution Cycle SPIM, a MIPS Interpreter

### Concocting an Instruction Set

Concocting an Instruction Set Nerd Chef at work. move flour,bowl add milk,bowl add egg,bowl move bowl,mixer rotate mixer... Read: Chapter 2.1-2.7 L04 Instruction Set 1 A General-Purpose Computer The von

### IMPLEMENTATION MICROPROCCESSOR MIPS IN VHDL LAZARIDIS DIMITRIS.

VLSI Design Project Report IMPLEMENTATION MICROPROCCESSOR MIPS IN VHDL LAZARIDIS DIMITRIS (thejimi39@hotmail.com) ATHENS 2012 ABSTRACT Implementation microprocessor Mips in hardware, supporting almost

### Exam in Computer Engineering

Exam in Computer Engineering Kurskod D0013E/SMD137/SMD082/SMD066 Tentamensdatum 2010-10-29 Skrivtid 14.00-18.00 Maximalt resultat 50 poäng Godkänt resultat 25 poäng Jourhavande lärare Andrey Kruglyak Tel

### Some material adapted from Mohamed Younis, UMBC CMSC 611 Spr 2003 course slides Some material adapted from Hennessy & Patterson / 2003 Elsevier

Some material adapted from Mohamed Younis, UMBC CMSC 611 Spr 2003 course slides Some material adapted from Hennessy & Patterson / 2003 Elsevier Science To command a computer's hardware, you must speak

### Part II Instruction-Set Architecture. Jan Computer Architecture, Instruction-Set Architecture Slide 1

Part II Instruction-Set Architecture Jan. 211 Computer Architecture, Instruction-Set Architecture Slide 1 MiniMIPS Instruction Formats op rs rt 31 25 2 15 1 5 R 6 bits 5 bits 5 bits 5 bits I J Opcode Source

### CMPE324 Computer Architecture Lecture 2

CMPE324 Computer Architecture Lecture 2.1 What is Computer Architecture? Software Hardware Application (Netscape) Operating System Compiler (Unix; Assembler Windows 9x) Processor Memory Datapath & Control

### ECE260: Fundamentals of Computer Engineering

MIPS Instruction Set James Moscola Dept. of Engineering & Computer Science York College of Pennsylvania Based on Computer Organization and Design, 5th Edition by Patterson & Hennessy MIPS Registers MIPS

### Review: Organization. CS152 Computer Architecture and Engineering Lecture 2. Review of MIPS ISA and Design Concepts

Review: Organization Processor Input CS52 Computer Architecture and Engineering Lecture 2 Control Review of MIPS ISA and Design Concepts path Output January 26, 24 John Kubiatowicz (http.cs.berkeley.edu/~kubitron)

### Instruction Set Architecture part 1 (Introduction) Mehran Rezaei

Instruction Set Architecture part 1 (Introduction) Mehran Rezaei Overview Last Lecture s Review Execution Cycle Levels of Computer Languages Stored Program Computer/Instruction Execution Cycle SPIM, a